User's Guide
SLVU828A – January 2013 – Revised June 2014
Using the TPS43060 Boost Evaluation Module (EVM)
This user's guide contains information for the TPS43060EVM-199 evaluation module (PWR199) including
the performance specifications, schematic, and the bill of materials.
1
2
3
4
Contents
Introduction ................................................................................................................... 3
Test Setup and Results ..................................................................................................... 7
Bill of Materials ............................................................................................................. 13
Board Layout ................................................................................................................ 14
List of Figures
1
TPS43060EVM-199 Schematic ............................................................................................ 5
2
Efficiency Versus Load Current ............................................................................................ 8
3
Light Load Efficiency Versus Load Current
4
5
6
7
8
9
10
11
12
13
14
15
16
.............................................................................. 8
Regulation Versus Output Current ........................................................................................ 8
Regulation Versus Input Voltage .......................................................................................... 8
Load Transient Response ................................................................................................. 9
Loop Response .............................................................................................................. 9
Output Voltage Ripple CCM ............................................................................................. 10
Output Voltage Ripple DCM ............................................................................................. 10
Output Voltage Ripple Pulse Skip Mode ................................................................................ 10
Input Voltage Ripple CCM ................................................................................................ 11
Input Voltage Ripple DCM ................................................................................................ 11
Start Up Relative to VIN ................................................................................................... 11
Start Up Relative to EN .................................................................................................... 11
Shutdown Relative to VIN .................................................................................................. 12
Shutdown Relative to EN .................................................................................................. 12
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17
Gate-Drive Signals ......................................................................................................... 12
18
TPS43060EVM-199 Top Assembly and Silkscreen ................................................................... 14
19
TPS43060EVM-199 Top-Side Layout ................................................................................... 15
20
TPS43060EVM-199 Layer 2 Layout ..................................................................................... 15
21
TPS43060EVM-199 Layer 3 Layout ..................................................................................... 16
22
TPS43060EVM-199 Bottom-Side Layout ............................................................................... 16
List of Tables
2
1
Input Voltage and Output Current Summary ............................................................................. 3
2
TPS43060EVM-199 Performance Specification Summary............................................................. 4
3
EVM Connectors and Test points
4
TPS43060EVM-199 Bill of Materials..................................................................................... 13
.........................................................................................
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Introduction
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1
Introduction
This user's guide contains background information for the TPS43060 as well as support documentation for
the TPS43060EVM-199 evaluation module (PWR199). Also included are the performance specifications,
schematic, and the bill of materials for the EVM.
1.1
Background
The TPS43060 is a DC-DC synchronous boost controller designed for a maximum output voltage of 58 V
from an input voltage source of 4.5 V to 38 V. It has a 7.5-V gate-drive supply optimized for use with
standard threshold MOSFETs. Rated input voltage and output current range for the evaluation module are
given in Table 1. This evaluation module is designed to demonstrate the high efficiency and high power
possible when designing with the TPS43060 controller. The switching frequency is externally set at a
nominal 300 kHz. The gate-drive circuitry for the external high-side and low-side FET is incorporated
inside the TPS43060 package. PWR199 uses the Infineon BSC123N08NS3G for both the high-side and
low-side MOSFETs. External inductor DCR or resistor current sensing allows for an adjustable cycle-bycycle current limit. The compensation components are external to the integrated circuit (IC), and an
external resistor divider allows for an adjustable output voltage. Additionally, the TPS43060 provides an
adjustable undervoltage lockout with hysteresis through an external resistor divider, adjustable slow-start
time with an external capacitor and a power good output voltage indicator. The absolute maximum input
voltage for the PWR199 is 38 V.
Table 1. Input Voltage and Output Current Summary
EVM
Input Voltage Range
Output Current Range
TPS43060EVM-199
VIN = 10 V to 38 V
IOUT = 0 A to 3 A
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Performance Specification Summary
A summary of the EVM performance specifications is provided in Table 2. Specifications are given for an
input voltage of VIN = 24 V and an output voltage of 40 V, unless otherwise specified. This EVM is
designed and tested for VIN = 10 V to 38 V. The ambient temperature is 25°C for all measurements,
unless otherwise noted.
Table 2. TPS43060EVM-199 Performance Specification Summary
Specification
Test Conditions
VIN voltage range
MIN
TYP
MAX
10
24
38
Output voltage set point
40
V
V
Output current range
VIN = 15 V to 38 V
0
3
A
Output current range
VIN = 10 V
0
2
A
Line regulation
VIN = 10 V to 35 V, IOUT = 2 A
±0.1%
Load regulation
IOUT = 0.001 A to 3 A
±0.1%
Load transient response
IOUT = 0.75 A to 2.25 A
Voltage change
Recovery time
IOUT = 2.25 A to 0.75 A
Voltage change
Recovery time
–700
mV
1
ms
600
mV
1
ms
4.7
kHz
Loop bandwidth
IOUT = 3 A
Phase margin
IOUT = 3 A
64
°
Input voltage ripple
IOUT = 3 A
100
mVpp
Output voltage ripple
IOUT = 3 A
350
mVpp
Output rise time
Operating frequency
Peak efficiency
4
Unit
IOUT = 3 A
25
ms
300
kHz
97.7%
DCM threshold
660
mA
Pulse skipping threshold
3.5
mA
No load input current
1.3
mA
UVLO start threshold
9.66
V
UVLO stop threshold
7.92
V
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1.3
Schematic
Figure 1 is the schematic for the EVM.
R16
10m
J5
VIN
VIN
R17
VIN: 10V-38V
10m
TP8
2
L1
R18
15uH
J6
VIN
1
GND
2
+
TP9
C13
1
C14
C15
C16
10uF
10uF
10uF
1
R14
10
R13
10
R15
1
ISNS-
ISNS+
J7
J1
GND
TP2
R2
VCC
D
TP4
G
TP5
2
C2
C3
C4
3
10uF
10uF
10uF
R4
3
FB
R7
4
SS
HDRV
FB
BOOT
VCC
PGND
12.1k
0.1uF 1500pF
6
7
8
D1
11
68uF
J3
G
TP6
R6
GND
49.9
S
R19 2.0
VCC
C10
C6
R8
1
348k
FB
C12 100pF
R12
GND
1
Q2
BSC123N08NS3G
9
R9
R10
VIN
VOUT
1
C17 +
4.7uF
5
C9
+
TP7
12
10
C5
2
D
0.1uF
SW
U1
TPS43060RTE
COMP
C8
0.033uF
EN
RT/CLK
LDRV
2
C1
13
VIN
1
C7
AGND
PWPD
191k
14
15
PGOOD
17 16
R5
47.5k
ISNS+
OFF
TP3
J2
ISNS-
EN
Q1
BSC123N08NS3G
100k
357k
1
ON
TP1
S
JP1
0
R1
VIN
R3
VOUT
40V @ 3A
1
0
11.0k
C11
0.1uF
R11
J4
ISNS-
ISNS+
0
1
Not Populated
2
For DCR sensing, open R14 and short R15, R16, R17 and R18. For resistor sensing, open R15.
For Split Rail application, open R11.
VBIAS (OPTIONAL)
Figure 1. TPS43060EVM-199 Schematic
1.4
Modifications
The EVM is designed to provide access to the features of the TPS43060. Some modifications can be
made to this module. For further details please see the product data sheet.
1.4.1
Output Voltage Set Point
To change the output voltage of the EVM, it is necessary to change the value of resistor R8. The value of
R8 for a specific output voltage can be calculated using Equation 1, where RHS is R8, RLS is R9 and VFB is
1.22 V. It is recommended to use a value of R9 near 10 kΩ.
V
VFB
RHS RLS u OUT
VFB
(1)
Note: VIN must be in a range so the minimum on-time is greater than the typical 100 ns and the minimum
off-time is greater than the largest of typical 250 ns and 5% of the switching period.
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Current Sensing
The default configuration of the EVM is for resistor current sensing. R13 and R14 are populated with R15
open. When adjusting the input voltage, output voltage or desired maximum output voltage, the current
sense resistors R16 and R17 may need to be adjusted. The peak inductor current should first be
calculated with Equation 2. Equation 3 is then used to calculate the required current sense resistor where
VCStyp is the current sense threshold. VCStyp should be determined from the TPS43060 data sheet with
the maximum duty cycle in the application. Ensure the current sense resistor is rated for the expected
power dissipation. For inductor DCR current sensing, R14 should be left open while R15, R16, R17 and
R18 are shorted.
V
VIN min
VIN minu OUT
IOUT
VOUT
ILpeak
V
VIN min
2 u L u fSW
1 OUT
VOUT
(2)
RCS
1.4.3
VCS typ
1.2 u ILpeak
(3)
Slow-Start Time
Adjust the slow-start time by changing the value of C7. Equation 4 can be used to calculate the required
capacitance based on a desired slow-start time, tSS. ISS is the charging current of 5-µA typical and VREF is
the internal reference voltage of 1.22 V. The EVM is set for a slow-start time of 25 ms using C7 = 0.1 µF.
t SS u ISS
CSS
VREF
(4)
1.4.4
Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R3 and R4. The EVM is set for a start
voltage of 9.66 V and stop voltage of 7.92 V, using R3 = 357 kΩ and R4 = 47.5 kΩ. Use Equation 5 and
Equation 6 to calculate the required resistor values for R3 and R4, respectively, for different start and stop
voltages. The typical values of the constants in the two equations are as follows: VEN_DIS = 1.14 V, VEN_ON =
1.21 V, IEN_pup = 1.8 µA, and IEN_hys = 3.2 µA.
§ VEN _ DIS ·
VSTART u ¨
¸ VSTOP
¨ VEN _ ON ¸
©
¹
RUVLO_ H
§
VEN _ DIS ·
IEN _ pup u ¨ 1
¸ I
¨
VEN _ ON ¸¹ EN _ hys
©
(5)
RUVLO_ H u VEN _ DIS
RUVLO_ L
VSTOP VEN _ DIS RUVLO _ H u IEN _ pup IEN _ hys
1.4.5
(6)
Input Voltage Rails
The EVM is designed to accommodate different input voltage levels for the power stage and control logic.
In the default configuration, the VIN inputs connected with R11 populated with a 0-Ω resistor. The input
voltage is supplied to J6. If desired, the two input voltage rails may be separated by unpopulating R11.
The control logic input voltage can be supplied to J4 and the power stage input voltage to J6.
1.4.6
Further Modification
Changing the input and output of conditions of the EVM will impact the design. It may also be necessary
to modify the inductor, output capacitor and compensation components for the desired performance in the
application. Please see the data sheet or the excel design spreadsheet located in the product folder for
details.
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2
Test Setup and Results
This section describes how to properly connect, set up, and use the EVM. The section also includes test
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up and shutdown.
2.1
Input/Output Connections
This EVM includes I/O connectors and test points as shown in Table 3. A power supply capable of
supplying at least 12 A must be connected to J6 through a pair of 20-AWG wires. The load must be
connected to J2 through a pair of 20-AWG wires. The maximum load-current capability must be 3 A. Wire
lengths must be minimized to reduce losses in the wires. If any modification is done to the EVM design, an
input supply and load rated for the new design are required. Test point TP8 provides a connection to
monitor the VIN input voltages with TP9 providing a convenient ground reference. TP3 is used to monitor
the output voltage with TP4 as the ground reference.
Table 3. EVM Connectors and Test points
Reference Designator
Function
J1
2-pin header for VOUT voltage connections
J2
VOUT, 40 V at 3-A maximum
J3
2-pin header for GND connections
J4
2-pin header for optional VBIAS input voltage connections (see Section 1.4.5)
J5
2-pin header for VIN input voltage connections
J6
VIN (see Table 1 for VIN range)
J7
2-pin header for GND connections
JP1
3-pin header for EN jumper. Install jumper from pins 1-2 to enable or pins 2-3 to disable.
TP1
PGOOD test point for power good output voltage indicator
TP2
HDRV test point for high-side gate-drive voltage
TP3
VOUT test point at VOUT connector
TP4
GND test point at VOUT connector
TP5
SW test point for switch node voltage
TP6
Test point between voltage divider network and output used for loop response measurements
TP7
LDRV test point for low-side gate-drive voltage
TP8
VIN test point at VIN connector
TP9
GND test point at VIN connector
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Efficiency
With the nominal VIN of 24 V, the efficiency of this EVM peaks at a load current of about 3 A, and then
decreases as the load current increases towards maximum load. Figure 2 shows the efficiency for the
EVM up to current limit with 1-V input and up to a 5-A load with 24-V and 38-V input. Figure 3 shows the
light load efficiency using a semi-log scale. Measurements are taken at ambient temperature of 25°C. The
efficiency may be lower at higher ambient temperatures due to temperature variation in the drain-to-source
resistance of the selected external MOSFETs.
90
96
80
94
70
Efficiency - %
100
98
Efficiency - %
100
92
90
VOUT = 40V, fsw = 300kHz
88
86
60
50
30
Vin = 10V
84
80
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Output Current - A
Vin = 38V
0
0.001
5
0.01
0.1
1
Output Current - A
C001
Figure 2. Efficiency Versus Load Current
2.3
Vin = 24V
10
Vin = 38V
0
Vin = 10V
20
Vin = 24V
82
VOUT = 40V, fsw = 300kHz
40
C002
Figure 3. Light Load Efficiency Versus Load Current
Output Voltage Regulation
The load regulation for the EVM is shown in Figure 4. The line regulation for the EVM is shown in
Figure 5. Measurements are given for an ambient temperature of 25°C.
0.1
VOUT = 40V, fsw = 300kHz
VIN = 24V
Output VOltage Deviation - %
Output Voltage Deviation - %
0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
0.5
1
1.5
2
2.5
Output Current - A
VOUT = 40V, fsw = 300kHz
IOUT = 2A
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
5
10
Using the TPS43060 Boost Evaluation Module (EVM)
15
20
25
30
Input Voltage - V
C002
Figure 4. Regulation Versus Output Current
8
3
0.08
35
C004
Figure 5. Regulation Versus Input Voltage
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2.4
Load Transients and Loop Response
C4: IOUT (1.0 A/div)
60
180
40
120
Gain - dB
20
60
Phase
0
0
Gain
-20
-60
-40
-120
VOUT = 40V, VIN = 24V
IOUT = 3A
-60
10
100
1000
10000
100000
-180
1000000
Frequency - Hz
C3: VOUT ac coupled (500 mV/div)
Phase - deg
The EVM response to load transients is shown in Figure 6. The current step is from 25% to 75% of
maximum rated load at nominal 24-V input. Total peak-to-peak voltage variation is as shown, including
ripple and noise on the output. The EVM loop-response characteristics are shown in Figure 7. Gain and
phase plots are shown for nominal VIN voltage of 24 V. Load current for the measurement is 3 A.
C005
Figure 7. Loop Response
Time: 500 µs/div
Figure 6. Load Transient Response
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Output Voltage Ripple
The EVM continuous conduction mode (CCM) output voltage ripple is shown in Figure 8. The output
current is the rated full load of 3 A and nominal VIN of 24 V. The voltage ripple is measured directly across
the output capacitors with a short ground lead. The discontinuous conduction mode (DCM) output voltage
ripple is shown in Figure 9. The output current is 0.3 A and nominal VIN of 24 V. The pulse skip mode
output voltage ripple is shown in Figure 10. There is no external load on the output and nominal VIN of 24
V.
C1: SW (20.0 V/div)
C1: SW (20.0 V/div)
C4: IL (2.0 A/div)
C4: IL (2.0 A/div)
C3: VOUT ac coupled (200 mV/div)
C3: VOUT ac coupled (50 mV/div)
Time: 2.0 µs/div
Time: 2.0 µs/div
Figure 8. Output Voltage Ripple CCM
Figure 9. Output Voltage Ripple DCM
C1: SW (20.0 V/div)
C4: IL (500 mA/div)
C3: VOUT ac coupled (50 mV/div)
Time: 10.0 ms/div
Figure 10. Output Voltage Ripple Pulse Skip Mode
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2.6
Input Voltage Ripple
The EVM CCM input voltage ripple is shown in Figure 11. The output current is the rated full load of 3 A
and nominal VIN of 24 V. The voltage ripple is measured directly across the input capacitors. The DCM
input voltage ripple is shown in Figure 12. The output current is 0.3 A and nominal VIN of 24 V.
C1: SW (20.0 V/div)
C1: SW (20.0 V/div)
C4: IL (2.0 A/div)
C4: IL (2.0 A/div)
C3: VIN ac coupled (100 mV/div)
C3: VIN ac coupled (100 mV/div)
Time: 2.0 µs/div
Time: 2.0 µs/div
Figure 11. Input Voltage Ripple CCM
2.7
Figure 12. Input Voltage Ripple DCM
Start Up
The start up waveforms are shown in Figure 13 and Figure 14. The input voltage for these plots is the
nominal 24 V and the output has a 2.5-A resistive load. In Figure 13 the input voltage supply is turned on
and VIN begins rising. Both the VCC and VOUT rail initially rise with VIN. When the input reaches the
undervoltage lockout threshold set by the external resistor divider, the device can begin switching and the
output ramps up to the set value of 40 V with the slow-start voltage. PGOOD goes high when VOUT is in
regulation.
In Figure 14 the input voltage is applied with EN held low. The output voltage is a diode drop below the
input voltage and VCC is disabled. When EN is released, the start up sequence begins with VCC coming
into regulation and the output ramps up to the set value of 40 V. PGOOD goes high when VOUT is in
regulation.
C1: EN (5.00 V/div)
C1: VIN (10.0 V/div)
C2: VCC (5.00 V/div)
C2: VCC (5.00 V/div)
C3: VOUT (20.0 V/div)
C3: VOUT (20.0 V/div)
C4: PGOOD (5.00 V/div)
C4: PGOOD (5.00 V/div)
Time: 5.00 ms/div
Figure 13. Start Up Relative to VIN
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Figure 14. Start Up Relative to EN
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Shutdown
The shutdown waveforms are shown in Figure 15 and Figure 16. In Figure 15 the input voltage is
removed, and when the input falls below the undervoltage lockout threshold set by the EN resistor divider,
the TPS43060 shuts down, PGOOD is pulled low and the output falls to ground. The output has a 2.5-A
resistive load.
In Figure 16 the input voltage is held at 24 V with no load and EN is shorted to ground. When EN is
grounded, the TPS43060 is disabled, PGOOD is pulled low and the output voltage discharges to VIN.
C1: VIN (10.0 V/div)
C1: EN (5.00 V/div)
C3: VOUT (20.0 V/div)
C2: VCC (5.00 V/div)
C4: PGOOD (5.00 V/div)
C3: VOUT (20.0 V/div)
C4: PGOOD (5.00 V/div)
Time: 5.00 ms/div
Time: 5.00 ms/div
Figure 15. Shutdown Relative to VIN
2.9
Figure 16. Shutdown Relative to EN
Gate-Drive Signals
In Figure 17 the gate-drive signals for the high-side and low-side FETs can be seen with the switching
node are shown. The input voltage is 24 V and the output has a 3-A load.
C2: HDRV (20.0 V/div)
C1: SW (20.0 V/div)
C3: LDRV (5.00 V/div)
Time: 1.0 µs/div
Figure 17. Gate-Drive Signals
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Bill of Materials
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3
Bill of Materials
Table 4 presents the bill of materials for the EVM.
Table 4. TPS43060EVM-199 Bill of Materials
COUNT
RefDes
Value
Description
Size
Part Number
MFR
1
C5
68µF
Capacitor, Aluminum, 63V, 20%
0.406 x 0.406 inch
EEVFK1J680P
Panasonic
1
C6
4.7µF
Capacitor, Ceramic, 16V, X5R, 10%
0603
STD
STD
1
C8
1200pF
Capacitor, Ceramic, 10V, X5R, 10%
0603
STD
STD
1
C9
0.022µF
Capacitor, Ceramic, 10V, X5R, 10%
0603
STD
STD
0
C10
Open
Capacitor, Ceramic, 10V, X7R, 10%
0603
STD
STD
1
C12
100pF
Capacitor, Ceramic, 50V, X7R, 20%
0603
STD
STD
3
C1 C7 C11
0.1µF
Capacitor, Ceramic, 50V, X7R, 10%
0603
STD
STD
5
C2-4 C14-16
10µF
Capacitor, Ceramic, 50V, X7R, 10%
1210
STD
STD
0
C13 C17
Open
Capacitor
Multi sizes
Engineering Only
STD
1
D1
MBR1H100SFT3G
Diode, Schottky Power Rectifier, 1A, 100V
SOD-123LF
MBR1H100SFT3G
On Semi
5
J1 J3-5 J7
PEC02SAAN
Header, Male 2-pin, 100mil spacing
0.100 inch x 2
PEC02SAAN
Sullins
2
J2 J6
ED120/2DS
Terminal Block, 2-pin, 15-A, 5.1mm
0.40 x 0.35 inch
ED120/2DS
OST
1
JP1
PEC03SAAN
Header, Male 3-pin, 100mil spacing
0.100 inch x 3
PEC03SAAN
Sullins
1
L1
15µH
Inductor, Shielded Power, 14A, 9mΩ
15.2x16.2 mm
XAL1510-153
alt:74435571500
Coilcraft
alt:WE
2
Q1 Q2
BSC123N08NS3G
MOSFET, Nch, 80V, 55A, 12.3mΩ
TDSON-8
BSC123N08NS3G
Infineon
1
R1
100k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R3
357k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R4
47.5k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R5
191k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R6
49.9
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R7
15.4k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R8
348k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
R9
11.0k
Resistor, Chip, 1/16W, 1%
0603
STD
STD
0
R18
Open
Resistor, Chip, 1W, 1%
1206
STD
STD
0
R12 R15
Open
Resistor, Chip, 1/16W, 1%
0603
STD
STD
2
R13-14
10
Resistor, Chip, 1/16W, 1%
0603
STD
STD
2
R16-17
10m
Resistor, Chip, 1W, 1%
1206
STD
STD
3
R2 R10-11
0
Resistor, Chip, 1/16W, 1%
0603
STD
STD
1
SH1
Short jumper, 100mil
0.100 inch
929950-00
3M
2
TP4 TP9
5001
Test Point, Black, Thru Hole Color Keyed
0.100 x 0.100 inch
5001
Keystone
7
TP1-3 TP5-8
5000
Test Point, Red, Thru Hole Color Keyed
0.100 x 0.100 inch
5000
Keystone
1
U1
TPS43060RTE
IC, Wide VIN Current Mode Synchronous Boost
Controller
VQFN
TPS43060RTE
TI
1
--
PWR199
Any
Notes:
1. These assemblies are ESD sensitive, ESD precautions shall be observed.
PCB, 3.5 in x 2.1 in x 0.062 in
2. These assemblies must be clean and free from flux and all contaminants.
Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted.
All other components can be substituted with equivalent MFG's components.
SLVU828A – January 2013 – Revised June 2014
Submit Documentation Feedback
Using the TPS43060 Boost Evaluation Module (EVM)
Copyright © 2013–2014, Texas Instruments Incorporated
13
Board Layout
4
www.ti.com
Board Layout
This section provides a description of the EVM, board layout, and layer illustrations.
4.1
Layout
The board layout for the EVM is shown in Figure 18 through Figure 22. This design has 4 layers of 2-oz
copper.
The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are all other
components to allow the user to easily view, probe, and evaluate the TPS43060 control IC. The remaining
area is filled with ground. The remaining three layers have additional copper for VIN, VOUT, AGND, and
PGND connected with multiple vias. Additional copper is also connected to the sense resistor to aid with
thermal dissipation. The second internal layer and bottom layer contain signal routes. Four vias directly
under the TPS43060 device provide a thermal path from the top-side ground plane to the bottom-side and
internal AGND plane. Lastly, the layout guidelines should be followed for Q1 and Q2. Vias are placed near
both FETs to aid with thermal dissipation.
All noise-sensitive analog circuitry are placed as close as possible to the IC. The voltage divider network
ties to the output voltage at the point of regulation on the bottom layer, near the output capacitors. Q1 and
Q2 are placed as close as possible to the IC to keep the gate-drive traces as short as possible. The
output capacitors are placed next to Q1 and Q2 to limit the length of the high frequency switching current
path. The SW copper is kept as small as possible to limit radiated noise from the high-frequency switching
voltage node. The power pad is connected to the AGND pin and all noise-sensitive circuitry must use this
as the ground return path. The ground return for the power components are connected to the PGND pin.
The AGND and PGND are connected at one point near the PGND pin. The bypass capacitors for VIN and
VCC are placed next to their respective pins. The filter capacitor between ISNS+ and ISNS– is located
next to the pins to help filter out switching noise. An additional input bulk capacitor may be required (C13)
depending on the connection to the EVM from the input supply. See the product datasheet for all layout
recommendations.
TP1
TP1
J1
TPS43060EVM-199
R7 R7
U1 U1 R19
R9 R9
R12
R19
TP6 TP6 C10C10 C12C12C11C11R10
R10
LOOP
R8 R8 R12 R15 R15
TP7
R6
R14 R14
R6 R13
TP7
R16
R16
LDRV
TP8 TP8
VIN
R17 R17
C14 C15 C16
R18 R18
VOUT
C3
C4
Q2
C5
TP9 TP9
GND
C17
J2
J7
GND J7
TP5 TP5
SW
L1
R11
J2
C16
C15
C14
C13
GND
J3
C2
C5
R13
J6
R11
C6
C13
++
VIN
C4
D1
C3
1
C17
R1
R2 R2
C1 C1 D1
Q1
R4
C7
C7 R5
R5
C9 C9
C8 C8
TP2
C6
J5 VIN
10-38V
J6
1
J5
TP3 TP3
VOUT
+
R3
R1
PWR199 Rev. A
Q1
++
R3
R4
TP2
HDRV
VOUT J1
40V @ 3A
GND
PGOOD
C2
JP1
ON EN OFF
J4
VBIAS
(OPTIONAL)
1
JP1
Q2
J4
L1
TP4 TP4
GND
J3 GND
Figure 18. TPS43060EVM-199 Top Assembly and Silkscreen
14
Using the TPS43060 Boost Evaluation Module (EVM)
SLVU828A – January 2013 – Revised June 2014
Submit Documentation Feedback
Copyright © 2013–2014, Texas Instruments Incorporated
Board Layout
www.ti.com
Figure 19. TPS43060EVM-199 Top-Side Layout
Figure 20. TPS43060EVM-199 Layer 2 Layout
SLVU828A – January 2013 – Revised June 2014
Submit Documentation Feedback
Using the TPS43060 Boost Evaluation Module (EVM)
Copyright © 2013–2014, Texas Instruments Incorporated
15
Board Layout
www.ti.com
Figure 21. TPS43060EVM-199 Layer 3 Layout
Figure 22. TPS43060EVM-199 Bottom-Side Layout
16
Using the TPS43060 Boost Evaluation Module (EVM)
SLVU828A – January 2013 – Revised June 2014
Submit Documentation Feedback
Copyright © 2013–2014, Texas Instruments Incorporated
Board Layout
www.ti.com
4.2
Estimated Circuit Area
The estimated printed-circuit-board area by outlining the components and the routing between them is
1.86 in2 (1202 mm2). This area does not include test points or connectors. Also note, this design uses
0603 components for easy modifications and places all components on one layer so the area can be
reduced.
Revision History
Changes from Original (January 2013) to A Revision .................................................................................................... Page
•
Changed Table 4, L1 Part Number From: XAL1510-103 To: XAL1510-153..................................................... 13
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SLVU828A – January 2013 – Revised June 2014
Submit Documentation Feedback
Copyright © 2013–2014, Texas Instruments Incorporated
Revision History
17
ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR
EVALUATION MODULES
Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user
expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following:
1.
User agrees and acknowledges that EVMs are intended to be handled and used for feasibility evaluation only in laboratory and/or
development environments. Notwithstanding the foregoing, in certain instances, TI makes certain EVMs available to users that do not
handle and use EVMs solely for feasibility evaluation only in laboratory and/or development environments, but may use EVMs in a
hobbyist environment. All EVMs made available to hobbyist users are FCC certified, as applicable. Hobbyist users acknowledge, agree,
and shall comply with all applicable terms, conditions, warnings, and restrictions in this document and are subject to the disclaimer and
indemnity provisions included in this document.
2. Unless otherwise indicated, EVMs are not finished products and not intended for consumer use. EVMs are intended solely for use by
technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical
mechanical components, systems, and subsystems.
3. User agrees that EVMs shall not be used as, or incorporated into, all or any part of a finished product.
4. User agrees and acknowledges that certain EVMs may not be designed or manufactured by TI.
5. User must read the user's guide and all other documentation accompanying EVMs, including without limitation any warning or
restriction notices, prior to handling and/or using EVMs. Such notices contain important safety information related to, for example,
temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or
contact TI.
6. User assumes all responsibility, obligation, and any corresponding liability for proper and safe handling and use of EVMs.
7. Should any EVM not meet the specifications indicated in the user’s guide or other documentation accompanying such EVM, the EVM
may be returned to TI within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE
EXCLUSIVE WARRANTY MADE BY TI TO USER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR
STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. TI SHALL
NOT BE LIABLE TO USER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES RELATED TO THE
HANDLING OR USE OF ANY EVM.
8. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which EVMs might be or are used. TI currently deals with a variety of customers, and therefore TI’s arrangement with
the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services with respect to the handling or use of EVMs.
9. User assumes sole responsibility to determine whether EVMs may be subject to any applicable federal, state, or local laws and
regulatory requirements (including but not limited to U.S. Food and Drug Administration regulations, if applicable) related to its handling
and use of EVMs and, if applicable, compliance in all respects with such laws and regulations.
10. User has sole responsibility to ensure the safety of any activities to be conducted by it and its employees, affiliates, contractors or
designees, with respect to handling and using EVMs. Further, user is responsible to ensure that any interfaces (electronic and/or
mechanical) between EVMs and any human body are designed with suitable isolation and means to safely limit accessible leakage
currents to minimize the risk of electrical shock hazard.
11. User shall employ reasonable safeguards to ensure that user’s use of EVMs will not result in any property damage, injury or death,
even if EVMs should fail to perform as described or expected.
12. User shall be solely responsible for proper disposal and recycling of EVMs consistent with all applicable federal, state, and local
requirements.
Certain Instructions. User shall operate EVMs within TI’s recommended specifications and environmental considerations per the user’s
guide, accompanying documentation, and any other applicable requirements. Exceeding the specified ratings (including but not limited to
input and output voltage, current, power, and environmental ranges) for EVMs may cause property damage, personal injury or death. If
there are questions concerning these ratings, user should contact a TI field representative prior to connecting interface electronics including
input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate
operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the applicable EVM user's guide prior
to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During
normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained
at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors which can be identified using EVMs’ schematics located in the applicable EVM user's guide. When
placing measurement probes near EVMs during normal operation, please be aware that EVMs may become very warm. As with all
electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in
development environments should use EVMs.
Agreement to Defend, Indemnify and Hold Harmless. User agrees to defend, indemnify, and hold TI, its directors, officers, employees,
agents, representatives, affiliates, licensors and their representatives harmless from and against any and all claims, damages, losses,
expenses, costs and liabilities (collectively, "Claims") arising out of, or in connection with, any handling and/or use of EVMs. User’s
indemnity shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if EVMs fail to perform as
described or expected.
Safety-Critical or Life-Critical Applications. If user intends to use EVMs in evaluations of safety critical applications (such as life support),
and a failure of a TI product considered for purchase by user for use in user’s product would reasonably be expected to cause severe
personal injury or death such as devices which are classified as FDA Class III or similar classification, then user must specifically notify TI
of such intent and enter into a separate Assurance and Indemnity Agreement.
RADIO FREQUENCY REGULATORY COMPLIANCE INFORMATION FOR EVALUATION MODULES
Texas Instruments Incorporated (TI) evaluation boards, kits, and/or modules (EVMs) and/or accompanying hardware that is marketed, sold,
or loaned to users may or may not be subject to radio frequency regulations in specific countries.
General Statement for EVMs Not Including a Radio
For EVMs not including a radio and not subject to the U.S. Federal Communications Commission (FCC) or Industry Canada (IC)
regulations, TI intends EVMs to be used only for engineering development, demonstration, or evaluation purposes. EVMs are not finished
products typically fit for general consumer use. EVMs may nonetheless generate, use, or radiate radio frequency energy, but have not been
tested for compliance with the limits of computing devices pursuant to part 15 of FCC or the ICES-003 rules. Operation of such EVMs may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: For EVMs including a radio, the radio included in such EVMs is intended for development and/or
professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability in such EVMs
and their development application(s) must comply with local laws governing radio spectrum allocation and power limits for such EVMs. It is
the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations.
Any exceptions to this are strictly prohibited and unauthorized by TI unless user has obtained appropriate experimental and/or development
licenses from local regulatory authorities, which is the sole responsibility of the user, including its acceptable authorization.
U.S. Federal Communications Commission Compliance
For EVMs Annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications could void the user's authority to operate the equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at its own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
Industry Canada Compliance (English)
For EVMs Annotated as IC – INDUSTRY CANADA Compliant:
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs Including Radio Transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs Including Detachable Antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Canada Industry Canada Compliance (French)
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
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Important Notice for Users of EVMs Considered “Radio Frequency Products” in Japan
EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan.
If user uses EVMs in Japan, user is required by Radio Law of Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use EVMs only after user obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or
Use of EVMs only after user obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect
to EVMs. Also, do not transfer EVMs, unless user gives the same notice above to the transferee. Please note that if user does not
follow the instructions above, user will be subject to penalties of Radio Law of Japan.
http://www.tij.co.jp
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品の
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1.
2.
3.
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