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TPS43330-Q1, TPS43332-Q1
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
TPS4333x-Q1 Low IQ, Single Boost, Dual Synchronous Buck Controller
1 Features
2 Applications
•
•
•
1
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•
•
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•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Two Synchronous Buck Controllers
One Pre-Boost Controller
Input Range up to 40 V, (Transients up to 60 V),
Operation Down to 2 V When Boost is Enabled
Low-Power-Mode IQ: 30 µA (One Buck On), 35 µA
(Two Bucks On)
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9 V to 11 V
Boost Output Selectable: 7 V, 10 V, or 11 V
Programmable Frequency and External
Synchronization Range 150 kHz to 600 kHz
Separate Enable Inputs (ENA, ENB)
Frequency Spread Spectrum (TPS43332)
Selectable Forced Continuous Mode or Automatic
Low-Power Mode at Light Loads
Sense Resistor or Inductor DCR Sensing
Out-of-Phase Switching Between Buck Channels
Peak Gate-Drive Current 1.5 A
Thermally Enhanced 38-Pin HTSSOP (DAP)
PowerPAD™ Package
Automotive Start-Stop, Infotainment, Navigation
Instrument Cluster Systems
Industrial and Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control Units
•
3 Description
The TPS43330-Q1 and TPS43332-Q1 devices
(TPS4333x-Q1)
include
two
current-mode
synchronous buck controllers and a voltage-mode
boost controller. The TPS4333x-Q1 family of devices
is ideally suited as a pre-regulator stage with low IQ
requirements and for applications that must survive
supply drops due to cranking events. The integrated
boost controller allows the devices to operate down to
2 V at the input without seeing a drop on the buck
regulator output stages. At light loads, the buck
controllers can be enabled to operate automatically in
low-power mode, consuming just 30 µA of quiescent
current.
The buck controllers have independent soft-start
capability and power-good indicators. Current
foldback in the buck controllers and cycle-by-cycle
current limitation in the boost controller provide
external MOSFET protection. The switching
frequency can be programed over 150 kHz to 600
kHz or synchronized to an external clock in the same
range. Additionally, the TPS43332-Q1 device offers
frequency-hopping spread-spectrum operation.
Device Information(1)
PART NUMBER
TPS43330-Q1
TPS43332-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (38)
12.50 mm × 6.20 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Diagram
VBAT
VBAT
TPS43330-Q1
or
TPS43332-Q1
VBUCKA
VBuckA
2V
VBUCKB
VBuckB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS43330-Q1, TPS43332-Q1
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application Diagram ................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
9
1
1
1
1
2
3
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 12
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 16
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 23
10 Application and Implementation........................ 25
10.1 Application Information.......................................... 25
10.2 Typical Application ................................................ 25
11 Power Supply Recommendations ..................... 35
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................. 35
12.2 Layout Example .................................................... 36
12.3 Power Dissipation Derating Profile, 38-Pin HTTSOP
PowerPAD™ Package ............................................. 39
13 Device and Documentation Support ................. 40
13.1
13.2
13.3
13.4
13.5
Third-Party Products Disclaimer ...........................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
14 Mechanical, Packaging, and Orderable
Information ........................................................... 40
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2013) to Revision F
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision D (September 2012) to Revision E
Page
•
Revised descriptions for DIV, ENA, and ENB pins................................................................................................................. 4
•
Revised DC Electrical Characteristics, items 4.2, 4.4, and 4.6 .............................................................................................. 8
•
Replaced typical characteristic curve: LOAD STEP RESPONSE (BOOST) (0 TO 5 A AT 10 A/µs)................................... 12
•
Altered functional block diagram .......................................................................................................................................... 16
•
Revised last paragraph of Light-Load PFM Mode section ................................................................................................... 24
•
Revised schematic for Application Example 1 ..................................................................................................................... 25
•
Changed R1 + R2... equation in Resistor Divider Selection... section ................................................................................. 34
Changes from Revision C (July 2012) to Revision D
Page
•
Changed specification names for HBM and CDM classification ratings ................................................................................ 6
•
Corrected TYP value for Vsense in Electrical Characteristics .................................................................................................. 9
•
Corrected capacitor value..................................................................................................................................................... 20
Changes from Revision B (July 2012) to Revision C
•
2
Page
Corrected year of revision date from 2011 to 2012................................................................................................................ 1
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Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
TPS43330-Q1, TPS43332-Q1
www.ti.com
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
6 Device Comparison Table
PART NUMBER
OPTION
TPS43330-Q1
Frequency-hopping spread spectrum OFF
TPS43332-Q1
Frequency-hopping spread spectrum ON
7 Pin Configuration and Functions
DAP Package
38-Pin HTSSOP With PowerPAD
Top View
VBAT
1
38
VIN
DS
2
37
GC1
3
36
DIV
GC2
4
35
VREG
CBA
5
34
CBB
GA1
6
33
GB1
PHA
7
32
PHB
GA2
8
31
GB2
PGNDA
EXTSUP
PGNDB
9
30
10
29
SA2
11
28
SB2
FBA
12
27
FBB
SA1
COMPA
SB1
COMPB
13
26
SSA
14
25
SSB
PGA
15
24
PGB
ENA
16
23
AGND
ENB
17
22
RT
18
21
DLYAB
19
20
SYNC
COMPC
ENC
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
23
O
Analog ground reference
CBA
5
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
COMPA
13
O
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. Clamping this voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPB
26
O
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. Clamping this voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPC
18
O
Error-amplifier output and loop-compensation node of the boost regulator
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
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TPS43330-Q1, TPS43332-Q1
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DIV
36
I
The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter
at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V. (1)
DLYAB
21
O
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the powergood comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
DS
2
I
This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An
alternative connection for better noise immunity is to a sense resistor between the source of the low-side
MOSFET and ground via a filter network.
ENA
16
I
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current.
ENB
17
I
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current. (1)
ENC
19
I
This input enables and disables the boost regulator. An input voltage higher than 1.7 V enables the controller.
Voltages lower than 0.7 V disable the controller. Because this pin provides an internal pulldown resistor (500 kΩ),
enabling the boost function requires pulling it high. When enabled, the controller starts switching as soon as VBAT
falls below the boost threshold, depending upon the programmed output voltage.
EXTSUP
37
I
One can use EXTSUP to supply the VREG regulator from one of the TPS43330-Q1 or TPS43330-Q2 buck
regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is
unused, leave the pin open without a capacitor installed.
FBA
12
I
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
FBB
27
I
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output
voltage.
GA1
6
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides
high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that
has a voltage swing provided by CBA.
GA2
8
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides
high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB1
33
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides
high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that
has a voltage swing provided by CBB.
GB2
31
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides
high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC1
3
O
This output can drive an external low-side N-channel MOSFET for the boost regulator. This output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC2
4
O
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can
bypass the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or disabled,
and thus reduce power losses.
PGA
15
O
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below the respective undervoltage threshold.
PGB
24
O
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below the respective undervoltage threshold.
PGNDA
9
O
Power ground connection to the source of the low-side N-channel MOSFETs of BuckA
PGNDB
30
O
Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
PHA
7
O
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
PHB
32
O
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
RT
22
O
Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost
controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz
for the boost controller.
(1)
4
DIV = high and ENC = high inhibits low-power mode on the bucks.
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Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
TPS43330-Q1, TPS43332-Q1
www.ti.com
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
SA1
10
I
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SA1 positive node, SA2 negative node).
SA2
11
I
SB1
29
I
SB2
28
I
SSA
14
O
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
SSB
25
O
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SB1 positive node, SB2 negative node).
SYNC
20
I
If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock,
this overriding the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power
mode at light loads. On the TPS43332-Q1 device, a high level enables frequency-hopping spread spectrum,
whereas an open or a low level disables it.
VBAT
1
I
Battery input sense for the boost controller. If, with the boost controller enabled, the voltage at VBAT falls below
the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed
boost output voltage.
VIN
38
I
Main Input pin. This is the buck-controller input pin as well as the output of the boost regulator. Additionally, VIN
powers the internal control circuits of the device.
VREG
35
O
The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck
and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtains its power from
either VIN or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
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TPS43330-Q1, TPS43332-Q1
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings (1)
Voltage
MIN
MAX
UNIT
Input voltage: VIN, VBAT
–0.3
60
V
Ground: PGNDA–AGND, PGNDB–AGND
–0.3
0.3
V
Enable inputs: ENA, ENB
–0.3
60
V
Bootstrap inputs: CBA, CBB
–0.3
68
V
Bootstrap inputs: CBA–PHA, CBB–PHB
–0.3
8.8
V
Phase inputs: PHA, PHB
–0.7
60
V
–1
60
V
Feedback inputs: FBA, FBB
–0.3
13
V
Error amplifier outputs: COMPA, COMPB
–0.3
13
V
High-side MOSFET drivers: GA1-PHA, GB1-PHB
–0.3
8.8
V
Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB
–0.3
8.8
V
Current-sense voltage: SA1, SA2, SB1, SB2
–0.3
13
V
Soft start: SSA, SSB
–0.3
13
V
Power-good outputs: PGA, PGB
–0.3
13
V
Power-good delay: DLYAB
–0.3
13
V
Switching-frequency timing resistor: RT
–0.3
13
V
SYNC, EXTSUP
–0.3
13
V
Low-side MOSFET driver: GC1–PGNDA
–0.3
8.8
V
Error-amplifier output: COMPC
–0.3
13
V
Enable input: ENC
–0.3
13
V
Current-limit sense: DS
–0.3
60
V
Output-voltage select: DIV
–0.3
8.8
V
P-channel MOSFET driver: GC2
–0.3
60
V
P-channel MOSFET driver: VIN-GC2
–0.3
8.8
V
Phase inputs: PHA, PHB (for 150 ns)
Voltage
(buck function:
BuckA and BuckB)
Voltage
(boost function)
Voltage
(PMOS driver)
Gate-driver supply, VREG
–0.3
8.8
V
Junction temperature, TJ
–40
150
°C
Operating temperature, TA
–40
125
°C
Storage
temperature, Tstg
–55
165
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to AGND, unless otherwise specified.
8.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
6
Electrostatic
discharge
Charged device model (CDM), per
AEC Q100-011
UNIT
±2000
Corner pins: VBAT (1), ENC (19), SYNC (20),
VIN (38)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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TPS43330-Q1, TPS43332-Q1
www.ti.com
SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
8.3 Recommended Operating Conditions
MIN
Buck function:
BuckA and BuckB
voltage
Boost function
NOM
MAX
Input voltage: VIN, VBAT
4
40
Enable inputs: ENA, ENB
0
40
Boot inputs: CBA, CBB
4
48
Phase inputs: PHA, PHB
–0.6
40
Current-sense voltage: SA1, SA2, SB1, SB2
0
11
Power-good output: PGA, PGB
0
11
SYNC, EXTSUP
0
9
Enable input: ENC
0
UNIT
V
9
Voltage sense: DS
40
DIV
Operating temperature: TA
0
VREG
–40
125
V
°C
8.4 Thermal Information
TPS4333x-Q1
THERMAL METRIC (1)
DAP
UNIT
38 PINS
RθJA
Junction-to-ambient thermal resistance (2)
27.3
RθJC(top)
Junction-to-case (top) thermal resistance (3)
19.6
RθJB
Junction-to-board thermal resistance (4)
15.9
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
6.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance (7)
1.2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
°C/W
0.24
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
8.5 Electrical Characteristics
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
1.0
INPUT SUPPLY
1.1
VBAT
1.2
1.3
(1)
PARAMETER
VIN
VIN(UV)
TEST CONDITIONS
Boost controller enabled, after satisfying
initial start-up condition
Supply voltage
MIN
TYP
MAX
2
40
Input voltage required for
device on initial start-up
6.5
40
Buck regulator operating
range after initial start-up
4
40
Buck undervoltage lockout
UNIT
V
V
VIN falling. After a reset, initial start-up
conditions may apply. (1)
VIN rising. After a reset, initial start-up
conditions may apply. (1)
3.5
3.6
3.8
V
3.8
4
V
If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
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Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
1.4
PARAMETER
VBOOST_UNL
TEST CONDITIONS
Boost unlock threshold
OCK
VBAT rising
MIN
TYP
MAX
8.2
8.5
8.8
V
30
40
µA
35
45
µA
40
50
µA
45
55
µA
4.85
5.3
7
7.6
5
5.5
VIN = 13 V, BuckA: LPM, BuckB: off, TA =
25°C
1.5
Iq_LPM_
LPM quiescent current:
(2)
VIN = 13 V, BuckB: LPM, BuckA: off, TA =
25°C
VIN = 13 V, BuckA, B: LPM, TA = 25°C
VIN = 13 V, BuckA: LPM, BuckB: off, TA =
125°C
1.6
Iq_LPM
LPM quiescent current:
(2)
VIN = 13 V, BuckB: LPM, BuckA: off, TA =
125°C
VIN = 13 V, BuckA, B: LPM, TA = 125°C
UNIT
SYNC = HIGH, TA = 25°C
1.7
Iq_NRM
Quiescent current:
normal (PWM) mode (2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA =
25°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA =
25°C
VIN = 13 V, BuckA, B: CCM, TA = 25°C
mA
SYNC = HIGH, TA = 125°C
1.8
Iq_NRM
VIN = 13 V, BuckA, B: CCM, TA = 125°C
7.5
8
1.9
Ibat_sh
Shutdown current
BuckA, B: off, VBAT = 13 V , TA = 25°C
2.5
4
µA
1.10
Ibat_sh
Shutdown current
BuckA, B: off, VBAT = 13 V, TA = 125°C
3
5
µA
2.0
INPUT VOLTAGE VBAT — UNDERVOLTAGE LOCKOUT
2.1
Boost-input undervoltage
1.8
1.9
2
V
VBAT rising. After a reset, initial start-up
conditions may apply. (1)
2.4
2.5
2.6
V
500
600
700
mV
Hysteresis
2.3
UVLOfilter
Filter time
3.0
INPUT VOLTAGE VIN — OVERVOLTAGE LOCKOUT
3.1
VOVLO
Overvoltage shutdown
3.2
OVLOHys
Hysteresis
3.3
OVLOfilter
Filter time
4.0
BOOST CONTROLLER
4.1
Vboost7V
4.2
Vboost7V-th
4.3
Vboost10V
Vboost10V-th
Vboost11V
mA
VBAT falling. After a reset, initial start-up
conditions may apply. (1)
UVLOHys
4.5
(2)
VBAT(UV)
VIN = 13 V, BuckB: CCM, BuckA: off, TA =
125°C
2.2
4.4
8
VIN = 13 V, BuckA: CCM, BuckB: off, TA =
125°C
Quiescent current:
normal (PWM) mode (2)
5
µs
VIN rising
45
46
47
VIN falling
43
44
45
1
2
3
5
V
V
µs
Boost VOUT = 7 V
DIV = low, VBAT = 2 V to 7 V
6.8
7
7.3
Boost-enable threshold
Boost VOUT = 7 V, VBAT falling
7.5
8
8.5
Boost-disable threshold
Boost VOUT = 7 V, VBAT rising
8
8.5
9
Boost hysteresis
Boost VOUT = 7 V, VBAT rising or falling
0.4
0.5
0.6
Boost VOUT = 10 V
DIV = open, VBAT = 2 V to 10 V
9.7
10
10.4
Boost-enable threshold
Boost VOUT = 10 V, VBAT falling
10.5
11
11.5
Boost-disable threshold
Boost VOUT = 10 V, VBAT rising
11
11.5
12
Boost hysteresis
Boost VOUT = 10 V, VBAT rising or falling
0.4
0.5
0.6
Boost VOUT = 11 V
DIV = VREG, VBAT = 2 V to 11 V
10.7
11
11.4
V
V
V
V
V
Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor
divider.
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TPS43330-Q1, TPS43332-Q1
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
4.6
PARAMETER
Vboost11V-th
TEST CONDITIONS
MIN
TYP
MAX
12.5
Boost-enable threshold
Boost VOUT = 11 V, VBAT falling
11.5
12
Boost-disable threshold
Boost VOUT = 11 V, VBAT rising
12
12.5
13
Boost hysteresis
Boost VOUT = 11 V, VBAT rising or falling
0.4
0.5
0.6
0.2
0.225
UNIT
V
BOOST-SWITCH CURRENT LIMIT
4.7
VDS
Current-limit sensing
4.8
tDS
Leading-edge blanking
DS input with respect to PGNDA
0.175
200
V
ns
GATE DRIVER FOR BOOST CONTROLLER
4.9
IGC1
4.10
rDS(on)
Peak
Gate-driver peak current
Source and sink driver
1.5
A
VREG = 5.8 V, IGC1 current = 200 mA
2
Ω
GATE DRIVER FOR PMOS
4.11
rDS(on)
PMOS OFF
4.12
IPMOS_ON
Gate current
VIN = 13.5 V, VGS = –5 V
10
4.13
tdelay_ON
Turnon delay
C = 10 nF
20
10
Ω
mA
5
10
µs
BOOST-CONTROLLER SWITCHING FREQUENCY
4.14
fsw-Boost
Boost switching frequency
4.15
DBoost
Boost duty cycle
fSW_Buck
/2
kHz
90%
ERROR AMPLIFIER (OTA) FOR BOOST CONVERTERS
Forward transconductance
VBAT = 12 V
0.8
1.35
VBAT = 5 V
0.35
0.65
0.9
11
V
0.808
V
4.16
GmBOOST
5.0
BUCK CONTROLLERS
5.1
VBuckA or
VBuckB
Adjustable output-voltage
range
5.2
Vref,
NRM
Internal reference and
tolerance voltage in normal
mode
5.3
Vref,
LPM
Internal reference and
Measure FBX pin
tolerance voltage in low-power
mode
Measure FBX pin
FBx = 0.75 V (low duty cycle)
V sense for reverse-current
limit in CCM
VI-Foldback
V sense for output short
5.7
tdead
Shoot-through delay, blanking
time
5.8
DCNRM
Maximum duty cycle (digitally
controlled)
5.9
DCLPM
Duty cycle, LPM
ILPM_Entry
LPM entry-threshold load
current as fraction of
maximum set load current
ILPM_Exit
LPM exit-threshold load
current as fraction of
maximum set load current
Vsense
5.5
5.6
0.784
1%
0.8
–2%
0.816
V
2%
60
75
90
mV
FBx = 1 V
–65
–37.5
–23
mV
FBx = 0 V
17
32.5
48
mV
High-side minimum on-time
5.10
0.8
–1%
V sense for forward-current
limit in CCM
5.4
0.792
mS
20
ns
100
ns
98.75%
80%
1%
See
(3)
.See
(3)
10%
HIGH-SIDE EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
5.11
IGX1_peak
Gate-driver peak current
5.12
rDS(on)
Source and sink driver
(3)
1.5
VREG = 5.8 V, IGX1 current = 200 mA
A
2
Ω
The exit threshold specification is to be always higher than the entry threshold.
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Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW-SIDE NMOS GATE DRIVERS FOR BUCK CONTROLLER
5.13
IGX2_peak
Gate-driver peak current
5.14
RDS
Source and sink driver
ON
1.5
VREG = 5.8 V, IGX2 current = 200 mA
A
2
Ω
ERROR AMPLIFIER (OTA) FOR BUCK CONVERTERS
5.15
GmBUCK
Transconductance
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
5.16
IPULLUP_FBx
Pullup current at FBx pins
6.0
DIGITAL INPUTS: ENA, ENB, ENC, SYNC
6.1
VIH
6.2
VIL
6.3
RIH_SYNC
Pulldown resistance on SYNC VSYNC = 5 V
500
kΩ
6.4
RIL_ENC
Pulldown resistance on ENC
VENC = 5 V
500
kΩ
6.5
IIL_ENx
Pullup current source on ENA,
VENx = 0 V
ENB
0.5
7.0
BOOST OUTPUT VOLTAGE: DIV
7.1
VIH_DIV
Higher threshold
7.2
VIL_DIV
Lower threshold
7.3
Voz_DIV
Voltage on DIV if unconnected Voltage on DIV if unconnected
8.0
SWITCHING PARAMETER – BUCK DC-DC CONTROLLERS
8.1
fSW_Buck
Buck switching frequency
RT pin: GND
360
400
440
kHz
8.2
fSW_Buck
Buck switching frequency
RT pin: 60-kΩ external resistor
360
400
440
kHz
8.3
fSW_adj
Buck adjustable range with
external resistor
RT pin: external resistor
150
600
kHz
8.4
fSYNC
Buck synchronization range
External clock input
150
600
kHz
8.5
fSS
Spread-spectrum spreading
TPS43332-Q1 only
9.0
INTERNAL GATE-DRIVER SUPPLY
5.8
6.1
V
9.1
VREG
0.2%
1%
7.5
7.8
0.2%
1%
4.6
4.8
V
150
250
mV
VEXTSUP = 0 V, normal mode as well as
LPM
100
400
mA
IVREG = 0 mA to 100 mA,
VEXTSUP = 8.5 V, SYNC = High
125
400
mA
VSSA and VSSB = 0 V
0.75
1.25
µA
1
1.35
mS
FBx = 0 V
50
100
200
nA
Higher threshold
VIN = 13 V
1.7
Lower threshold
VIN = 13 V
VREG = 5.8 V
VREG /
2
µA
V
V
5%
IVREG = 0 mA to 100 mA, VEXTSUP = 0 V,
SYNC = high
Internal regulated supply
VEXTSUP = 8.5 V
P)
Load regulation
IEXTSUP = 0 mA to 125 mA, SYNC = High
VEXTSUP = 8.5 V to 13 V
9.3
VEXTSUP-th
EXTSUP switch-over voltage
threshold
IVREG = 0 mA to 100 mA,
VEXTSUP ramping positive
9.4
VEXTSUP-Hys
EXTSUP switch-over
hysteresis
9.5
IVREG-Limit
Current limit on VREG
9.6
IVREG_EXTSU Current limit on VREG when
using EXTSUP
P-Limit
10.0
SOFT START
10.1
ISSx
11.0
OSCILLATOR (RT)
11.1
VRT
12.0
POWER GOOD / DELAY
12.1
PGpullup
Pullup for A and B to Sx2
12.2
PGth1
Power-good threshold
Soft-start source current
V
V
0.2
Load regulation
5.5
7.2
4.4
Oscillator reference voltage
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VREG – 0.2
VIN = 8 V to 18 V, VEXTSUP = 0 V, SYNC =
high
VREG(EXTSU
V
0.7
Internal regulated supply
9.2
10
0.72
1
1.2
V
50
FBx falling
–5%
–7%
V
kΩ
–9%
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Product Folder Links: TPS43330-Q1 TPS43332-Q1
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
12.3
PGhys
Hysteresis
12.4
PGdrop
Voltage drop
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPGA = 5 mA
450
mV
IPGA = 1 mA
100
mV
1
µA
16
µs
2%
12.5
12.6
PGleak
Power-good leakage
12.7
tdeglitch
Power-good deglitch time
VSx2 = VPGx = 13 V
2
12.8
tdelay
Reset delay
External capacitor = 1 nF
VBuckX < PGth1
12.9
tdelay_fix
Fixed reset delay
No external capacitor, pin open
12.10
IOH
Activate current source
(current to charge external
capacitor)
12.11
IIL
Activate current sink (current
to discharge external
capacitor)
13.0
OVERTEMPERATURE PROTECTION
13.1
Tshutdown
Junction-temperature
shutdown threshold
13.2
Thys
Junction-temperature
hysteresis
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
1
ms
20
50
µs
30
40
50
µA
30
40
50
µA
150
165
°C
15
°C
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8.6 Typical Characteristics
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
FORCED CONTINUOUS MODE (SYNC = 1), 200-mA LOAD
VOUT AC-COUPLED
1 A/DIV
100 mV/DIV
DISCONTINUOUS MODE (SYNC = 0), 200-mA LOAD
1 A/DIV
2 A/DIV
1 A/DIV
IIND
LOW-POWER MODE (SYNC = 0), 20-mA LOAD
50 µs/DIV
2 µs/DIV
Figure 1. Inductor Currents (Buck)
Figure 2. Buck Load Step: Forced Continuous Mode (0 to 4
A at 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
VOUTA
100 mV/DIV
VOUTB
VOUT AC-COUPLED
1 V/DIV
2 A/DIV
IIND
50 µs/DIV
2 ms/DIV
Figure 3. Soft-Start Outputs (Buck)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
Figure 4. Buck Load Step: Low-Power-Mode Entry (4 A to 90
mA at 2.5 A/µs)
VBAT (BOOST INPUT) = 5 V, V IN (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 KHz, INDUCTOR = 680 nH,
RSENSE = 10 mΩ, CIN = 440 μF, C OUT = 660 μF
100 mV/DIV
VOUT AC-COUPLED
2 A/DIV
IIND
50 µs/DIV
Figure 5. Buck Load Step: Low-Power-Mode Exit (90 mA to
4 A at 2.5 A/µs)
12
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Figure 6. Load Step Response (Boost) (0 to 5 A at 10 A/µs)
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
Typical Characteristics (continued)
VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
5 V/DIV
VBAT (BOOST INPUT)
VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
0V
0V
200 mV/DIV
200 mV/DIV
10 A/DIV
VBAT (BOOST INPUT)
5 V/DIV
VOUT BuckA AC-COUPLED
VIN (BOOST OUTPUT)
5 V/DIV
VOUT BuckB AC-COUPLED
0V
10 A/DIV
IIND
0A
IIND
0A
20 ms/DIV
Figure 7. Cranking-Pulse Boost Response (12 V to 3 V in 1
ms at Buck Outputs 7.5 and 11.5 W)
Figure 8. Cranking-Pulse Boost Response (12 V to 4 V in 1
ms at Boost Direct Output 25 W)
60
Quiescent Current (µA)
VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,
RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
3-A LOAD
5 A/DIV
20 ms/DIV
100-mA LOAD
50
40
BOTH BUCKS ON
30
ONE BUCK ON
20
10
NEITHER BUCK ON
5 A/DIV
0
-40
-15
10
2 µs/DIV
50
Sense Current (µA)
Peak Current Sense Voltage (mV)
62.5
37.5
25
12.5 SYNC = LOW
0
–12.5
–25
SYNC = HIGH
0.8
0.95
1.1
1.25
1.4
110
135
160
Figure 10. No-Load Quiescent Current vs Temperature
Figure 9. Inductor Currents (Boost)
75
–37.5
0.65
85
35
60
Temperature (°C)
1.55
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
150°C
25°C
0
1
2
Figure 11. BUCKx Peak Current Limit vs COMPx Voltage
3
4
5
6
7
8
9
10 11 12
Output Voltage (V)
COMPx Voltage (V)
Figure 12. Current-Sense Pins Input current (Buck)
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80
805
70
804
Regulated FBx Voltage (mV)
Peak Current Sense Voltage (mV)
Typical Characteristics (continued)
60
50
40
30
20
10
803
802
801
800
799
798
797
796
0
795
0
0.2
0.4
0.8
0.6
–40
–15
10
FBx Voltage (V)
35
60
85
110
135
160
Temperature (°C)
Figure 13. Foldback Current Limit (Buck)
Figure 14. Regulated FBx Voltage vs Temperature (Buck)
Peak Current Sense Voltage (mV)
80
70
60
VIN = 8 V
50
40
VIN = 12 V
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100
Duty Cycle (%)
Figure 15. Current Limit vs Duty cycle (Buck)
14
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
9 Detailed Description
9.1 Overview
The TPS43330-Q1 and TPS43332-Q1 devices include two current-mode synchronous buck controllers and a
voltage mode boost controller. The integrated boost controller allows the devices to operate down to 2 V at the
input without seeing a drop on the buck regulator output stages. At light loads, one can enable the buck
controllers to operate automatically in low-power mode, consuming just 30 μA of quiescent current. The buck
controllers have independent soft-start capability and power-good indicators. Current foldback in the buck
controllers and cycle-by-cycle current limitation in the boost controller provide external MOSFET protection. The
switching frequency is programmable over 150 kHz to 600 kHz or can be synchronized to an external clock in the
same range. The TPS43332-Q1 device also offers frequency-hopping spread-spectrum operation.
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9.2 Functional Block Diagram
VIN
EXTSUP
VREG
SYNC
Gate Driver
Supply
37
PWM
Logic
5
CBA
6
GA1
7
PHA
8
GA2
9
PGNDA
10
SA1
11
SA2
12
FBA
13
COMPA
15
PGA
21
DLYAB
34
CBB
33
GB1
32
PHB
31
GB2
30
PGNDB
29
SB1
28
SB2
27
FBB
26
COMPB
24
PGB
VREG
35
Internal
Oscillator
22
180 deg
RT
Duplicate for second
Buck controller channel
Internal ref
(Band gap)
38
Slope
Comp
PWM
comp
SYNC and
LPM
20
Current sense
Amp
OTA
GC2
Gm 0.8 V
Source
and
Sink
Logic
4
SSA
FBA
SA2
ENC
1 µA
SSA
14
ENA
16
ENA
SSB
ENB
17
DS
2
Filter timer
500 nA
40 µA
VIN
1 µA
25
VIN
40 µA
ENB
500 nA
OCP
VIN
VboostxV
0.2 V
COMPC
18
DIV
36
Gm
Second
Buck
Controller
Channel
Ramp
Vboost7V-th
VBAT
OTA
1
MUX
Vboost10V-th
Vboost11V-th
GC1
3
ENC
19
AGND
23
VREG
PWM
comp
PWM
Logic
PGNDA
16
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
9.3 Feature Description
9.3.1 Buck Controllers: Normal Mode PWM Operation
9.3.1.1 Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. Using a resistor at RT sets another frequency according to Equation 1.
X
fSW =
(X = 24 kW ´ MHz)
RT
fSW = 24 ´
109
RT
(1)
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz is also
possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and upon detection of this condition, the
device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical
switching frequencies, 180 degrees out-of-phase.
9.3.1.2 Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. The ENx pins are highvoltage pins, with a threshold of 1.7 V for the high level, and with which direct connection to the battery is
permissible for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA
(typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck
controllers are disabled, the device shuts down and consumes a current of less than 4 µA.
9.3.1.3 Feedback Inputs
The right-resistor feedback-divider network connected to the FBx (feedback) pins sets the output voltage.
Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA
pullup current source as a protection feature in case the pins open up as a result of physical damage.
9.3.1.4 Soft-Start Inputs
To avoid large inrush currents, each buck controller has an independent programmable soft-start timer. The
voltage at the SSx pin acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx pins,
in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After startup,
the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes the
reference for the buck controllers. Use Equation 2 to calculate the soft-start ramp time.
I SS ´ Dt
CSS =
(Farads)
DV
where
•
•
•
CSS is the required capacitor for ∆t, the desired soft-start time
ISS = 1 µA (typical)
∆V = 0.8 V
(2)
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be
tracked by a suitable resistor-divider network.
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Feature Description (continued)
9.3.1.5 Current Sensing and Current Limit With Foldback
Clamping of the maximum value of the COMPx pin limits the maximum current through the inductor to a
specified value. When the output of the buck regulator (and hence the feedback value at the FBx pin) falls to a
low value because of a short circuit or overcurrent condition, the clamped voltage at the COMPx pin successively
decreases, thus providing current foldback protection, which protects the high-side external MOSFET from
excess current (forward-direction current limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the
COMPx node drops low. A clamp is on the lower end as well to limit the maximum current in the low-side
MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward peak-current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is
for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5 V output and 12 V input), 50
mV is a more reasonable value, considering tolerances and mismatches. The graphs in the Typical
Characteristics section provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,
thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 16 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate because of the temperature sensitivity and a wide variation of the parasitic inductor series
resistance. Therefore using the more-accurate sense resistor for current sensing may be advantageous.
Inductor L
TPS43330-Q1
or
TPS43332-Q1
VBuckX
DCR
R1
1
C1
1
2
Sx2
VC
Sx1
1
Figure 16. DCR Sensing Configuration
9.3.1.6 Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation under all conditions. For optimal performance of this circuit, select the inductor and sense resistor
according to Equation 3.
L ´ f SW
= 200
RS
where
•
•
•
18
L is the buck-regulator inductor in henries
fsw is the buck-regulator switching frequency in hertz
RS is the sense resistor in ohms
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Feature Description (continued)
9.3.1.7 Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an opendrain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
To avoid triggering the power-good indicators because of noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the duration of the delay by using a suitable capacitor at the DLYAB pin according to Equation 4.
tDELAY
1 msec
=
CDLYAB
1 nF
(4)
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
9.3.2 Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The boost-controller switching-frequency setting is one-half of the
buck-controller switching frequency. An internal resistor-divider network programmable to 7 V, 10 V, or 11 V sets
the output voltage of the boost controller at the VIN pin, based on the low, open, or high status, respectively, of
the DIV pin. The device does not recognize a change of the DIV setting while the in the low-power mode.
The active-high ENC pin enables the boost controller, which is active when the input voltage at the VBAT pin has
crossed the unlock threshold of 8.5 V at least once. A single threshold crossing arms the boost controller, which
begins switching as soon as VIN falls below the value set by the DIV pin, regulating the VIN voltage. Thus, the
boost regulator maintains a stable input voltage for the buck regulators during transient events such as a
cranking pulse at the VBAT pin.
A voltage at the DS pin exceeding 200 mV pulls the CG1 pin low, turning off the boost external MOSFET.
Connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and
ground achieves cycle-by-cycle overcurrent protection for the MOSFET. Select the on-resistance of the MOSFET
or the value of the sense resistor in such a way that the on-state voltage at DS does not exceed 200 mV at the
maximum-load and minimum-input-voltage conditions. When using a sense resistor, TI recommends connecting
a filter network between the DS pin and the sense resistor for better noise immunity.
The boost output (VIN) can be used to supply other circuits in the system. However, the boost output should be
high-voltage tolerant. The device regulates the boost output to the programmed value only when VIN is low, and
so VIN can reach battery levels.
VBAT
VIN
TPS43330-Q1
or
TPS43332-Q1
DS
GC1
Figure 17. External Drain-Source Voltage Sensing
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Feature Description (continued)
VBAT
VIN
TPS43330-Q1
or
TPS43332-Q1
GC1
DS
RIFLT
CIFLT
RISEN
Figure 18. External Current Shunt Resistor
9.3.3 Frequency-Hopping Spread Spectrum
The TPS43332-Q1 device features a frequency-hopping pseudo-random spectrum-spreading architecture. On
this device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next
within a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a
linear-feedback shift register that changes the frequency of the internal oscillator based on a digital code. The
shift register is long enough to make the hops pseudo-random in nature and has a design such that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.
Table 1. Frequency-Hopping Control
SYNC
TERMINAL
FREQUENCY SPREAD SPECTRUM (FSS)
COMMENTS
External clock
Not active
Device in forced continuous mode, internal PLL locks into external clock
between 150 kHz and 600 kHz.
Low or open
Not active
Device can enter discontinuous mode. Automatic LPM entry and exit,
depending on load conditions
High
TPS43330-Q1: FSS not active
TPS43332-Q1: FSS active
Device in forced continuous mode
9.3.4 Gate-Driver Supply (VREG, EXTSUP)
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8
V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF.
NOTE
This pin has internal current-limit protection; do not use it to power any other circuits.
The VIN pin powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical).
If VIN is expected to go to high levels, excessive power dissipation can occur in this regulator, especially at high
switching frequencies and when using large external MOSFETs. In this case, powering this regulator from the
EXTSUP pin is advantageous, which can have a connection to a supply lower than VIN but high enough to
provide the gate drive. When the voltage on the EXTSUP pin is greater than 4.6 V, the linear regulator
automatically switches to the EXTSUP pin as the input, to provide this advantage. Efficiency improvements are
possible when using one of the switching regulator rails from the TPS4333x-Q1 family of devices or any other
voltage available in the system to power the EXTSUP pin. The maximum voltage for application to the EXTSUP
pin is 9 V.
20
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VIN
LDO
VIN
typ 5.8 V
EXTSUP
LDO
EXTSUP
typ 7.5 V
typ 4.6 V
VREG
Figure 19. Internal Gate-Driver Supply
Using a voltage above 5.8 V (sourced by VIN) for the EXTSUP pin is advantageous because it provides a large
gate drive and hence better on-resistance of the external MOSFETs.
When using the EXTSUP pin, always keep the buck rail supplying the EXTSUP pin enabled. Alternatively, if
switching off the buck rail supplying the EXTSUP pin is necessary, place a diode between the buck rail and the
EXTSUP pin.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from the VIN pin and has a typical value of 7.5 V. Current-limit protection for the VREG pin is
available in low-power mode as well. If the EXTSUP pin is unused, leave the pin open without a capacitor
installed.
9.3.5 External P-Channel Drive (GC2) and Reverse-Battery Protection
The TPS4333x-Q1 family of devices include a gate driver for an external P-channel MOSFET which can connect
across the rectifier diode of the boost regulator. Such connection is useful to reduce power losses when the
boost controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage to drive a
P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off the P-channel
MOSFET, eliminating the diode bypass.
Another use for the gate driver is to bypass any additional protection diodes connected in series, as shown in
Figure 20. Figure 21 also shows a different scheme of reverse battery protection, which may require only a
smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching
cycle. Because the diode is not always in the series path, the system efficiency can be improved.
R10
GC2
D3
Q7
Q6
L3
Fuse (S1)
VIN
VBAT
D2
C16
C17
D1
C15
TPS43330-Q1
or
TPS43332-Q1
C14
DS
GC1
C13
COMPC
R9
VBAT
Figure 20. Reverse-Battery Protection Option 1 for Buck-Boost Configuration
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GC2
VBAT
VIN
TPS43330-Q1
or
TPS43332-Q1
Fuse
DS
GC1
COMPC
VBAT
Figure 21. Reverse-Battery Protection Option 2 for Buck-Boost Configuration
9.3.6 Undervoltage Lockout and Overvoltage Protection
The TPS4333x-Q1 family of devices starts up at a VIN voltage of 6.5 V (minimum), required for the internal
supply (VREG). When the device has started up, the device operates down to a VIN voltage of 3.6 V; below this
voltage level, the undervoltage lockout disables the device.
NOTE
if VIN drops, VREG drops as well and therefore reduces the gate-drive voltage, whereas the
digital logic is fully functional. Even if the ENC pin is high, the boost-unlock voltage of
typically 8.5 V (typical) one time is required before boost activation can take place (see the
Boost Controller section).
A voltage of 46 V at the VIN pin triggers the overvoltage comparator, which shuts down the device. To prevent
transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of 5
µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators begin including a new
soft-start ramp for the buck regulators.
With the boost controller enabled, a voltage less than 1.9 V (typical) on the VBAT pin triggers an undervoltage
lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN
falls at a rate dependent on its capacitor and load, eventually triggering VIN undervoltage. A short falling
transient at the VBAT pin even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before the VIN
pin discharges to the undervoltage threshold.
9.3.7 Thermal Protection
The TPS4333x-Q1 family of devices is protected from overheating using an internal thermal shutdown circuit. If
the die temperature exceeds the thermal shutdown threshold of 165ºC because of excessive power dissipation
(for example, because of fault conditions such as a short circuit at the gate drivers or the VREG pin), the
controllers turn off and then restart when the temperature has fallen by 15ºC.
22
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9.4 Device Functional Modes
Table 2 lists the enable and inhibit pin configurations for the modes of operation.
Table 2. Mode of Operation
ENABLE AND INHIBIT
PINS
ENA
ENB
ENC SYNC
Low
Low
Low
Low
High
Low
X
DRIVER STATUS
BUCK
CONTROLLERS
DEVICE STATUS
Shutdown
Approximately 4 µA
BuckB: LPM enabled
Approximately 30 µA (light
loads)
BuckB: LPM inhibited
mA range
BuckA: LPM enabled
Approximately 30 µA (light
loads)
High
BuckA: LPM inhibited
mA range
Low
BuckA and BuckB: LPM
enabled
Approximately 35 µA (light
loads)
BuckA and BuckB: LPM
inhibited
mA range
Low
Shut down
Disabled
BuckB running
Disabled
High
High
High
Low
High
Low
Low
Low
High
Low
Low
Low
Low
High
High
X
Low
BuckA running
Low
High
Low
Disabled
Shut down
Disabled
Shutdown
Approximately 4 µA
BuckB running
Boost running for VIN < set
boost output
BuckB: LPM enabled
Approximately 50 µA (no
boost, light loads)
BuckB: LPM inhibited
mA range
Boost running for VIN < set
boost output
BuckA: LPM enabled
Approximately 50 µA (no
boost, light loads)
BuckA: LPM inhibited
mA range
BuckA and BuckB: LPM
enabled
Approximately 60 µA (no
boost, light loads)
BuckA and BuckB: LPM
inhibited
mA range
BuckA running
High
Low
High
High
High
High
Disabled
BuckA and BuckB
running
High
High
QUIESCENT CURRENT
BOOST CONTROLLER
BuckA and BuckB
running
Boost running for VIN < set
boost output
9.4.1 Buck Controllers: Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device
senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this
target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing VCOMPx to
fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current
matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower Nchannel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, a limit exists on the duty cycle of 95% to charge the bootstrap
capacitor at CBx which allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck
regulator switches at one-fourth of the normal frequency.
9.4.2 Buck Controllers: Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the choice of the inductor and sense resistor is as recommended in the slopecompensation section.
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In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the
current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse
occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic
operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and
35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
The TPS4333x-Q1 family of devices can support the full-current load during low-power mode until the transition
to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of fullload current if the selection of inductor and sense resistor is as recommended. Moreover, a hysteresis also exists
between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power
mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to
GND. A high (VREG) level on DIV inhibits low-power mode, unless the ENC pin is set to low.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS43330-Q1 and TPS43332-Q1 devices are ideally suited as a pre-regulator stage with low Iq
requirements and for applications that must survive supply drops due to cranking events. The integrated boost
controller allows the devices to operate down to 2 V at the input without seeing a drop on the buck regulator
output stages. Below component values and calculations are a good starting point and theoretical representation
of the values for use in the application; improving the performance of the device may require further optimization
of the derived components.
10.2 Typical Application
The following example illustrates the design process and component selection for the TPS43330-Q1 device.
2.5V to 40V
L1
VBAT
D1
BOOST — 10V, 25W
3.9µH
10µF
CIN
220µF
680µF
COUT1
TOP-SW3
1kΩ
VIN
VBAT
EXTSUP
DS
BOT-SW3
1.5kΩ
0.02Ω
1nF
TOP-SW1
VBuckA — 5V, 15W
0.015Ω
DIV
GC2
VREG
CBA
CBB
GA1
GB1
PHA
PHB
4.7µF
TOP-SW2
L3
0.1µF
0.1µF
L2
8.2µH
100µF
COUTA
GC1
VBuckB — 3.3V, 6.6W
0.03Ω
15µH
100µF
COUTB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDB
PGNDA
84kΩ
SA1
SA2
FBA
TPS43330-Q1
or
TPS43332-Q1
50kΩ
SB1
SB2
FBB
16kΩ
16kΩ
33pF
1.5nF 24kΩ
10nF
COMPA
COMPB
SSA
SSB
PGA
PGB
ENA
AGND
ENB
RT
27pF
30kΩ 1.1nF
10nF
5kΩ
220pF
5kΩ
22nF 7.2kΩ
COMPC
ENC
DLYAB
1nF
SYNC
Figure 22. Simplified Application Schematic
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Typical Application (continued)
10.2.1 Design Requirements
Table 3 lists the design-goal parameters.
Table 3. Application Example
PARAMETER
VBuckA
VBuckB
BOOST
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking
pulse input) to 30 V
Output voltage, VOUTx
5V
3.3 V
10 V
Maximum output current, IOUTx
3A
2A
Input voltage
Load-step output tolerance, ∆VOUT +
∆VOUT(Ripple)
Current output load step, ∆IOUTx
2.5 A
±0.5 V
±0.2 V
±0.12 V
0.1 A to 3 A
0.1 A to 2 A
0.1 A to 2.5 A
400 kHz
400 kHz
200 kHz
Converter switching frequency, fSW
10.2.2 Detailed Design Procedure
The component values for this design example are calculated using the same equations as used for above
example. In this example, the boost operates at 150 kHz , while the buck operates at 300 kHz each. The Buck A
operates down to 5 V to give.
Table 4. Application Example – Component Proposals
COMPONENT PROPOSAL
VALUE
L1
NAME
MSS1278T-392NL (Coilcraft)
4 µH
L2
MSS1278T-822ML (Coilcraft)
8.2 µH
L3
MSS1278T-153ML (Coilcraft)
15 µH
D1
SK103 (Micro Commercial Components)
TOP_SW3
IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2
Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2
Si4840DY-T1-E3 (Vishay)
BOT_SW3
IRFR3504ZTRPBF (International Rectifier)
COUT1
EEVFK1J681M (Panasonic)
680 µF
COUTA, COUTB
ECASD91A107M010K00 (Murata)
100 µF
CIN
EEEFK1V331P (Panasonic)
220 µF
10.2.2.1 Boost Component Selection
A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its
transfer function. The RHP zero relates inversely to the load current and inductor value and directly to the input
voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too
close to the RHP zero frequency, the regulator may become unstable.
Thus, for high-power systems with low input voltages, choose a low inductor value. A low value increases the
amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost
regulator. Select these components with the ripple-to-RHP zero trade-off in mind and considering the power
dissipation effects in the components because of parasitic series resistance.
A boost converter that operates always in the discontinuous mode does not contain the RHP zero in the transfer
function. However, designing for the discontinuous mode demands an even lower inductor value that has high
ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it can
become unstable.
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VIN
CO
7V
COMPx
OTA-gmEA
R ESR
10 V
C1
+
VREF
C2
R3
12 V
Figure 23. Boost Compensation Components
This design assumes operation in continuous-conduction mode. During light load conditions, the boost converter
operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for
stability.
10.2.2.2 Boost Maximum Input Current IIN_MAX
The maximum input current flows at the minimum input voltage and maximum load. The efficiency for VBAT = 5 V
at 2.5 A is 80%, based on the graphs in the Typical Characteristics section.
POUT
25 W
PINmax =
=
= 31.3 W
Efficiency
0.8
(5)
Therefore:
IINmax (at VBAT = 5 V) =
31.3 W
= 6.3 A
5V
(6)
10.2.2.3 Boost Inductor Selection, L
Allow an input ripple current of 40% of IIN max at VBAT = 5 V.
L=
VBAT ´ t ON
IINripple max
=
VBAT
5V
=
= 4.9 mH
IINripple max ´ 2 ´ fSW 2.52 A ´ 2 ´ 200 kHz
(7)
Select a lower value of 4 µH to ensure a high RHP-zero frequency while making a compromise that expects a
high current ripple. This inductor selection also makes the boost converter operate in discontinuous conduction
mode, where compensation is easier.
The inductor saturation current must be higher than the peak inductor current and some percentage higher than
the maximum current-limit value set by the external resistive sensing element.
Determine the saturation rating at the minimum input voltage, maximum output current, and maximum core
temperature for the application.
10.2.2.4 Inductor Ripple Current, IRIPPLE
Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.
10.2.2.5 Peak Current in Low-Side FET, IPEAK
I
3.1 A
I PEAK = IINmax + RIPPLE = 6.3 A +
= 7.85 A
2
2
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Based on this peak current value, calculate the external current-sense resistor, RSENSE.
0.2 V
RSENSE =
= 25 mW
7.85 A
(9)
Select 20 mΩ, allowing for tolerance.
The filter component values RIFLT and CIFLT for current sense are 1.5 kΩ and 1 nF, respectively, which allows for
good noise immunity.
10.2.2.6 Right Half-Plane Zero RHP Frequency, fRHP
VBAT min
fRHP =
= 32 kHz
2p ´ IINmax ´ L
(10)
10.2.2.7 Output Capacitor, COUTx
To ensure stability, select the output capacitor, COUTx, such that Equation 11 is true.
fRHP
fLC £
10
10
2p ´ L ´ COUTx
£
V BAT min
2p ´ IINmax ´ L
æ 10 ´ IINmax
³ç
ç VBAT min
è
COUTx
2
2
ö
æ 10 ´ 6.3 A ö
÷ ´L = ç
÷ ´ 4 mH
÷
5V
è
ø
ø
COUTx min ³ 635 mF
(11)
Select COUTx = 680 µF.
This capacitor is usually aluminum electrolytic with ESR in the tens of milliohms. ESR in this range is good for
loop stability, because it provides a phase boost. The output filter components, L and C, create a double pole
(180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the
modulator at frequency fESR. Use Equation 12 to determine these frequencies.
f ESR =
f ESR =
f LC =
1
2p ´ COUTx ´ RESR
Hz, assume RESR = 40 mW
1
= 6 kHz
2p ´ 660 mF ´ 0.04 W
1
2p ´ L ´ COUTx
=
1
2p ´ 4 mH ´ 660 mF
= 3.1 kHz
(12)
Equation 12 satisfies fLC ≤ 0.1 fRHP.
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
10.2.2.8 Bandwidth of Boost Converter, fC
Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response:
fLC < fESR< fC< fRHP Zero
fC < fRHP Zero / 3
fC < fSW / 6
fLC < fC / 3
10.2.2.9 Output Ripple Voltage Due to Load Transients, ∆VOUTx
Assume a bandwidth of fC = 10 kHz.
DVOUTx = R ESR ´ DI OUTx +
DI OUTx
4 ´ COUTx ´ f C
= 0.04 W ´ 2.5 A +
2.5 A
= 0.19 V
4 ´ 660 mF ´ 10 kHz
(13)
Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters
are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,
select smaller components for the boost output.
10.2.2.10 Selection of Components for Type II Compensation
The required loop gain for unity-gain bandwidth (UGB) is calculated with Equation 14.
æ fC ö
æ fC ö
G = 40 log ç
÷ - 20 log ç
÷÷
çf
ç fLC ÷
è ESR ø
è
ø
æ 10 kHz ö
æ 10 kHz ö
÷ - 20 log ç
÷ = 15.9 dB
3.1
kHz
è
ø
è 6 kHz ø
G = 40 log ç
(14)
The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This Gm allows a
constant loop response across the input-voltage range and makes compensation easier by removing the
dependency on VBAT.
R3 =
C1 =
C2 =
10G/20
85 ´ 10-6 A / V 2 ´ VOUTx
= 7.2 kW
10
10
=
= 22 nF
2p ´ f C ´ R3 2p ´ 10 kHz ´ 7.2 kW
C1
æf
2p ´ R3 ´ C1´ ç SW
è 2
ö
÷ -1
ø
=
22 nF
æ 200 kHz ö
2p ´ 7.2 kW ´ 22 nF ´ ç
÷ -1
2
è
ø
= 223 pF
(15)
10.2.2.11 Input Capacitor, CIN
The input ripple required is lower than 50 mV.
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DVC1 =
CIN =
IRIPPLE
8 ´ fSW ´ CIN
IRIPPLE
8 ´ fSW ´ DVC1
www.ti.com
= 10 mV
= 194-μF
DVESR = IRIPPLE ´ R ESR = 40 mV
(16)
Therefore, TI recommends 220 µF with 10-mΩ ESR.
10.2.2.12 Output Schottky Diode D1 Selection
Maximizing efficiency requires a Schottky diode with low forward-conducting voltage, VF, over temperature and
fast switching characteristics. The reverse breakdown voltage should be higher than the maximum input voltage,
and the component should have low reverse leakage current. Additionally, the peak forward current should be
higher than the peak inductor current. The following calculation gives the power dissipation in the Schottky diode:
PD = ID(PEAK) ´ VF ´ (1 - D)
D = 1-
VINMIN
VOUT + VF
= 1-
5V
= 0.53
10 V + 0.6 V
PD = 7.85 A ´ 0.6 V ´ (1 - 0.53) = 2.2 W
(17)
10.2.2.13 Low-Side MOSFET (BOT_SW3)
æ VI ´ IPk
PBOOSTFET = (IPk )2 ´ rDS(on) (1 + TC) ´ D + ç
ç 2
è
ö
÷÷ ´ (tr + t f ) ´ fSW
ø
æ VI ´ IPk
PBOOSTFET = (7.85 A)2 ´ 0.02 W ´ (1 + 0.4) ´ 0.53 + ç
è 2
ö
÷ ´ (20 ns + 20 ns) ´ 200 kHz = 1.07 W
ø
(18)
The times tr and tf denote the rising and falling times of the switching node and relate to the gate-driver strength
of the TPS43330-Q1 device, TPS43332-Q1 device, and gate Miller capacitance of the MOSFET. The first term
denotes the conduction losses, which the low on-resistance of the MOSFET minimizes. The second term
denotes the transition losses which arise because of the full application of the input voltage across the drainsource of the MOSFET as it turns on or off. Transition losses are higher at high output currents and low input
voltages (because of the large input peak current) and when the switching time is low.
NOTE
The on-resistance, rDS(on), has a positive temperature coefficient, which produces the
(TC = d × ΔT) term that signifies the temperature dependence. (Temperature coefficient d
is available as a normalized value from MOSFET data sheets and can have an assumed
starting value of 0.005 per °C.)
10.2.2.14 BuckA Component Selection
10.2.2.14.1 BuckA Component Selection
t ON min =
VOUTA
3.3 V
=
= 275 ns
VIN max ´ f SW 30 V ´ 400 kHz
(19)
tON min is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is
achievable at this frequency.
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
10.2.2.14.2 Current-Sense Resistor RSENSE
Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is
approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple
currents, select a VSENSE maximum of 50 mV.
50 mV
RSENSE =
= 17 mW
3A
(20)
Select a value of 15 mΩ for RSENSE.
10.2.2.15 Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response,
choose the inductor such that:
R SENSE
15 mW
L = K FLR ´
= 200 ´
= 7.5 mH
f SW
400 kHz
(21)
KFLR = coil-selection constant = 200
Select a standard value of 8.2 µH. For the buck converter, select the inductor saturation currents and core to
sustain the maximum currents.
10.2.2.16 Inductor Ripple Current IRIPPLE
At the nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IOUT max ≈ 1 A.
10.2.2.17 Output Capacitor COUTA
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ, giving ∆VOUT(Ripple) ≈ 15 mV
and a ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
2 ´ DI OUTA
2 ´ 2.9 A
COUTA »
=
= 72.5 mF
f SW ´ DVOUTA 400 kHz ´ 0.2 V
(22)
VOUTA(Ripple) =
DVOUTA =
I OUTA(Ripple)
8 ´ f SW ´ COUTA
DI OUTA
4 ´ f C ´ COUTA
+ I OUTA(Ripple) ´ ESR =
+ DI OUTA ´ ESR =
1A
+ 1 A ´ 10 mW = 13.1mV
8 ´ 400 kHz ´ 100 mF
2.9 A
+ 2.9 A ´ 10 mW = 174 mV
4 ´ 50 kHz ´ 100 mF
(23)
(24)
10.2.2.18 Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response.
• Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
• Select the zero fz ≈ fC / 10
• Make the second pole fP2 ≈ fSW / 2
10.2.2.19 Selection of Components for Type II Compensation
VOUT
RESR
RL
R1
VSENSE
GmBUCK
COUT
R2
VREF
COMP
Type 2A
R3
R0
C2
C1
Figure 24. Buck Compensation Components
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2p ´ f C ´ VOUT ´ COUTx
R3 =
=
www.ti.com
2p ´ 50 kHz ´ 5 V ´ 100μF
GmBUCK ´ K CFB ´ VREF
GmBUCK ´ K CFB ´ VREF
= 23.57 kW
where
•
•
•
•
•
VOUT = 5 V
COUT = 100 µF
GmBUCK = 1 mS
VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
(25)
Use the standard value of R3 = 24 kΩ.
10
C1 =
10
=
2p ´ R3 ´ fC
= 1.33 nF
2p ´ 24 kW ´ 50 kHz
(26)
Use the standard value of 1.5 nF.
C1
1.5 nF
=
= 33 pF
C2 =
f
æ SW ö
æ 400 kHz ö
2p ´ R3 ´ C1ç
÷ -1
÷ - 1 2p ´ 24kW ´ 1.5 nF ç
2
è
ø
è 2 ø
(27)
The resulting bandwidth of buck converter, f C, is calculated with Equation 28.
fC =
GmBUCK ´ R3 ´ K CFB VREF
´
2p ´ COUTx
VOUT
fC =
1mS ´ 24 kW ´ 8.33 S ´ 0.8 V
= 50.9 kHz
2p ´ 100 μF ´ 5 V
(28)
fC is close to the target bandwidth of 50 kHz.
The resulting zero frequency, fZ1, is calculated with Equation 29.
1
1
fZ1 =
=
= 4.42 kHz
2p ´ R3 ´ C1 2p ´ 24 kW ´ 1.5 nF
(29)
fZ1 is close to the fC / 10 guideline of 5 kHz.
The second pole frequency, fP2, is calculated with Equation 30.
1
1
fP2 =
=
= 201kHz
2p ´ R3 ´ C2 2p ´ 24 kW ´ 33 pF
(30)
fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
10.2.2.20 Resistor Divider Selection for Setting VOUTA Voltage
b=
VREF
0.8 V
=
= 0.16
VOUTA
5V
(31)
Select the divider current through R1 and R2 to be 50 µA. Then use Equation 32 and Equation 33 to find the
values of R1 and R2.
R1 + R2 =
R2
R1 + R2
5V
50 mA
= 66 kW
(32)
= 0.16
(33)
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
10.2.2.21 BuckB Component Selection
Using the same method as for VBuckA produces the following parameters and components.
VOUTB
3.3 V
t ON min =
=
= 275 ns
VIN max ´ f SW 30 V ´ 400 kHz
(34)
This value is higher than the minimum duty cycle specified (100 ns typical).
60 mV
RSENSE =
= 30 mW
2A
L = 200 ´
30 mW
= 15 mH
400 kHz
(35)
∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max)
Select an output capacitance COUTB of 100 µF with low ESR in the range of 10 mΩ.
Assume fC = 50 kHz.
2 ´ DI OUTB
2 ´ 1.9 A
=
= 46 mF
COUTB »
fSW ´ DVOUTB 400 kHz ´ 0.12 V
VOUTB(Ripple) =
DVOUTB =
I OUTB(Ripple)
8 ´ f SW ´ COUTB
DI OUTB
4 ´ f C ´ COUTB
+ I OUTB(Ripple) ´ ESR =
+ DI OUTB ´ ESR =
(36)
0.4 A
+ 0.4 A ´ 10 mW = 5.3 mV
8 ´ 400 kHz ´ 100 mF
1.9 A
+ 1.9 A ´ 10 mW = 114 mV
4 ´ 50 kHz ´ 100 mF
(37)
(38)
2p ´ f C ´ VOUTB ´ COUTB
R3 =
GmBUCK ´ K CFB ´ VREF
=
2p ´ 50 kHz ´ 3.3 V ´ 100 mF
1mS ´ 4.16 S ´ 0.8 V
= 31kW
(39)
Use the standard value of R3 = 30 kΩ.
10
C1 =
10
=
2p ´ R3 ´ fC
æ fSW
è 2
2p ´ R3 ´ C1´ ç
=
=
(40)
C1
C2 =
fC =
= 1.1nF
2p ´ 30 kW ´ 50 kHz
ö
÷ -1
ø
1.1nF
æ 400 kHz ö
2p ´ 30 kW ´ 1.1nF ´ ç
÷ -1
2
è
ø
GmBUCK ´ R3 ´ K CFB
2p ´ COUTB
´
= 27 pF
(41)
VREF
VOUTB
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p ´ 100 μF ´ 3.3 V
= 48 kHz
(42)
fC is close to the target bandwidth of 50 kHz.
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The resulting zero frequency, fZ1, is calculated with Equation 43.
fZ1 =
1
1
=
2p ´ R3 ´ C1
= 4.8 kHz
2p ´ 30 kW ´ 1.1nF
(43)
fZ1 is close to the fC guideline of 5 kHz.
The second pole frequency, fP2, is calculated with Equation 44.
fP2 =
1
1
=
2p ´ R3 ´ C2
2p ´ 30 kW ´ 27 pF
= 196 kHz
(44)
fP2 is close to the fSW / 2 guideline of 200 kHz.
Therefore the design satisfies all requirements for a good loop.
10.2.2.22 Resistor Divider Selection for Setting VOUT Voltage
b=
VREF
VOUT
=
0.8 V
3.3 V
= 0.242
(45)
Select the divider current through R1 and R2 to be 50 µA. Then use Equation 46 and Equation 47 to calculate
the values of R1 and R2.
R1 + R2 =
R2
R1 + R2
3.3 V
50 mA
= 66 kW
(46)
= 0.242
(47)
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
10.2.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for
these MOSFETs. The output is a totem pole, allowing full-voltage drive of VREG to the gate with peak output
current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the
reference for the low-side MOSFET is the power-ground (PGNDx) terminal. For a particular application, select
these MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source
breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gatedriver strength of the TPS4333x-Q1 family of devices and to the gate Miller capacitance of the MOSFET. The
first term denotes the conduction losses, which are minimal when the on-resistance of the MOSFET is low. The
second term denotes the transition losses, which arise because of the full application of the input voltage across
the drain-source of the MOSFET as it turns on or off. Transition losses are lower at low currents and when the
switching time is low.
æ V ´I
ö
PBuckTOPFET = (IOUT )2 ´ rDS(on) (1 + TC) ´ D + ç IN OUT ÷ ´ (tr + t f ) ´ f SW
2
è
ø
2
PBuckLOWERFET = (IOUT ) ´ rDS(on) (1 + TC) ´ (1 - D) + VF ´ IOUT ´ (2 ´ t d ) ´ fSW
(48)
(49)
In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. The second term in the preceding equation denotes this. Using external
Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.
NOTE
The value of rDS(on) has a positive temperature coefficient, and the TC term for rDS(on)
accounts for that fact. TC = d × ΔT(°C). The temperature coefficient d is available as a
normalized value from MOSFET data sheets and can have an assumed starting value of
0.005 per ºC.
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
10.2.3 Application Curves
VIN (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
90
1000
80
EFFICIENCY (%)
100
70
POWER LOSS,
SYNC = HIGH
60
100
50
40 POWER LOSS,
SYNC = LOW
30
10
20
1
EFFICIENCY,
SYNC = HIGH
10
0
0.0001
0.01
0.1
VBAT = 8 V
70
VBAT = 5 V
60
VBAT = 3 V
50
40
30
20
10
0.1
0.001
80
Efficiency (%)
90
10000
EFFICIENCY,
SYNC = LOW
POWER LOSS (mW)
100
1
10
OUTPUT CURRENT (A)
Figure 25. Efficiency Across Output Currents (Bucks)
0
0.01
10
1
Output Current (A)
Figure 26. Efficiency Across Output Currents (Boost)
11 Power Supply Recommendations
The TPS43330-Q1 device is designed to operate from an input voltage up to 40 V. Ensure that the input supply
is well regulated. Furthermore, if the supply voltage in the application is likely to reach negative voltage (for
example, reverse battery) a forward diode must be placed at the input of the supply. For the VIN pin, a good
quality X7R ceramic capacitor is recommended. Capacitance derating for aging, temperature, and DC bias must
be taken into account while determining the capacitor value. Connect a local decoupling capacitor close to the
Vreg for proper filtering. The PowerPAD™ package, which offers an exposed thermal pad to enhance thermal
performance, must be soldered to the copper landing on the PCB for optimal performance.
12 Layout
12.1 Layout Guidelines
Use the following guidelines for the design considerations of the grounding and PCB circuit layout.
12.1.1 Boost Converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense
resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to
Schottky diode D1 to the COUT1 capacitor. Connect the negative terminal of the input capacitor and the
negative terminal of the sense resistor together with short trace lengths.
2. The overcurrent-sensing shunt resistor may require noise filtering, and the filter capacitor should be close to
the IC pin.
12.1.2 Buck Converter
1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1.
The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.
3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitors for noise near the IC pins.
4. The resistor divider for sensing the output voltage connects between the positive terminal of its respective
output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their
traces near any switching nodes or high-current traces.
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Layout Guidelines (continued)
12.1.3 Other Considerations
1. Short PGNDx and AGND to the thermal pad. Use a star ground configuration if connecting to a non-ground
plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense
feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive
circuits near the dv/dt nodes; these include the gate-drive outputs, phase pins, and boost circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Locate the bypass capacitors as close as possible to their respective power and ground pins.
12.2 Layout Example
POW ER
IN PUT
Powe r L ines
Connec tion to GND P lane o fPCB th rough v ias
Connec tion to top /bo ttom o fPCB th rough v ias
Vo ltage Ra ilO u tpu ts
V BOOST
VBAT
V IN
EXTSUP
GC1
D IV
GC2
VREG
CBA
CBB
GA1
GB1
PHA
PHB
GA2
GB2
PGNDA
PGNDB
SA1
SB1
SA2
SB2
FBA
FBB
COMPA
COMPB
SSA
SSB
PGA
PGB
ENA
AGND
ENB
RT
COMPC
ENC
M ic rocon tro lle r
VBUCKB
VBUCKA
DS
DLYAB
Exposed Pad
connec ted to GND
P lane
SYNC
Figure 27. TPS4333x-Q1 Layout Example
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
Layout Example (continued)
Boost: Switching Components
Minimize this loop area to reduce ringing
Buck 1 and Buck 2: Switching Components
Minimize this loop area to reduce ringing
Supply Decoupling Capacitor
Place nearby
Figure 28. Layout Example (Top)
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Layout Example (continued)
Multiple vias connect the input, output, and package pad to the ground plane
Large ground plane reduces noise and ground-loop errors
Figure 29. Layout Example (Bottom)
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SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014
12.3 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD™ Package
Figure 30. Derating Profile for Power Dissipation Based on High-K JEDEC PCB
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13 Device and Documentation Support
13.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS43330-Q1
Click here
Click here
Click here
Click here
Click here
TPS43332-Q1
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS43330-Q1 TPS43332-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TPS43330QDAPRQ1
NRND
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43330Q1
TPS43332QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43332Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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