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TPS43331-Q1
SLVSA38B – DECEMBER 2009 – REVISED JULY 2017
TPS43331-Q1 Dual Switcher and Linear Regulators
1 Features
2 Applications
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level 2
Input Operating Range 5 V to 30 V (VBAT)
Two, Adjustable Output Voltage, Step-Down
Switching Voltage Regulators
External Clock Input
Soft-Start Control for Step-Down Regulators
Programmable, Linear Regulator (VSTBY), Low
Quiescent Current (65 µA typ)
Programmable, Linear Regulator (VLR)
Overvoltage Detection and Shutdown
Protected, High-Side Drive Ouput (HSD)
Power-On Reset for Standby Regulator (VSTBY)
Serial Communication, I2C Interface
Low Voltage Warning Detection With
Programmable Input Threshold (LVWIN, VBATW)
Enable Feature, Controls VBUCK 1
Programmable Power Good Delay Time (PGDLY)
for VSTBY
Current-Limit and Independent Thermal Detection
and Shutdown Protection on All Regulators and
High-Side Driver Output
Thermally Enhanced 38-Pin DAP PowerPAD™
Package
Simplified Schematic
PGDLY
CBS1
VGT1
CSLEW
PH1
VCP
Vsupply
VINSB TPS43331
The standby linear regulator (VSTBY) is high voltage
tolerant and can be connected directly to the vehicle
battery, the quiescent current is typically 65 µA to
maintain a regulated output with light loads.
Device Information(1)
PART NUMBER
TPS43331-Q1
VLR
HSD
BODY SIZE (NOM)
12.50 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Load Current (VOUT = 5 V)
100
80
VBUCK 2
VGB2
VSTBY
PACKAGE
HTSSOP (38)
90
VSTBY
EN
I2CID
RST*
AGnd
The TPS43331-Q1 is a multi-rail output voltage
regulator, with two synchronous switch mode
controllers and two linear regulators. In addition, there
is a reverse protected high side switch and voltage
supervisor for monitoring the standby regulator and
input voltage. The regulator outputs and high side
switch are controlled either by discrete inputs for
certain outputs and serial interface using the I2C
configuration for outputs not controlled by discrete
inputs.
VBUCK 1
CBS2
VGT2
PH2
LVWIN
SDA
SCL
SYNCH
3 Description
VGB1
VBAT*
VBATP
VBAT
Automotive Applications
Power Supply for Microcontrollers and DSPs
VLREG
HSD
Copyright © 2017, Texas Instruments Incorporated
Efficiency (%)
1
70
60
50
7Vin
40
12Vin
18Vin
30
24Vin
fSW = 185 kHz
20
0
0.5
1
1.5
Load Current (A)
2
2.5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS43331-Q1
SLVSA38B – DECEMBER 2009 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
DC Electrical Characteristics .................................... 5
I2C Interface Electrical Characteristics...................... 7
Switching Regulators Electrical Characteristics........ 8
Standby Regulator (VSTBY) Electrical
Characteristics ........................................................... 9
6.9 Linear Regulator (VLR) Electrical Characteristics... 10
6.10 High-Side Driver (HSD) Electrical Characteristics 11
6.11 AC Switching Characteristics................................ 11
6.12 I2C Interface Switching Characteristics................. 12
6.13 Switching Regulators Switching Characteristics ... 12
6.14 Linear Regulator Switching Characteristics .......... 13
6.15 High-Side Driver (HSD) Switching
Characteristics ......................................................... 13
6.16 Timing and Switching Diagrams ........................... 14
6.17 Typical Characteristics .......................................... 18
7
Detailed Description ............................................ 20
7.1
7.2
7.3
7.4
7.5
7.6
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Map...........................................................
20
21
21
26
27
29
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Application .................................................. 30
8.3 System Example ..................................................... 43
9 Power Supply Recommendations...................... 44
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 44
10.3 Power Dissipation Derating................................... 45
11 Device and Documentation Support ................. 46
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
46
12 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2015) to Revision B
Page
•
Added the automotive features to the Features section......................................................................................................... 1
•
Changed the values for the linear regulator and standby regulator in the Recommended Operating Conditions table........ 5
•
Added the VBAT = 6 V test condition and change VUVLO to 9 V in the battery < 18 V test condition for the battery
input leakage current parameter in the DC Electrical Characteristics table ........................................................................... 5
•
Added back the 18-V test condition (8% maximum) for the VSTBY parameter..................................................................... 9
•
Added to the Charge Pump Capacitor Input (VCP) section ................................................................................................. 23
•
Updated some of the symbols in the Detailed Design Procedure section ........................................................................... 32
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 46
•
Changed the Electrostatic Discharge Caution statement..................................................................................................... 46
Changes from Original (December 2009) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Added Thermal Information table .......................................................................................................................................... 5
•
Deleted parameter VSTBY = 18 for 8 MAX............................................................................................................................... 9
•
Changed Input voltage in Table 3 ....................................................................................................................................... 32
•
Changed VBUCK 1 to IBUCK 1 in Table 3 ......................................................................................................................... 32
•
Changed VBUCK 2 to IBUCK 2 in Table 3 ......................................................................................................................... 32
2
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SLVSA38B – DECEMBER 2009 – REVISED JULY 2017
5 Pin Configuration and Functions
DAP Package
28-Pin HTSSOP With PowerPAD
Top View
AGND
VSTBYS
VSTBY
VINSB
CSLEW
VCP
VLRS
VINLR
VLR
EN
SDA
SCL
SYNCH
LVWIN
VBATW
VBAT
HSD
PGDLY
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VGB1
PH1
VGT1
CBS1
VCMP1
VFB1
ISLO1
ISHI1
PGND
ISHI2
ISLO2
VFB2
VCMP2
CBS2
VGT2
PH2
VGB2
VBATP
I2CID
Pin Functions
PIN
NO.
NAME
I/O
DEFAULT
STATE
DESCRIPTION
1
AGND
Ground
—
Analog ground reference
2
VSTBYS
I
—
Voltage feedback for standby regulator
3
VSTBY
O
—
Regulated output, for standby and normal mode
4
VINSB
Power
—
Power input for standby regulator
5
CSLEW
O
Low
6
VCP
I
—
Storage capacitor for charge pump
Capacitor to control VSTBY slew rate
7
VLRS
I
—
Voltage feedback for switched linear regulator
8
VINLR
Power
—
Input power for switched linear regulator
9
VLR
O
—
Linear regulator output, switched using serial interface
10
EN
I
Low
11
SDA
I/O
—
Input command for active mode
Serial bidirectional data line for I2C
12
SCL
I
—
Serial clock input for synchronization of data communications for I2C
13
SYNCH
I
Low
14
LVWIN
I
—
15
VBATW
O
Open
16
VBAT
Power
—
Input power for high side driver switch
17
HSD
O
—
High side driver output
18
PGDLY
I
—
Power good delay capacitor input for VSTBY regulator
19
RST
O
Low
Low-voltage reset indicator for VSTBY (active low)
20
I2CID
I
Low
Chip Identifier for I2C
21
VBATP
Power
—
22
VGB2
O
Low
External clock input for synchronization of switching frequency for SMPS
Low-voltage warning input
Battery voltage warning output
Battery voltage input for IC with external protection for reverse connections
Low side gate drive output for channel 2 (synchronous switch)
23
PH2
I
—
24
VGT2
O
Low
Phase reference for bootstrap drive channel 2
25
CBS2
I
—
Bootstrap capacitor for high side gate drive channel 2
26
VCMP2
I
—
Compensation feedback for channel 2
27
VFB2
I
—
Regulated output voltage feedback for channel 2
28
ISLO2
I
—
Low side of output current sense, channel 2
29
ISHI2
I
—
High side of output current sense, channel 2
High side gate drive output for channel 2 (synchronous switch)
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Pin Functions (continued)
PIN
I/O
DEFAULT
STATE
PGND
Ground
—
Power ground, switching regulator ground reference
ISHI1
I
—
High side of output current sense, channel 1
ISLO1
I
—
Low side of output current sense, channel 1
33
VFB1
I
—
Regulated output voltage feedback for channel 1
34
VCMP1
I
—
Compensation feedback for channel 1
35
CBS1
I
—
Bootstrap capacitor for high side gate drive channel 1
36
VGT1
O
Low
37
PH1
I
—
38
VGB1
O
Low
NO.
NAME
30
31
32
DESCRIPTION
High side gate drive output for channel 1 (synchronous switch)
Phase reference for bootstrap drive channel 1
Low side gate drive output for channel 1 (synchronous switch)
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Unregulated input (3)
VBAT, VBATP
–0.3
40
V
Unregulated power supply (3)
VINSB, VINLR
–0.3
40
V
High side output
(4)
HSD
–0.3
40
V
Low voltage warning input
LVWIN
–0.3
40
V
Switched linear regulator
VLR
–0.3
15
V
Bootstrap capacitor
VCP
–0.3
18
V
PGDLY, CSLEW, VBATW, RST, EN, VSTBYS, VSTBY, VLRS,
SYNCH, I2CID, SCL, SDA, VCMP1, VCMP2, VFB1, VFB2 (3)
–0.3
5.5
ISHI1, ISHI2, ISLO1, ISLO2 (3)
–0.3
10
CBS1, CBS2, VGT1, VGT2
–0.3
40
VGB1, VGB2
–0.3
10
PH1, PH2 (4)
–1
40
Operating junction temperature range, TJ
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
Logic level or low voltage signals
(1)
(2)
(3)
(4)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Absolute negative voltage on these pins not to go below –0.5 V.
Absolute negative voltage on these pins not to go below –1 V, and transients of –2 V because of recirculation of an inductive load
for < 100 ns.
6.2 ESD Ratings
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
VALUE
UNIT
2000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SLVSA38B – DECEMBER 2009 – REVISED JULY 2017
6.3 Recommended Operating Conditions
MIN
MAX
Unregulated input
VBAT, VBATP
5
30
V
Unregulated power supply
VINSB, VINLR
1.8
30
V
High side output
HSD
5
30
V
Low voltage warning input
LVWIN
5
30
V
Linear regulator
VLR
1.2
12
V
Standby regulator
VSTBY, VSTBYS
1.2
5
V
Bootstrap capacitor
VCP
16
V
5.3
V
Logic level or low voltage signals
PGDLY, CSLEW, VBATW, RST, EN, VLRS, SYNCH,
I2CID, SCL, SDA, VCMP1, VCMP2, VFB1, VFB2
4.5
ISHI1, ISHI2, ISLO1, ISLO2
1.2
9
V
CBS1, CBS2, VGT1, VGT2
5
38
V
VGB1, VGB2
3
8
V
–1
30
V
–40
125
°C
PH1, PH2
TA
(1)
Operating ambient temperature
UNIT
(1)
Assumes TA = TJ – Power dissipation × θJA
6.4 Thermal Information
TPS43331-Q1
THERMAL METRIC (1)
DAP (HTSSOP)
UNIT
38 PINS
RθJA
Junction-to-ambient thermal resistance (2)
25
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (3)
10
°C/W
RθJB
Junction-to-board thermal resistance
—
°C/W
ψJT
Junction-to-top characterization parameter
—
°C/W
ψJB
Junction-to-board characterization parameter
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
This assumes a JEDEC JESD 51-5 standard board with thermal vias – See the Layout Example section and the application report
PowerPAD Thermally Enhanced Package for more information.
This assumes junction to exposed thermal pad.
6.5 DC Electrical Characteristics
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBAT Battery input
VNOV
Normal operating voltage
6
18
V
VJSV
Jump start voltage
TA = –40ºC to 50ºC
18
26.5
V
VOVSD
Overvoltage shutdown
All outputs except standby reg are disabled,
27
VHYS
Hysteresis
VUVLO
Undervoltage lockout
IQ
Battery input leakage
current
V
0.5
VSTBY ref disabled, Verify < VOL(max)
2
V
5.2
Standby mode, VBAT = 14 V, IVSTBY = 100 µA,
IBattery – |IVSTBY|, EN = 0 V
100
Standby mode, 9 V < VBAT < 18 V, IVSTBY = –100 µA,
IBattery – |IVSTBY|, EN = 0 V
130
Standby mode, 18 V < VBAT < 40 V, IVSTBY = –100 µA,
IBattery – |IVSTBY|, EN = 0 V
200
Standby mode, VBAT = 6 V, IVSTBY = –100 µA,
IBattery – |IVSTBY|, EN = 0 V
2.5
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V
µA
mA
5
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SLVSA38B – DECEMBER 2009 – REVISED JULY 2017
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DC Electrical Characteristics (continued)
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
IB
IB
Battery input bias current
VBAT input bias current
TEST CONDITIONS
MIN
VBAT = 6V to 18V, HSDEN = VLREN = SW2EN = 1,
VGT2 = VGB2 = open, IVSTBY = IVLR = IHSD = 100 µA,
IBattery – |IVSTBY| – |IVLR| – |IHSD|
TYP
MAX UNIT
25
VBAT = 6 V to 18 V, HSDEN = 1, IHSD = 100 µA, |IVBAT| –
|IHSD|
1
VBAT = 40 V
5
VBAT = –20 V
mA
mA
–2
LVWIN Low voltage warning input
VTH
Input high threshold
VHYS
Hysteresis
ILKG
Input leakage current
1.1
1.2
V
On rising edge on input signal
70
120
mV
LVWIN = 1 V to 18 V
–1
1
LVWIN = 40 V
–1
1
µA
VBATP Consumption current
IB
IVSTBY = 50 mA
10
SW2EN = 1, VGTX = VGBX = open
15
VLREn = 1, IVLR = 100 µA
10
Supply current from VBATP IVBATP = | IVLR |
line
VBAT = 40 V, IVSTBY = 50 mA
10
mA
6
VBAT = VINLR = Open, VUVLO < VBATP = VINSB < 18 V,
VLREn = SW2EN = HSDEN = 1, IVLR = IHSD = –100 µA,
VGTX = VGBX = Open, IVBATP – | IVSTBY + IVLR + IHSD |
20
CSLEW Slew rate control on standby regulator VSTBY
ICSLEW
Soft-start rate on VSTBY
reg
CCSLEW = 0.01 µF
–2.9
–1.45
µA
EN Enable/disable input
VIH
Enable
VIL
Disable
VHYS
Hysteresis
ILKG
Input leakage current
2
V
0.8
V
300
800
mV
–1
1
µA
SYNCH Synchronization input voltage threshold
VIH
Enable
Switch enabled going from low to high 20% to 80%
VIL
Disable
Switch disabled going from high to low 80% to 20%
VHYS
Hysteresis
RPD
Input pulldown resistance
2
V
0.8
V
300
800
mV
20
100
kΩ
–2.6
–1.5
µA
1.5
2.5
V
PGDLY Power good delay
IOH
Power delay output current
PGDLY = 0, 100 pF ≤ CPGDLY ≤ 0.01 µF
VTH
Input threshold
Verify RST deasserted
VSAT
PGDLY saturation voltage
100 pF ≤ CPGDLY ≤ 0.01uF
0.4
V
0.5 V ≤ VSTBY ≤ VTH_min (VSTBY), IOL = 1.6 mA, Active
mode
0.4
V
0.5 V ≤ VSTBY ≤ VTH_min (VSTBY), IOL = 1.6 mA, Standby
mode
0.4
V
RST Reset output
VOL
Reset output
ILeakage
Output leakage current
0.5 V ≤ VBATP ≤ VUVLO_min, IOL = 100 µA
RST = VSTBY, Active and standby modes
–10
0.4
V
10
µA
VBATW Low input voltage warning (Battery input)
VOL
Warning output voltage
IOL = 1.6 mA, Active and standby modes
ILeakage
Output leakage current
VBATW = VSTBY, Active and standby modes
6
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–10
0.4
V
10
µA
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6.6 I2C Interface Electrical Characteristics
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
I2CID Serial interface ID address input
VIH
Input high threshold
VIL
Input low threshold
VHYS
Hysteresis
ILKG
Input leakage current
2
I2CID = 3.3 V
V
0.8
V
0.3
0.8
V
–1
1
µA
SCL Serial clock input for synchronization
VIH
Input high threshold
VIL
Input low threshold
VHYS
Hysteresis
ILKG
Input leakage current
CSCLIN
Input line capacitance
2
V
0.8
0.3 V ≤ VSCL ≤ 3.0 V
V
0.3
0.8
V
–1
1
µA
10
pF
SDA Serial communications data line
VIH
Input high threshold
VIL
input low threshold
VHYS
Hysteresis
ILeakage
Leakage current
VSAT
Output saturation voltage
CSDAIN
Input line capacitance
2
V
0.8
V
0.3
0.8
V
–1
1
µA
IOL = 3 mA
0.4
V
IOL = 6 mA
0.6
V
10
pF
0.3 V ≤ VSDA ≤ 3.0 V
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6.7 Switching Regulators Electrical Characteristics
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switch mode regulators (Channel 1)
IO
Output current
VO
Regulated output voltage range
1.2
10
VFB1
Feedback voltage input
980
1020
VOTOL
Regulated output voltage tolerance
–5%
5%
VISCTH
Short circuit current, voltage
threshold (1)
60
120
mV
VDO
Dropout voltage (2)
IO = IO(max), VBAT = 9 V, Includes drop due to
VISCTH
400
mV
dV/dt
Output voltage soft-start slew rate (3)
Step response on regulator enable, IO = IO(max)
10
V/ms
VP_SC
Overshoot
(4)
Load transient response (4)
VP_TR
4
IO = 100% to 10% IO(max), Includes external
feedback resistors
A
V
mV
5%
IO = ISC(max), Remove short
5%
IO = 10% to 100% IO(max)
–5%
IO = 100% to 10% IO(max)
5%
IVGT1_SRC
Gate drive source current (high side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
IVGT1_SINK
Gate drive sink current (high side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
500
1020
mA
IVGB1_SRC
Gate drive source current (low side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
90
135
mA
IVGB1_SINK
Gate drive sink current (low side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
440
1300
mA
210
330
mA
Switch mode regulators (Channel 2), SW2EN = 1 (unless otherwise noted)
IO
Output current
4.0
VO
Regulated output voltage range
1.2
10
VFB1
Feedback voltage input
980
1020
VOTOL
Regulated output voltage tolerance
–5%
5%
VISCTH
Short circuit current, voltage
threshold (1)
60
120
mV
VDO
Dropout voltage (2)
IO = IO(max), VBAT = 9 V, Includes drop due to
VISCTH
400
mV
dV/dt
Output voltage soft-start slew rate (3)
Step response on regulator enable, IO = IO(max)
10
V/ms
VP_SC
Overshoot (4)
IO = ISC(max), Remove short
VP_TR
Load transient response (4)
IO = 100% to 10% IO(max), Includes external
feedback resistors
A
V
mV
5%
IO = 10% to 100% IO(max)
–5%
IO = 100% to 10% IO(max)
5%
IVGT2_SRC
Gate drive source current (high side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
IVGT2_SINK
Gate drive sink current (high side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
500
1020
mA
IVGB2_SRC
Gate drive source current (low side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
90
135
mA
IVGB2_SINK
Gate drive sink current (low side)
VGT1 = VGB1 = 6 V, Measure time calculate
current
440
1300
mA
(1)
(2)
(3)
(4)
8
210
330
mA
The output remains stable using soft-start conditions when the output drops from regulation to 0 V. The device is not damaged by a hard
short to ground.
Lower VBAT until the output drops to 0.1 V. Measure VBAT – VO.
Design information – Not tested. Specified by CSLEW current and bench characterization.
Design information – Not tested.
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6.8 Standby Regulator (VSTBY) Electrical Characteristics
VINLR = 3 V to 18 V, VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Active mode
MIN
TYP MAX
5
300
0.05
300
1.2
3.6
980
1020
–5%
5%
UNIT
IO
Output current
VO
Regulated output
voltage range
VSTBYS
Feedback input
voltage for standby
regulator
VSTBY
Regulated output
voltage tolerance
LR
Load regulation
IO = IO(max) to IO(min)
–4%
0%
SR
Line regulation
IO = IO(max), VO + VDO < VINSB < 18 V
–4%
4%
ISC
Short circuit current
limit
VSTBY = 0 V
310
1400
mA
VDO
Dropout voltage (4)
IO = 300 mA
1200
mV
VLVRTH
Low-voltage reset
threshold
Lower VO until goes low
900
950
mV
TSD
Thermal shutdown (5)
150
210
°C
THYS
Hysteresis
5
15
°C
ΔV/ΔT
Output voltage slew
rate (6)
Step response on regulator, IO = IO(min)
10
V/mS
VOP_SC
Overshoot (5)
IO = ISC(min), Remove short
VP_TR
VPRSS
Load transient
response (5)
Power supply
rejection ratio (5)
Standby mode
VINSB = (VO + VDO) to 18 V, IO = IO(max) (1) to IO(min),
TA = –40°C to +50°C, VINSB = 18 V to 26.5 V, IO = IO(max) (2) to IO(min)
IO = IO(max) to IO(min), VO + VDO < VINSB < 18 V,
1% nominal (3% worse case) tolerance resistors
IO = IO(max) to IO(min), 18 V < VINSB < 26.5 V
–6%
6%
Active mode, VSTBY = 3.6 V, CVSTBY = 1 µF, Δt = 10 µs,
IO = IO(min) to IO(max), IO = IO(max) to IO(min)
–6%
6%
Standby mode, VSTBY = 1.2 V, CVSTBY = 1 µF, Δt = 10 µs,
IO = –100 mA to IO(max), IO = IO(max) to –100 mA
–6%
6%
Standby mode, VSTBY = 3.6 V, CVSTBY = 1 µF, Δt = 10 µs,
IO = –100 mA to IO(max), IO = IO(max) to –100 mA
–6%
6%
IO = 0.5×IO(max), fo = 120 Hz to 10 kHz, VINSB = 14-V DC and 1-V AC
(p – p)
50
IO = 0.5×IO(max), fo = 20 to 20 kHz, VINSB = 14-V DC and 1-V AC (p –
p)
45
400
100-kHz low-pass filter, fo = 20 Hz to 20 kHz, IVSTBY = –5 mA
200
Output voltage
transient response
IO = IO(min) to IO(max), CO(max)
CO
Output capacitance
CO(nom) = 1 µF, 16 V
RESR
Output capacitance
ESR
f = 1 kHz, TA = 125°C
DF
Output capacitor
dissipation factor
f = 1 kHz, TA = –40°C
(1)
(2)
(3)
(4)
(5)
(6)
dB
100-kHz low-pass filter, fo = 20 Hz to 100 kHz, IVSTBY = –5 mA
ttr
mV
5%
Active mode, VSTBY = 1.2 V, CVSTBY = 1 µF, Δt = 10 µs,
IO = IO(min) to IO(max), IO = IO(max) to IO(min)
Output noise
V
8%
(3)
VN
mA
0.53
uV
40
µs
1.15
µF
8.75
Ω
1%
f = 1 kHz, TA = 25°C
3.5%
f = 1 kHz, TA = 125°C
5.5%
This nomenclature is meant to agree with the convention that current flow into the pin is a positive. Therefore Io(max) is a smaller
magnitude current and Io(min) is larger magnitude current throughout the parametric tables.
Design information – Not tested, parameter assured by characterization.
The output remains stable using soft-start conditions when the output drops from regulation to 0 V. The IC is not damaged by a hard
short to ground.
Lower VBAT until the output drops to 0.1 V. Measure VBAT – VO.
Design information – Not tested.
Design information – Not tested. Specified by CSLEW current and bench characterization.
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6.9 Linear Regulator (VLR) Electrical Characteristics
VINLR = 3 V to 18 V, VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
IO
TEST CONDITIONS
Output current
VINLR = (VO + VDO) to 18 V, IO = IO(max) to IO(min),
TA = –40°C to +50°C, VINLR = 18 V to 26.5 V, IO = IO(max) to
IO(min)
VO
Regulated output
voltage range
VLRS
Feedback input voltage
VLR
IO = IO(max) to IO(min), VO + VDO < VINLR < 18 V,
Output voltage tolerance 1% nominal (3% worse case) tolerance resistors
IO = IO(max) to IO(min), VINLR = 18 V to 26.5 V
LR
Load regulation
SR
Line regulation
ISC
Short circuit current limit
Dropout voltage (2)
VDO
TSD
Thermal shutdown
THYS
Hysteresis
VOP_SC
Overshoot
VP_TR
Load transient
response (3)
VPRSS
5
650
mA
1.2
8.5
V
980
1020
–5%
5%
–4%
1%
–4%
4%
IO = IO(max), 18 V < VINLR < 26.5 V
–4%
4%
VLR = 0 V
(1)
mV
2.7
A
IO = –200 mA
0.7
400
mV
IO = –600 mA
1.7
V
150
210
ºC
5
15
ºC
IO = ISC(min), Remove short
5%
VLR =1.2 V, CVLR = 1 µF, Δt = 10 µs, IO = IO(min) to IO(max),
IO = IO(max) to IO(min)
–6%
6%
VLR = 8.5 V, CVLR = 1 µF, Δt = 10 µs, IO = IO(min) to IO(max),
IO = IO(max) to IO(min)
–6%
6%
IO = 0.5×IO(max), fo = 120 Hz to 10 kHz, VINLR = 14-V DC
and 1-V AC (p – p)
50
IO = 0.5×IO(max), fo = 20 Hz to 20 kHz, VINLR = 14-V DC
and 1-V AC (p – p)
45
dB
100-kHz low-pass filter, fo = 20 Hz to 100 kHz, IVLR = –5 mA
400
Weighted filter, fo = 20 Hz to 20 kHz, IVLR = –5 mA
200
ttr
Output voltage transient
response (3)
IO = IO(min) to IO(max), CO(max)
CO
Output capacitance (3)
CO(nom) = 1 µF, 16 V
RESR
Output capacitance
ESR (3)
f = 1 kHz, TA = 125°C
DF
Output capacitor
dissipation factor (3)
f = 1 kHz, TA = –40°C
10
UNIT
IO = IO(max), VO + VDO < VINLR < 18 V
Output noise (3)
(2)
(3)
MAX
8%
(3)
Power supply rejection
ratio (3)
TYP
IO = IO(max) to IO(min)
VN
(1)
MIN
0.53
uV
40
µs
1.15
µF
8.75
Ω
1%
f = 1 kHz, TA = 25°C
3.5%
f = 1 kHz, TA = 125°C
5.5%
The output remains stable using soft-start conditions when the output drops from regulation to 0 V. The IC is not damaged by a hard
short to ground.
Lower VBAT until the output drops to 0.1 V. Measure VBAT – VO.
Design information – Not tested
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6.10 High-Side Driver (HSD) Electrical Characteristics
VBAT = VBATP = 6 V to 18 V, HSD1EN = 1, TJ = –40°C to +150ºC (unless otherwise noted)
PARAMETER
VSAT
HSD output saturation
voltage
TEST CONDITIONS
Leakage current
TYP
0.6
IHSD = –450 mA, t = 0.5 s
1.2
V
5
µA
–5
V
HSD1EN = 0, RHSD = 20 Ω to –1 V
–100
HSD1EN = 0, VBAT = HSD
–100
100
HSD1EN = 0, VBAT = HSD = 34 V
–100
100
µA
0
10
mA
15
mA
VBAT = open, CVBAT = 1 mF, HSD = 18 V
µA
(1)
GND = open, RHSD = 20 Ω to –1 V
ISTG
High-side short circuit
current
HSD = 0 V
TSD
HSD thermal shutdown (3)
IHSD = –100 µA
HSD = VBAT
THYS Hysteresis
(1)
(2)
(3)
MAX UNIT
IHSD = –300 mA
HSD1EN = 0, HSD = 0 V
ILKG
MIN
µA
0.310
1.4
A
–2
2 (2)
mA
150
190
ºC
5
15
ºC
The condition does not damage the IC or any external components connected to the IC.
The limits are based on characterization. This condition does not damage the IC and or any external components connected to the IC.
Design information – Not tested
6.11 AC Switching Characteristics
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted) (see Figure 1 and Figure 2)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RST Reset timing
1
tenrst
Reset enable time
2
tPGDLY
Reset delay time
CPGDLY(nom) = 100 pF
0
3
tpor
Internal power on reset
4
tf
Reset fall time
25
µs
100
µs
VSTBY in regulation to RST deasserted delay
5
ms
CRST = 50 pF
2
µs
20
µs
1
µs
VSTBY Standby regulator de-glitch timer
5
tlvcp
De-glitch filter time
5
PGDLY Power good discharge time
tdch
Power good delay capacitor
discharge time
CPGDLY = 0.01 µF
VBATW low input voltage warning
6
tprlvw
Low voltage rising output
indicator propagation delay
1
µs
7
tpfovsd
Overvoltage shutdown
propagation delay
1
µs
8
tpflvw
Low voltage falling output
warning propagation delay
1
µs
9
tf
Fall time
1
µs
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6.12 I2C Interface Switching Characteristics
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted) (see Figure 3) (1) (2)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SCL Serial clock timing
1
fSCL
2
tHD,
Serial clock frequency
STA
Hold time for repeated start
3
tLOW
Clock low pulse width
4
tHIGH
Clock high pulse width
5
tSU,
STA
Standard mode
0
100
kHz
Fast mode
0
400
kHz
Standard mode
4
µs
Fast mode
0.6
µs
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
Setup time for repeated start
4
µs
Fast mode
0.6
µs
Standard mode
4.7
µs
Fast mode
0.6
µs
Standard mode
6
tr, SCL
Clock rise time
1
µs
21 (3)
300
ns
60
300
ns
0.3
µs
Fast mode, CSCL = 10 pF
21
300
ns
Fast mode, CSCL = 400 pF
60
300
ns
50
ns
Fast mode, CSCL = 10 pF
Fast mode, CSCL = 400 pF
Standard mode
7
tf, SCL
8
tSP,SCL
Clock fall time
Clock input noise pulse
SDA Serial communications data line
9
tSU,
DAT
Serial data setup time
Standard mode
250
Fast mode
100
ns
ns
Standard mode
10
tr, SDA
Data rise time
tf, SDA
12
tSP,SDA
Data fall time
21
300
ns
Fast mode, CSDA = 400 pF
60
300
ns
300
ns
Fast mode, CSDA = 10 pF
21
300
ns
Fast mode, CSDA = 400 pF
60
300
ns
SDA input noise pulse
Standard mode
13
tfo,SDA
14
tSU,STO
15
tBU
SDA output pulse time
Bus free between stop and start bit
50
ns
250
ns
ns
Fast mode, CSDA = 10 pF
21
250
Fast mode, CSDA = 400 pF
60
250
Standard mode
Stop bit setup time
µs
Fast mode, CSDA = 10 pF
Standard mode
11
1
ns
4
µs
Fast mode
0.6
µs
Standard mode
4.7
µs
Fast mode
1.3
µs
Capacitance on serial interface pins SCL and SDA are 10 pF ≥ CSCL, CSDA ≥ 400 pF
Parameters assured by worst case test program execution in fast mode.
The total load capacitance range for SCL and SDA for I2C specification
(1)
(2)
(3)
6.13 Switching Regulators Switching Characteristics
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
NO.
12
PARAMETER
1
fSW
Nominal operating frequency
1
fSWTOL
Operating frequency tolerance
1
fSYN CH
Synch frequency range nominal
1
DSYN CH
Synch input duty ratio
TEST CONDITIONS
MIN
TYP
MAX UNIT
165
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kHz
–15%
15%
225
400
40%
60%
kHz
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Switching Regulators Switching Characteristics (continued)
VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
2
tr
Gate drive transition time, rising
VGTx = VGB × 6 V, CVGBx = 100 nF
500 (1)
ns
3
tf
Gate drive transition time, falling
VGTx = VGB × 6 V, CVGBx = 100 nF
100 (1)
ns
4
tDS
Synchronous switch on delay
100 (2)
ns
5
tdt
Top switch on delay
20
100
ns
tdc
Minimum on time
3.5% (3)
98.2% (4)
(1)
(2)
20
Switching times will vary for different external FET.
Delay time is intended to guard against shoot-through losses and will be dependent upon the switch transition times. Measurements are
done at either threshold values or 50% as shown below.
Don(min) = (1.2 V × (1 – tol)) / Vov(max) = (1.2 V × 0.95) / 33 V.
Min refresh time of 220 ns every five periods at 440 kHz.
(3)
(4)
6.14 Linear Regulator Switching Characteristics
VINLR = 3 V to 18 V, VBAT = VBATP = 6 V to 18 V, TJ = –40°C to +150ºC (unless otherwise noted) (see Figure 5)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1
tdon
Turnon delay
15
µs
2
tdoff
Turnoff delay
3
tdovsd
Delay timer overvoltage shutdown
15
µs
200
4
tdrovsd
Delay timer return from overvoltage shutdown
200
µs
µs
6.15 High-Side Driver (HSD) Switching Characteristics
VBAT = VBATP = 6 V to 18 V, HSD1EN = 1, TJ = –40°C to +150ºC (unless otherwise noted) (see Figure 6)
NO.
(1)
PARAMETER
TEST CONDITIONS
(1)
1
tdon
Turnon delay
2
tdoff
Turnoff delay
3
tr
Rise time, 10% to 90%
4
tdovsd
5
tdrovsd
MIN
TYP
MAX UNIT
0
15
µs
0
200
µs
25
75
µs
Delay timer overvoltage shutdown
0
200
µs
Delay timer return from overvoltage shutdown
0
200
µs
RHSD = 180 Ω
Design information – Not tested
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6.16 Timing and Switching Diagrams
V
POR
VBAT
VLOB
t
V
VBATP
VUVLO
3
t
V
Bandgap
t
2
VSTBY
5
VTHL(max)
V
VTHL(min)
VSTBY
0.5V
0.5V
Cslew/internal ref for VSTBY
1
1
t
V
RST
VLO(min)
4
t
Figure 1. Input and Control Timing
14
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Timing and Switching Diagrams (continued)
VBAT
t
6
8
7
LVWIN
t
9
VBATW*
t
Figure 2. Input and Control Timing for VBATW
SDA
15
11
13
9
10
3
4
7
12
14
5
SCL
2
6
1
8
Figure 3. Serial Communication AC Timing (I2C Interface)
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Timing and Switching Diagrams (continued)
1
Oscillator
50%
t
2
3
4
5
90%
VGTx
10%
t
3
2
90%
VGBx
10%
t
Figure 4. Switching Regulators Timing
SDA
(I2C,VLREN)
VIL(max)
t
VBAT
VIHOV(min)
VILOV(max)
t
3
1
2
4
90%
VLR
10%
t
Figure 5. Linear Regulator Timing
16
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Timing and Switching Diagrams (continued)
SDA
(I2C,HSDEN)
VIL(max)
t
VBAT
VIHOV(min)
1
VILOV(max)
4
3
5
2
t
90%
HSD
10%
t
Figure 6. HSD Timing
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6.17 Typical Characteristics
186
Internal Switching Frequency fsw (kHz)
VFB Voltage Reference (V)
1.010
1.005
1.000
0.995
185
184
183
182
181
180
179
178
177
176
0.990
-40 -25 -10
5
20
35
50
65
80
175
-40 -25 -10 5
20 35 50 65 80
Am bient Tem perature (C)
95 110 125
Am bient Tem perature (°C)
Figure 7. Feedback Reference vs Ambient Temperature
95 110 125
Figure 8. Internal Fixed Switching Frequency vs Ambient
Temperature
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
70
70
60
50
7Vin
40
60
50
40
7Vin
30
12Vin
12Vin
20
18Vin
18Vin
30
10
24Vin
fSW = 185 kHz
24Vin
fSW = 185 kHz
20
0
0
0.5
1
1.5
Load Current (A)
2
2.5
0
Figure 9. Efficiency vs Load Current
0.5
1
1.5
Load Current (A)
2
2.5
Figure 10. Efficiency vs Load Current
1.25
0.089
1.20
0.088
Over -Current Voltage Threshold (V)
1.15
HSD Rds ON (Ohms)
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.088
0.087
0.087
0.086
0.086
0.085
0.55
0.50
-40 -25 -10
5
20
35
50
65
80
95 110 125
0.085
-40
Am bient Tem perature (°C)
Figure 11. HSD RDS ON Resistance vs Ambient
Temperature
18
-15
10
35
60
Am bient Tem perature (°C)
85
Figure 12. Overcurrent Voltage Threshold vs Ambient
Temperature
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Typical Characteristics (continued)
1.05
68
67
VBAT = 14 V
VLR Drop out Voltage (V)
Quiescent Current (µA)
66
65
64
63
62
1
ILoad = 650 m A
0.95
0.9
61
60
0.85
59
58
-40 -30 -20 -10 0
0.8
-40
10 20 30 40 50 60 70 80 90
-15
10
35
60
85
Am bient Tem perature (°C)
Am bient Tem perature (°C)
Figure 14. VLR Dropout Voltage vs Ambient Temperature
Figure 13. Quiescent Current vs Ambient Temperature
VSTBY Dropout Voltage (V)
0.72
ILoad = 300 m A
0.67
0.62
0.57
0.52
-40
-15
10
35
60
85
Am bient Tem perature (°C)
Figure 15. VSTBY Dropout Voltage vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The TPS43331-Q1 is a combination of two switched mode synchronous step down controllers and two linearly
regulated power supplies. There is also a protected high side output, controlled by a discrete input to switch
auxiliary input power to other devices in the system. The standby regulator VSTBY is enabled once the input
power from the protected terminal of the battery supply is available to the device. The standby regulator
consumes less than 75 µA with less than 100 µA of load current on the regulated output terminal (VSTBY). In
this condition the device is operating in the low power mode and current consumption from the input voltage
source is minimized. The standby regulator on initial power up has a soft start function (CSLEW); the voltage
ramp on the CSLEW is used to control the output voltage ramp rate of the standby regulator.
The second linearly regulated supply will be controlled through the serial communications. A digital bit assigned
in a register controls if the VLR output is enabled (bit = 1) or disabled (bit = 0). This regulator is powered from
either protected battery input or regulated voltage source. Both linearly regulated supplies can be programmed to
a specified output voltage range based on feedback threshold setting on their respective sense terminals
(VSTBYS and VLRS).
The two switch-mode synchronous step down controllers are configured to drive external NMOS power switches,
and control the energy in the inductor by limiting the current using a resistor current sense feedback. The output
voltage is regulated using external resistor feedback network. The regulated output voltage can be programmed
to a specified range using different feedback thresholds at the VFB(x) terminal. The switch mode step down
controller channel 1 is enabled when the active mode terminal EN is set high (logic 1). The second switch mode
controller channel 2 is activated using the serial communications interface. Both switch mode configuration have
dead time implementation to prevent simultaneous conduction during the switching phase. This is achieved by
monitoring the voltage on the phase node to control gate drive sequencing. To minimize ripple current on the
input line the two buck regulators are switched 180º out of phase. In addition, the SYNCH pin can be used to
alter the switching frequency of both regulators and synchronize it to an external clock operating between
150 kHz and 400 kHz. Although the switching is now synchronous with the external clock, both regulators always
operate 180° out of phase with respect to each other. During initial power up the switch mode regulator has a
soft start function based on the internal oscillator and independent of the external clock signal on the
synchronization input (SYNCH).
The high side switch output is powered from battery and has internal reverse blocking to prevent conduction
when the power input line is bias negative with respect to high side driver output terminal. This output is current
limited in the event of a short to ground condition. The output is controlled through serial communications, a
single bit setting with the default being output OFF state.
The voltage supervisor circuitry monitors the standby voltage output and activates the reset line (pulls RST low) if
the regulated output voltage is below low voltage threshold. There is a power good delay timer function (PGDLY)
which allows the output voltage to stabilize before the RST line is deasserted. This delay time can be
programmed externally using a capacitor. The second voltage supervisor monitors the scaled value of the input
voltage source sensed on the LVWIN terminal. If the voltage sensed at this node is below the internal threshold
setting, the voltage warning output terminal (VBATW) is pulled low. Alternatively if the VBAT input is above an
overvoltage set point (27 V to 31 V), the outputs are disabled and voltage warning output terminal (VBATW) is
pulled low.
The serial communications is using the inter-IC communications (I2C) interface bus. The maximum frequency of
operation is 400-kbaud, and a chip identifier terminal (I2CID) sets the address for communications.
Thermal sensing and protection is implemented for both the linear regulators and the high side driver outputs.
Thermal shutdown on any one output will NOT directly disable any other output circuitry.
20
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Overview (continued)
1.
7.2 Functional Block Diagram
Vinswx (switched battery)
36
Osc
VCP
6
VSTBY
3 kΩ
VBATW
D1
0.1 µF
VBATP
L1
Fuse
D2
1000 µF
47 µF
CSLEW
EN
Enable
SYNCH
2.2 kΩ
Data
82 pF
37
VBATP
38
Buck Switch-Mode
Regulator
SDA
3.3 V
2.2 kΩ
Clock
82 pF
SCL
VINSB
VSTBY
I2CID
21
Voltage
Monitor for
OV/UV
Reset
PGDLY
Switching
Phase Control
14
Soft-Start
Control
5
10
34
24
29
Thermal
sense
27
28
Enable
26
I2C
12
3
Programmable Standby
Linear Regulator
2
4
RS1
VBUCK 1
R1
Q2
ISHI1
C1
R2
ISLO1
AGND
VFB1
VCMP1
10 µF
VGT2
Q3
CBS2
L3
RS2
VBUCK 2
R4
ISHI2
C4
R5
ISLO2
VFB2
VCMP2
R6
C5
C6
VSTBY
VSTBY
R7
VSTBYS
C7
R8
Thermal
sense
20
Voltage
supervisory
with POR
delay
19
18
1
VGB1
L2
0.1 µF
23 PH2
VGB2
Q4
22
11
0.1 µF
AGND
25
Switching
Phase Control
13
16
CBS1
PH1 0.1 µF
C3
Cd
VBAT
32
10uF
PGND
C2 R3
Buck SwitchMode Regulator
3 kΩ
RST
31
33
15
0.1 µF
R12
R11
3.3 V
Charge
pump
VBATP
LVWIN
Ext. Clock
35
High-Side
Driver
Interrupt
Vbattery
Clock
0.1uF
Q1
VGT1
Overvoltage
Disable
Charge Pump
Voltage
Internal Vref
Monitor
8
VINLR
C8
Programmable
Linear Regulator
9
7
High-Side Driver With
Reverse Battery and
Current-Limit Protection
Bandgap
Reference
VINLR
17
VLR
VLRS
VLREG
R9
C9
R10
HSD
HSD
10 µF
Thermal
Sense
30
PGND
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Figure 16. Typical Application Schematic
7.3 Feature Description
7.3.1 Unregulated Battery Input Voltage (VBAT)
This input terminal will have an external input filter and voltage suppression above 40 V for protection. The input
is used to provide the operating voltage for the high side driver output, and used for sensing over voltage
condition in the system. The over voltage detection circuitry has hysteresis for noise rejection.
7.3.2 Protected Unregulated Battery Input Voltage (VBATP)
This terminal provides the power source for internal circuitry to bias band-gap reference, oscillator and other
circuitry in the device. The voltage on this terminal is used to sense for system undervoltage condition.
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Feature Description (continued)
7.3.3 Low-Voltage Warning Input (LVWIN)
This input is used to detect low voltage condition. The input voltage source is scaled using external resistor
network (programmable) to set the threshold for detection of low voltage condition. Once the input voltage is
below the set threshold the low voltage warning output terminal is pulled low (VBATW).
7.3.4 Voltage Warning Output (VBATW)
This is an open drain output which is pulled up to supply with an external resistor. This output is asserted low
when either of the following conditions is satisfied:
• Detection of low-voltage condition
• Detection of overvoltage condition
If the fault condition is removed the VBATW output is deasserted (output goes high).
7.3.5 Low-Voltage Reset (RST)
This output indicates if there is a low voltage on the standby regulator output (VSTBY). The output is deasserted
once the standby regulator achieves proper regulation and after the power delay timer has expired. This low
voltage reset circuitry is functional for voltages above 0.5 V on the standby regulator output terminal. Additionally
the low voltage reset output will remain low if the standby regulator input voltage is in the undervoltage lockout
mode. If the PGDLY and VSTBYS pins are both high, the nRST pin is high. The VSTBYS voltage must be higher
than 0.93 V (typical) and the nRST pin is pulled low 10 µs (typical) after the VSTBYS pin goes low.
7.3.6 Power-Good Delay Timer Input (PGDLY)
The capacitor on this terminal programs power good delay timer function. A current source on this pin charges
an external capacitor once the standby regulator achieves proper regulation. Once the voltage on the capacitor
exceeds the internal threshold the internal comparator will deassert the reset output line. The external capacitor
is discharged (reset) once the RST output is deasserted, and so any subsequent power up sequence will start
from zero time for the power good delay. The power good delay is not initiated as a result of external device
asserting the reset output terminal.
7.3.7 Active Mode Enable Input (EN)
This input pin commands different modes of operation. When asserted low the device will enter low quiescent
standby mode, with only the standby regulator ON. Once the input is asserted high the device is in active mode
and regulator output control is achieved by discrete inputs and serial communications. The input is TTLcompatible with hysteresis for noise rejection. There is an internal pull down to ensure a default state of standby
mode.
7.3.8 Slew Rate Control Capacitor Input (CSLEW)
This pin provides the soft-start function for an internal reference used by the standby linear voltage regulator. An
internal current source will charge an external capacitor to produce a linear voltage ramp at start up for the
internal reference. This will be used to limit the slew rate of the output voltage of the standby regulator. An
internal low side switch is used to discharge the capacitor in accordance will the operating mode requirements for
slew rate control.
The soft start time must be greater than dtss > 2π (LC)1/2.
C = dt × I / dv
where
•
•
•
22
dv = 1.2 V
I = 1.6- to 2.4-µA range
dt > 2π (LC)1/2
(1)
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Feature Description (continued)
7.3.9 Charge Pump Capacitor Input (VCP)
This pin has an external capacitor to provide storage for an internal charge pump.
This charge pump is activated at supply voltages less than approximately 9 V to appropriately supply the highside driver. When active, the quiescent current is increased.
7.3.10 Power Ground (PGND)
This pin is the power ground reference for the device. All switching nodes are referenced to this ground.
7.3.11 Analog Ground Reference (AGND)
This pin is reference ground for ALL non-power and non-switch-mode related ground termination inside the
device.
7.3.12 Inter-IC Communications Interface (I2CID)
The serial communications interface is a 7-bit address for controlling the switch mode controller 2 (VBUCK 2),
linear regulator (VLR) and high side driver output (HSD). There are two lines SCL and SDA to control the
communications between the master and the slave. An I2CID terminal is used to address the IC in a system
where multiple IC’s may be implemented. The SDA terminal has an internal FET switch to pull the SDA low as
an acknowledgment signal back to the main controller. An active high allows access to the register.
7.3.13 Clock Input (SCL)
This pin is an input pin for a clock signal input from the master control. The clock signal is used to synchronize
the data communications between the master device and the slave (TPS43331-Q1). The input signal will be TTLcompatible with hysteresis for noise rejection.
7.3.14 Data Line (SDA)
The pin is a data line communications between the master and slave device. The input signal is TTL-compatible
with hysteresis for noise rejection. An internal pull down driver will provide an acknowledgment signal back to the
master controller.
7.3.15 Interface Chip Identifier (I2CID)
The pin is used as a chip identification input for the I2C interface between the master and the slave device. The
input signal is TTL-compatible with hysteresis for noise rejection. The state of the input signal is reflected in the
I2C chip address byte 0. The value of the signal on this terminal is latched on a POR condition. A low leakage
internal pull-down is implemented to ensure the default state is zero.
The device requires a three-byte access from the microcontroller (Chip address, Register address and data).
7.3.16 Switch Mode Regulators
There are two switch-mode controllers when configured with external power switches form the buck (step-down)
regulators. One switch-mode regulator is controlled by an enable input control (EN) and the second is controlled
by a bit using the serial communications interface.
Short-circuit detection is achieved by current sensed through an external sense resistor in series with the
inductor. The current limit is applied on a cycle-by cycle basis. Once overcurrent is detected the output is
disabled for the remainder of the cycle, and is enabled on the next clock edge.
7.3.17 Upper FET Gate Drive Outputs (VGT1 and VGT2)
These outputs are the gate drive signals for the external high side FETs for each switch-mode controller.
The output voltage is clamped to prevent excessive gate drive voltage to the external MOS devices. These
outputs are a push-pull configuration and are current limited for charging a capacitive load.
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Feature Description (continued)
7.3.18 Lower FET Gate Driver Outputs (VGB1 and VGB2)
These outputs are the gate drive signals for the external low side FETs for each switch-mode controller. The
switching signal is 180 degrees out of phase with the upper gate drive signals for each controller. The lower gate
drive controls the FET for synchronous switching. These output signals are clamped to prevent excessive gate
voltage to the external MOS devices. These outputs are a push-pull configuration and are current limited for
charging a capacitive load.
7.3.19 Bootstrap Capacitor Input (CBS1 and CBS2)
These pins are the bootstrap capacitor inputs for switcher 1 and switcher 2 respectively. These capacitors act as
the voltage supply for the upper gate drive circuitry. The capacitors are re-charged on every low side
synchronous switching action. In the case of 100% duty cycle for the upper FET, the device will automatically
reduce the duty cycle to approximately 95% on every fifth cycle to allow these capacitors to re-charge.
7.3.20 Phase Reference for High-Side Bootstrap Supply (PH1 and PH2)
These pins provide a floating voltage reference for the high-side FET gate drive circuitry for switcher 1 and
switcher 2 respectively. These nodes are used to monitor the status of the upper external FETs, and allow
switching of the lower external FETs without shorting the supply.
7.3.21 Current Sense High-Side (ISHI1 and ISHI2)
These are the high-side current sense resistor node inputs for switcher 1 and switcher 2 respectively. The
common mode range of the combined high-side and low-side current sense inputs supports the entire output
voltage range.
7.3.22
Current Sense Low-Side (ISLO1 and ISLO2)
These are the low-side current sense resistor node inputs for switcher 1 and switcher 2 respectively. The
common mode range of the combined high-side and low-side current sense inputs supports the entire output
voltage range.
7.3.23 Regulated Output Sense Voltage Feedback (VFB1 and VFB2)
These are the input pins for the voltage output feedback signals for switcher 1and switcher 2 respectively. The
external resistor network setting on these pins programs the desired regulated output voltages for each switchmode converter.
7.3.24 Feedback Compensation Input (VCMP1 and VCMP2)
These are the input pins for the converter compensation feedback for switcher 1 and switcher 2 respectively.
7.3.25 Synchronization Input (SYNCH)
This is an input pin for feeding an external clock to synchronize the switching frequency of both switch-mode
regulators. The IC will detect a small number of edges (2 to 5) prior to recognizing a valid external clock input
signal and synchronizing the internal operation with an external clock input. The regulator operates with an
external input clock signal until a low voltage reset or a command to go into a sleep mode.
7.3.26 Standby Linear Regulator Input (VINSB)
This is the input pin for the operating voltage of the standby regulator. The voltage source for the standby
regulator requires an external blocking diode in the module for reverse supply conditions. This input pin requires
the necessary filtering and protection against positive and negative transients to prevent damage to the IC (see
Figure 16).
24
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Feature Description (continued)
7.3.27 Standby Regulator Output (VSTBY)
This is the regulated output of the standby regulator, and derives the voltage source from the VINSB terminal.
The regulator has an internal linear current limit for protection against shorts to ground. The output voltage will
recover to the specified range once the fault condition is removed. This output remains within the tolerance of the
specification during positive transient events on the input. An under-shoot condition during any load transient
event will not assert a reset condition on the RST output, proving the load transient is within the specified range.
Once the regulator drops-out due to low input voltage on VINSB, the output tracks the input voltage minus the
saturation voltage of the pass device. The device will enter thermal shut down if the local die temperature
exceeds the thermal shut-down threshold. The thermal shut-down has hysteresis such that the output enables
once the local die temperature falls below the disable threshold. If the output falls below the specified low voltage
reset, the IC will notify this condition by asserting the rest line RST low.
7.3.28 Standby Regulator Sense Voltage (VSTBYS)
This pin is used to program the regulated output voltage to a range specified in the parametric table. An external
resistor network is used to ratio the output voltage and fed back into the VSTBYS pin.
7.3.29 Switched Linear Regulator Input (VINLR)
This is the input pin for the operating voltage of the switched linear regulator. The voltage source for this
regulator requires an external blocking diode in the module for reverse supply conditions. This input pin requires
the necessary filtering and protection against positive and negative transients to prevent damage to the IC (see
Figure 16).
7.3.30 Switched Linear Regulator Output (VLR)
This is the regulated output of the switched linear regulator, and derives the voltage source from the VINLR
terminal. The regulator has an internal linear current limit for protection against shorts to ground. The output
voltage will recover to the specified range, once the fault condition is removed. This output remains within the
tolerance of the specification during load transient event on the output line. The output is disabled in the event
VBAT exceeding the overvoltage shut-down threshold VOVSD. The output will be enabled once the VBAT input
voltage falls below the internal set threshold (with hysteresis).
Once the regulator drops-out due to low input voltage on VINLR, the output tracks the input voltage minus the
saturation voltage of the pass device. The device will enter thermal shut down if the local die temperature
exceeds the thermal shut-down threshold. The thermal shut-down has hysteresis such that the output enables
once the local die temperature falls below the disable threshold.
7.3.31 Switched Linear Regulator Sense Voltage (VLRS)
This pin is used to program the regulated output voltage to a range specified in the parametric table. An external
resistor network is used to ratio the output voltage and fed back into the VLRS pin.
7.3.32 High-Side Driver Output (HSD)
This pin is the output of the high side driver (switched input voltage). The output is enabled through a bit in the
I2C data register. If the voltage on the VBAT supply exceed the overvoltage shutdown threshold VOVSD this
output is disabled. Upon return from the fault condition the output recovers to the state set by the enable bit
(HSDEN) in I2C data register without any intervention from the system. The output is stable during any soft-start
conditions or specified load transients. This output is protected against:
• Short to module supply
• Short to module ground
• Short through the load to –1 V
• Unpowered short to module supply
• Reverse supply (–13 V)
The output has short circuit protection with a linear current limit and thermal shutdown with hysteresis.
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Feature Description (continued)
If the local die temperature exceeds the thermal shutdown detection threshold this output is disabled. This output
is enabled once the local die temperature falls below the detection threshold with hysteresis providing the
HSDEN bit is set.
The invoking of thermal shut down on this output does not directly affect any other outputs or circuitry in the IC.
The operation of the switch is not affected during the re-circulation of an inductive load providing the negative
voltage applied to this pin is within the specified limits
7.4 Device Functional Modes
7.4.1 Operating Mode Definition
Figure 17 shows the operating modes of the TPS43331-Q1.
Battery Connect
Undervoltage
lockout
Power-On Reset
Undervoltage
lockout
Standby regulator
slew rate control
Power Good Delay
Timer not expired
Standby regulator
Out of regulation
Low-voltage Reset
Standby regulator
Out of regulation
Low voltage reset
Output Deasserted
Low voltage reset
Output Asserted Low
Enable Input Low
Enable Input
Low
Standby Mode
Active Mode
Enable Input High
Standby regulator
In regulation
Figure 17. Operating Modes
26
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7.5 Programming
7.5.1 Register Definition for I2C
7.5.1.1 Chip Address Byte
The IC supports two addresses by using bit 4 of the chip address byte and the I2CID input. The state of the
I2CID input pin is read into bit 3 of the chip address byte (indicated by X in the frame above).
The valid chip addresses for writing to this IC are $0001000 (0x08) and $0001100 (0x0C), since the LSB of the
chip address byte is a read/write bit, these two addresses translate into hex values of 0x10 and 0x18
respectively.
Frame format requires two-byte access from the master controller.
• The first byte contains the address information
• The second byte contains the data information
Table 1. Frame Format
CHIP ADDRESS BYTE 0
0
0
1
X
0
REGISTER ADDRESS
0
0
A
0
0
0
0
0
0
DATA BYTE 0
0
1
A
7
6
5
4
3
2
1
0
A
P
LSB
0
MSB
S
The data format/transfer will be the following order:
1. MSB first to LSB last; Bit 7 of each byte is the MSB. Bit 0 of each byte is the LSB.
2. Bit 0 (LSB) in the address byte defines the read/write bit; a value of 0 indicates a data write.
3. The bit marked X in the address byte indicates the state of the I2CID input.
Transmission format:
1. The data transfer begins with a start signal (S), where the SDA transitions from high to low while SCL is high
(see Figure 18).
2. After 8 bits are transmitted and detected the IC (TPS43331-Q1) will send an acknowledge pulse (A) to the
master.
3. After each successive writes of 8 bits, the IC sends an acknowledge pulse to the master.
4. The message communications is completed (stop condition P) when SDA transitions from low to high while
SCL is high.
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08h Address case
SDA
1
SCL
2
3
4
5
6
7
8
9
Acknowledge
Start Condition
Stop Condition
0Ch Address case
SDA
SCL
1
2
3
4
5
6
7
8
9
Acknowledge
Start Condition
Stop Condition
ID rejected
SDA
SCL
1
2
3
4
5
Start Condition
(1)
6
7
8
9
Acknowledge
Stop Condition
Bit 8 is used for read or writer options, with:
Bit 8 = 1 is read
Bit 8 = 0 is write
Figure 18. I2C Communications
If a transfer is interrupted by a stop condition, the partial byte transmission shall not be latched. Only the prior
messages transmitted and acknowledged are latched.
28
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7.6 Register Map
7.6.1 Data Register
Figure 19. Data Register Format
7
X
R/W-0
6
X
R/W-0
5
X
R/W-0
4
X
R/W-0
3
X
R/W-0
2
SW2EN
R/W-0
1
LREN
R/W-0
0
HSDEN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; –n = value after reset
Table 2. Data Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7–3
X
R/W
00000
X
SW2EN
R/W
0
2
SW2EN default state = 0, switcher 2 is OFF (disabled)
SW2EN = 1, switcher 2 ON (enabled)
1
LREN
R/W
0
LREN default state = 0, the switched linear regulator (VLR) is OFF
LREN = 1, the switched linear regulator (VLR) is ON
0
HSDEN
R/W
0
HSDEN default state = 0, the high side switch is OFF
HSDEN = 1, the high side switch is ON
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS43331-Q1 is a combination of two switched-mode, synchronous step-down controllers and two linearlyregulated power supplies. These devices are configured to drive external NMOS power switches and control the
energy in the inductor by limiting the current using a resistor current sense feedback. The output voltage is
regulated using an external resistor feedback network. The regulated output voltage can be programmed to a
specified range using different feedback thresholds at the VFB(x) terminal. To minimize ripple current on the
input line, the two buck regulators are switched 180º out of phase.
The protected high-side output is controlled by a discrete input to switch auxiliary input power to other devices in
the system. The standby regulator VSTBY is enabled when the input power from the protected terminal of the
battery supply is available to the device. The standby regulator consumes less than 75 μA, with less than 100 μA
of load current on the regulated output terminal (VSTBY).
8.2 Typical Application
The calculations from the Buck Regulators section result in the schematic shown in Figure 20.
The design requirements for the switching regulator design in Figure 20 are listed in Table 3.
Assume Type III Compensation network for each buck regulator.
30
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JP1
VBAT
VBAT
8
J1
VBAT
C39
2
0.1uF
D
7
G
10
2
4.7uF
VBUCK 1
GND
J3
PH1
L1
22uH
GND
Si4946EY
R17
2
6
R19
Q1B
1
C21
R26
4
GND
0
0.1uF
C24
R28 GND
100k
6
0.1uF
GND
7
C25
10uF
R30
R31
0
VBAT
VLR
J6
8
9
698k
1
GND
VSTBY
SDA
R39
SCL
100k
SW_REG_SYNC
VBATW
10
11
12
13
14
15
VBATW1
16
VBAT
R41
R37
17
4.7M
18
GND
19
1M
VGT1
VINSB
CBS1
CSLEW
VCMP1
VCP
VFB1
VLRS
ISLO1
VLRIN
ISHI1
VLR
PGND
EN
ISHI2
SDA
ISLO2
SCL
VFB2
SYNCH
VCMP2
LVWIN
CBS2
#VBATW
VGT2
VBAT
PH2
HSD
PGDLY
#RST
VGB2
VBATP
I2CID
C22
3.3n
0.1uF
C32
C33
C34
1000pF
0.1uF
1000pF
1200pF
GND
32
31
30
GND
29
R32
17.4k
GND
28
C26
27
R33
C28
25
C27
29.4k
3.3n
26
1200pF
C29
R34
VBAT
0.1uF
24
220p
23
Q2A
22
R36
21
2
VBAT
40.2k
C30
C31
4.7uF
4.7uF
TP14
R40
GND
PH2
L2
22uH
Si4946EY
20
1
R42
Q2B
100k
4
GND
GND
49.9
R38
C40
R29
10
G
R35
1.1k
G
10
GND
GND
C18
10k
GND
GND
29.4k
220p
33
GND
RST_OUT/
40.2k
R27
RST/
GND
1.1k
R23
C23
6
VSTBY
1
TP12
R20
0.1uF
J5
VBUCK 1
49.9
R25
GND
34
R18
GND
C20
36
VBAT_SW1
2
D
S
Si4946EY
35
2.2uF
C37
J4
GND
2
2
1
0.03
+
D
5
2
SW_REG1_ON
VSTBY
37
100uF
TP11
1000pF
D
S
VLR
5
PH1
C17
G
3
2
3
VSTBYS
C15
8
2
150k
4
D
7
STBY
J7
38
3
R24
VGB1
C16
2
TPS43331DAC
AGND
PwrPad
10uF
1
D
S
U4
GND
+
10
1
100k
C19
VSTBY
0.03
D
5
R21 GND
1
1
1
GND
2
1
470uF
R16
C14
C36
C35
100uF
2.2uF
VBUCK 2
VBUCK 2
2
C38
+
C13
4.7uF
D
S
D1
GND
Q1A
1
2
1
1
GND
1000pF
Si4946EY
GND
GND
GND
GND
GND
GND
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Figure 20. Design Circuit Schematic
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8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Requirements
PARAMETER
VALUE
Input voltage
8 V to 26 V (14 V typ)
Output voltage buck regulator 1– VBUCK 1
Min = 4.75 V, Max = 5.25 V
Output voltage buck regulator 2 – VBUCK 2
Min = 3.135 V, Max = 3.465 V
Converter switching frequency, fSW
250 kHz
Maximum output current on buck regulator 1– IO
2A
Maximum output current on buck regulator 2 – IO
1.5 A
Maximum ripple current Iripple
0.2 × IO
8.2.2 Detailed Design Procedure
8.2.2.1 Type II Compensation
L
C2
VBUCK
ESR
(CO)
R2
R1
FB
C1
COMP
Error
Amplifier
CO
RS2
+
±
1V
Figure 21. Type II Compensation
The LC output filter gives a Double Pole which has a –180° phase shift.
1
fLC
(Hertz)
2S LCO
(2)
The ESR of the output capacitor, CO, gives a zero that has a 90° phase shift.
1
fESR
(Hertz)
2S u CO u ESRCo
(3)
The values of R1 and RS2 are chosen based on the desired VBUCK.
R1 RS2
VBUCK Vref u
(Volt)
RS2
where
•
32
Vref = 1 V
(4)
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Use the following equations to select the resistor vales:
Select RS2 = 10 kΩ
RS2(VBUCK Vref )
R1
Vref
(5)
10000(VBUCK 1)
R1
1
fc u Vramp u R1
R2
VBAT u fLC
(6)
where
•
•
Vramp = 1.8 V, VBAT = typical input operating voltage
fc = fSW × 0.1 (the cutoff frequency, when the gain is 1 is called the unity gain frequency)
(7)
The fc is typically 1/5 to 1/10 of the switching frequency.
Use Equation 8 to calculate the PWM modulator gain (K).
VBAT
K
Vramp
(8)
Use Equation 9 to calculate the amplifier gain (Av).
R2
Av
R1
fc
fz
(Hertz)
K
fp fc u K(Hertz)
(9)
(10)
(11)
C1
10
2S u R2 u fLC
(12)
C2
C1
( S u R2 u C1 u fSW ) 1
(13)
Open Loop Error
Amp Gain
fp = 1 / (2p × R2 × (C1 × C2 / C1 + C2))
Gain (dB)
fz = 1 / (2p × R2 × C1)
20log (R2 / R1)
1 / (2p × R1 × C2)
Modulator and
Filter Gain
Compensation Gain
Closed Loop Gain
0.1 × fLC
fLC
fESR
0.5 × fSW
Frequency
Figure 22. Type II Bode Plots
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8.2.2.2 Type III Compensation
L
C2
VBUCK
R3
ESR
(CO)
R1
C3
R2
C1
FB
COMP
Error
Amplifier
CO
RS2
+
±
1V
Figure 23. Type III Compensation
fc = fSW × 0.1 (the cutoff frequency when the gain is 1 is called the unity gain frequency).
The fc is typically 1/5 to 1/10 of the switching frequency double pole frequency response due to the LC output
filter.
The LC output filter gives a Double Pole which has a –180° phase shift.
1
fLC
(Hertz)
2S LCO
(14)
The ESR of the output capacitor, CO, gives a zero that has a 90° phase shift.
1
fESR
(Hertz)
2S u CO u ESRCo
(15)
VBUCK
Vref u (R1 RS2)
(Volt)
RS2
where
•
Vref = 1 V
(16)
Use Equation 17 to calculate the PWM modulator gain (K).
VBAT
K
Vramp
where
•
•
Vramp = 1.8 V
VBAT = typical input operating voltage
Use Equation 18 to calculate the amplifier gain (Av).
R2 u (R1 R3)
Av
R1 u R3
C1 C2
fP1
(Hertz)
2S u R2 u (C1 u C2)
fP2
fZ1
fZ2
34
1
(Hertz)
2S u R3 u C3
1
(Hertz)
2S u R2 u C1
1
(Hertz)
2S u (R1 R3) u C3
(17)
(18)
(19)
(20)
(21)
(22)
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Use the following guidelines for compensation components:
Make the two zeroes close to the double pole (LC); for example, fZ1 ≈ fZ2 ≈ 1 / 2π × (LCO)1/2.
1. Make the first zero below the filter double pole (approximately 50% to 75% of fLC).
2. Make the second zero at filter double pole (fLC).
Make the two poles above the cross-over frequency fc.
1. Make the first pole at the ESR frequency (fESR).
2. Make the second pole at 0.5 the switching frequency (0.5 × fSW).
Use the following equations to select the resistor values:
Select RS2 = 10 kΩ
RS2 u VBUCK Vref
R1
(Ohm)
Vref
R1
R2
10000 u VBUCK
1
fc u Vramp u R1
fLC u VBAT
1
(23)
(Ohm)
(24)
(Ohm)
(25)
Calculate C1 based on placing a zero at 50% to 75% of the output filter double pole frequency.
1
C1
(Farad)
S u R2 u fLC
(26)
Calculate C2 by placing the first pole at the ESR zero frequency.
C1
C2
(Farad)
2S u R2 u C1 u fESR 1
(27)
Set the second pole at 0.5 the switching frequency and also set the second zero at the output filter double pole
frequency.
R1
R3
(Ohm)
§ fSW
1 ·
u
¨
¸ 1
fLC ¹
© 2
(28)
1
C3
(Farad)
S u R3 u fSW
(29)
Open Loop Error
Amp Gain
fP1
fP2
fZ2
Gain (dB)
fZ1
20log R6(R4 + R9) / (R4 × R9)
20log (R6 / R4)
20log (10)
Modulator Gain
Compensation Gain
Closed Loop Gain
fLC
fESR
Frequency
Figure 24. Type III Bode Plots
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8.2.2.3 Component Calculations
8.2.2.3.1 Buck-Controllers (VBUCK1, VBUCK2)
Use Equation 30 to calculate and select the desired inductor ripple current (ΔIL).
ΔIL= Iripple = 0.4×IO(max)
where
•
IO(max) = Maximum output current
(30)
The typical inductor ripple current is between 20% to 40% of the maximum output current.
Use Equation 31 to calculate the value of the inductor (L).
(VBAT(max) VBUCK )VBUCK
L
(Henry)
fSW u Iripple u VBUCK(max)
where
•
•
fSW is the switching frequency of the regulator
Iripple = Allowable ripple current in the inductor, 20% to 40% of maximum IO(max)
(31)
Use Equation 32 to calculate the value of the the rms and peak current flowing in the inductor is.
IL(RMS)
IO2
Iripple2
(Ampere)
12
(32)
Use Equation 33 to calculate the inductor peak current.
Iripple
IL(peak) IO
(Ampere)
2
(33)
Use Equation 34 to calculate the value of the output voltage ripple.
§
·
1
'VBUCK 'IL ¨ ESR
¸ (Volt, Peak-to-Peak)
8 u fSW u CO ¹
©
(34)
Usually the first term is dominant. The output ripple voltage is typically within the tolerance of the output
specification.
Use Equation 35 to calculate the value of the output capacitor.
L(IO(max)2
CO
VBUCK(max)2
IO(min)2 )
VBUCK(min)2
(Farad)
where
•
•
IO(max) is the maximum output current
IO(min) is the minimum output current
(35)
The difference between the maximum to minimum output current is the worst case load step in the system
where:
VBUCK(max) is the maximum tolerance of the regulated output voltage.
VBUCK(min) is the minimum tolerance of the regulated output voltage.
8.2.2.4 Power Dissipation
The power dissipation is largely dependent on the MOSFET driver current and input voltage. The drive current is
proportional to the total gate charge of the external MOSFET.
PGate = Qg × VDR × fSW (Watt)
(36)
Assuming both high-side and low-side MOSFETs are identical in a synchronous configuration, use Equation 37
to calculate the total power dissipation.
Pcontroller1 = 2 × Qg × fSW × VBAT (Watt) per channel
36
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The total power dissipation for the dual-channel controller is:
Pcontroller 1 and 2 = 4 × Qg × fSW × VBAT (Watt)
(38)
Use Equation 39 to calculate the device power consumption.
PIC = Iq × VBAT (Watt)
(39)
Use Equation 40 to calculate the power of the standby linear regulator.
PSTBY_REG = (VINSB – VSTBY ) × IVSTBY (Watt)
(40)
Use Equation 41 to calculate the power of the linear regulator.
PLIN_REG = (VINLR – VLR ) × IVLR (Watt)
(41)
Use Equation 39 to calculate the power of the high-side driver.
PHSD = IHSD × 0.6 (Watts ) for up to 300-mA output current
(42)
Therefore, use Equation 43 to calculate the total power dissipation (PTotal).
PTotal = Pcontroller 1 and 2 + PSTBY_REG + PLIN_REG + PIC + PHSD (Watt)
(43)
8.2.2.5 Buck Regulators
8.2.2.5.1 Buck Regulator 1 (VBUCK 1)
8.2.2.5.1.1 Step 1. Calculate the Inductor Value
Use Equation 31 to find the inductor value and assume an inductor ripple current of 0.8 A.
L
VBAT(max)
VBUCK VBUCK
fSW u Iripple u VBAT(max)
26 5 5
3
250 u 10 u 0.8 u 26
20.2 u 10
6
(Henry)
(44)
L = 20.2 µH, use a value of 22 µH
8.2.2.5.1.2 Step 2. Inductor Peak Current
Use Equation 33 to calculate the peak inductor current (IL(peak)).
Iripple
0.8
IL(peak) IO
2
2.4 (Ampere)
2
2
(45)
IL(peak) = 2.4 A
8.2.2.5.1.3 Step 3. Calculating the Output Capacitance (CO)
Use Equation 35 to calculate the output capacitance.
L(IO(max)2 IO(min)2 )
22 u 10 6 (22 (20 u 10 3 )2
CO
VBUCK(max)2 VBUCK(min)2
5.152 4.852
29.3 u 10 6 (Farad)
(46)
Assume a tolerance of ±3% to allow for some margin, the minimum IO current is 20 mA. Using Equation 34, the
value of the minimum output capacitor, CO(min), is 29.3 µF. Considering temperature variations and manufacture
tolerance, choose a value of 68 µF or greater for CO(min).
For this design, the value of CO is 100 µF.
8.2.2.5.1.4 Step 4. Calculating Loop Compensation Values
Use Equation 14 to determine the double pole:
1
1
fLC
2S LCO 2 u 3.142 22 u 10 6 u 100 u 10 6
3990 (Hertz)
(47)
fLC = 3.39 kHz
Use Equation 15 to determine the zero due to the ESR of the output capacitor CO with ESR = 60 mΩ:
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fESR
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1
2S u CO u ESR
1
2 u 3.142 u 100 u 10
6
26.5 u 103 (Hertz)
u 0.06
(48)
fESR = 26.5 kHz
fC = 0.08 × fSW = 20 kHz
Us Equation 24 and assume R27 = 10 kΩ to find the value of R23:
10000 u (VBUCK 1) 10000 u (5 1)
R23
40 u 103 (Ohm)
1
1
(49)
R23 = 40.2 kΩ
Use Equation 25 to find the value of R25:
fc u Vramp u R23 20 u 103 u 1.8 u 40.2 u 103
R25
fLC u VBAT
3.39 u 103 u 14
30493 (Ohm)
(50)
R25 = 30.5 kΩ, Choose R25 = 29.4 kΩ
Use Equation 26 to find the value of C20:
1
1
C20
S u R25 u fLC 3.142 u 29.4 u 103 u 3.39 u 103
3129 u 10 12 (Farad)
(51)
C20 = 3.13 nF, Choose C20 = 3.3 nF
Use Equation 27 to find the value of C23:
C23
C20
(2S u R25 u C2 u fESR ) 1
3.3 u 10
9
(2 u 3.142 u 29.4 u 103 u 3.3 u 10
9
u 26.5 u 103 ) 1
213 u 10
12
(Farad)
(52)
C23 = 213 pF, Choose C23 = 220 pF
Us Equation 28 to find the value of R20:
R20
R23
40 u 103
§ fSW
1 ·
u
¨
¸ 1
fLC ¹
© 2
§ 250 u 103
·
1
u
¨¨
¸¸ 1
3
2
3.39 u 10 ¹
©
1.1 u 103 (Ohm)
(53)
R20 = 1.12 kΩ, Choose R20 = 1.1 kΩ
Use Equation 29 to find the value of C18:
1
1
C18
S u R20 u fSW 3.142 u 1.1 u 103 u 250 u 103
1.142 u 10 9 (Farad)
(54)
C18 = 1142 pF, Choose C18 = 1200 pF
8.2.2.5.2 Buck Regulator 2 (VBUCK 2)
Using the same method for calculating the component values for Buck Regulator 2, with the set output
conditions, the following values were selected.
8.2.2.5.2.1 Step 5. Calculate the Inductor Value
Use Equation 31 to find the inductor value and assume an inductor ripple current of 0.3 A:
L = 19.2 µH, use a value of 22 µH
8.2.2.5.2.2 Step 6. Inductor Peak Current
From Equation 33, the peak inductor current is:
IL(peak) = 1.65 A
38
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8.2.2.5.2.3 Step 7. Calculating the Output Capacitance (CO)
Assume a tolerance of ±3% to allow for some margin and a minimum IO current of 20 mA. Use Equation 35 to
calculate the value of the output capacitor:
CO(min) = 32.7 µF, with temperature variations and manufacture tolerance choose a value of 100 µF for this
design.
CO = 100 µF
8.2.2.5.2.4 Step 8. Calculating Loop Compensation Values
Use Equation 14 to determine the double pole:
fLC = 3.39 kHz
Use Equation 15 to determine the zero from the ESR of the output capacitor, CO, with ESR = 60 mΩ:
fESR = 26.5 kHz
fc = 0.8 × fSW = 20 kHz
Use Equation 24 and the R32 value of 17.4 kΩ:
R34 = 40.2 kΩ
Use Equation 25:
R33 = 30.3 kΩ, Choose R33 = 29.4 kΩ
Use Equation 26:
C26 = 3.129 nF, Choose C26 = 3.3 nF
Use Equation 27:
C29 = 213 pF, Choose C29 = 220 pF
Use Equation 28:
R35 = 1.1 kΩ , Choose R35 = 1.1 kΩ
Use Equation 29:
C27 = 1142 pF, Choose C27 = 1200 pF
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8.2.3 Application Curves
40
Figure 25. High-Side Driver (HSD) Output Power-Down
Delay From I2C Bit Disable, ∆t = 43 µs
Figure 26. High-Side Driver (HSD) Output Power-On Delay
From I2C Bit Enable, ∆t = 47 µs
Figure 27. High-Side Driver (HSD) Output Turnon Delay
From I2C Bit Enable, ∆t = 7.6 µs
Figure 28. Load Step on VBUCK 1 From 0 A to 2 A, VOUT1
Droop = 150 mV
Figure 29. Load Step on VBUCK 1 From 2 A to 0 A, VOUT1
Overshoot = 148 mV
Figure 30. Load Step on VBUCK 2 From 0 A to 1.3 A, VOUT1
Droop = 102 mV
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Figure 31. VBUCK 1 and VBUCK 2 Switching 180° Out of
Phase
Figure 32. VBUCK 1 Turnon Delay From Enable Going
High, ∆t = 200 µs
Figure 33. VBUCK 1 Power-On Delay From Enable Going
High, ∆t = 2.8 ms (ILoad = 1.3 A)
Figure 34. VBUCK 2 Turnon Delay From I2C Enable Bit
Going High, ∆t = 164 µs
Figure 35. VBUCK 2 Turnoff Delay From I2C Enable Bit
Going Low, ∆t = 7.2 µs
Figure 36. VBUCK 2 Power-On Delay From I2C Enable Bit
Going High, ∆t = 2.24 ms
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Figure 37. Linear Regulator (VLR) Turnon Delay From I2C
Enable Bit Going High, ∆t = 12 µs
Figure 38. Linear Regulator (VLR) Power-On Delay From
I2C Enable Bit Going High, ∆t = 61.2 µs
Figure 39. Linear Regulator (VLR) Turnoff Delay From I2C Enable Bit Going Low, ∆t = 6.4 µs
42
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8.3 System Example
8.3.1 Multiple Power Supply Configuration for Vehicle Audio Applications
Figure 40 shows an example of configuration for car-audio power-supply application. Other combinations are
possible depending on the system requirements.
VBAT
VSTBY-3.3 V
Bias
Standby Regulator
VLR-2.5 V
Voltage
Supervisor
Linear Regulator
HSD-VBAT
Serial Interface
2
(I C)
High-Side Driver
VBUCK 1-1.5 V
SMPS Controller 1
Active Mode
VBUCK 2-10 V
SMPS Controller 2
VSTBY-1.8 V
Standby Regulator
Bias
VLR-8.5 V
Voltage
Supervisor
Linear Regulator
HSD-VBAT
Serial Interface
2
(I C)
High-Side Driver
VBUCK 1-3.3 V
SMPS Controller 1
Active Mode
VBUCK 2-5 V
SMPS Controller 2
Figure 40. Multiple Power Supply for Vehicle Audio
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9 Power Supply Recommendations
Apply 5 V to 30 V to the VBAT and VBATP pins. Apply 1.8 V to 30 V to the VINSB and VINLR pins.
10 Layout
10.1 Layout Guidelines
10.1.1 Grounding and Circuit Layout Considerations
The TPS43331-Q1 has two separate ground termination (AGND and PGND) pins. The ground signal consists of
a plane to minimize impedance. Try to separate the low-signal ground termination from the power-ground signal.
The high-power noisy circuits, such as the output, synchronous rectifier, MOSFET driver decoupling capacitor,
and the input capacitor, should be connected to the PGND plane. The AGND plane should only make a single
point connection to the PGND plane.
The sensitive nodes, such as the feedback resistor divider, oscillator resistor (to set frequency), current sense,
and compensation circuitry, should be connected to the AGND plane.
Try and minimize the high current-carrying loops to a minimum by ensuring optimal component placement.
Ensure the bypass capacitors are located as close as possible to the respective power and ground pins.
Sensitive circuits, such as sense feedback , frequency setting resistor for the oscillator, current sense and
compensation circuits, should not be located near the dv/dt nodes which include the gate drive outputs, phase
pins, and boost circuits (bootstrap).
10.2 Layout Example
Top Side
Power Bus
VBUCK 1
Synchronous
Power FET’s
VLREG
VSTBY
AGND
VSTBYS
PH1
VSTBY
VGT1
VSTBY ≥ 3.3V for I2C
Resistor
divider
VLR Output
Capacitor
uC or Pattern
Generator
VINSB
CBS1
CSLEW
VCMP1
VCP
VFB1
VLRS
ISLO1
VINLR
ISHI1
VLR
PGND
EN
ISHI2
SDA
ISLO2
SCL
VFB2
SYNCH
VCMP2
LVWIN
CBS2
VBATW*
VGT2
VBAT
PH2
HSD
VGB2
PGDLY
VBATP
RST*
Exposed PAD
Connected to
Ground Plane
I2CID
VBUCK 1
VBUCK 1
Output
Capacitor
Resistor
divider
Switched
Power
Output
Inductor
VGB1
Power Input
VBUCK 1
Compensation
Network
Ground
HSD Output
VBUCK 2
Compensation
Network
Si4946
Resistor
divider
VSTBY
Output
Capacitor
TPS43331QDAPRQ1
Si4946
VBUCK 1
sense
resistor
VBUCK 2
Synchronous
Power FET’s
Output
Inductor
VBUCK 2
Output
Capacitor
Resistor
divider
VBUCK 2
VBUCK 2
sense
resistor
Top Side
Power Bus
Connection to backside of PCB through vias
Connection to topside of PCB through vias
Connection to ground plane of PCB through vias
Power bus
Voltage Output rails
Thermal Vias
Figure 41. PCB Layout
44
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10.3 Power Dissipation Derating
The power dissipation curve (see Figure 42) is based on attachment of the exposed power pad to the printed
circuit board with multi layer FR4. The data is based of JEDEC JESD 51-5 standard board with thermal vias and
high-K profile. The user must review PowerPAD Thermally Enhanced Package Application Report for
recommended method of exposed pad attachment.
2.5
Power Dissipation (W)
2
1.5
1
0.5
0
0
20
40
60
80
100
120
140
160
Temperature (°C)
Figure 42. Power Dissipation Derating
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, PowerPAD Thermally Enhanced Package Application Report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
46
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Copyright © 2009–2017, Texas Instruments Incorporated
Product Folder Links: TPS43331-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TPS43331QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43331Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
