TPS51116-EP
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SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
COMPLETE DDR, DDR2, DDR3, AND LPDDR3 MEMORY POWER SOLUTION
SYNCHRONOUS BUCK CONTROLLER, 1-A LDO, BUFFERED REFERENCE
Check for Samples: TPS51116-EP
FEATURES
1
•
2
•
Synchronous Buck Controller (VDDQ)
– Wide-Input Voltage Range: 3.0-V to 28-V
– D−CAP™ Mode with 100-ns Load Step
Response
– Current Mode Option Supports Ceramic
Output Capacitors
– Supports Soft-Off in S4/S5 States
– Current Sensing from RDS(on) or Resistor
– 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
1.5-V (DDR3) or 1.2-V (LPDDR3) or
Output Range 0.75-V to 3.0-V
– Equipped with Powergood, Overvoltage
Protection and Undervoltage Protection
1-A LDO (VTT), Buffered Reference (VREF)
– Capable to Sink and Source 1 A
– LDO Input Available to Optimize Power
Losses
– Requires only 20-μF Ceramic Output
Capacitor
– Buffered Low Noise 10-mA VREF Output
– Accuracy ±20 mV for both VREF and VTT
– Supports High-Z in S3 and Soft-Off in S4/S5
– Thermal Shutdown
APPLICATIONS
•
•
DDR/DDR2/DDR3/LPDDR3 Memory Power
Supplies
SSTL-2, SSTL-18, SSTL-15 and HSTL
Termination
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (–55°C to 125°C)
Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, and
LPDDR3 memory systems. It integrates a synchronous buck controller with a 1-A sink/source tracking linear
regulator and buffered low noise reference. The TPS51116 offers the lowest total solution cost in systems where
space is at a premium. The TPS51116 synchronous controller runs fixed 400-kHz, pseudo-constant frequency
PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest
transient response or in current mode to support ceramic output capacitors. The 1-A sink/source LDO maintains
fast transient response only requiring 20-μF (2 × 10 μF) of ceramic output capacitance. In addition, the LDO
supply input is available externally to significantly reduce the total power losses. The TPS51116 supports all of
the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and
VTTREF (soft-off) in S4/S5 (suspend to disk). TPS51116 has all of the protection features including thermal
shutdown and is offered in a 20-pin HTSSOP PowerPAD™ package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS51116-EP
SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
ORDERABLE
PART NUMBER
TA
PACKAGE
–55°C to 125°C
Plastic HTSSOP PowerPAD (PWP) (2)
(1)
(2)
TPS51116MPWPREP
TPS51116MPWPEP
TOP-SIDE
MARKING
VID NUMBER
V62/12602-01XE
51116M
V62/12602-01XE-T
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
With Cu NIPDAU lead/ball finish
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range unless otherwise noted
VIN
Input voltage range
VOUT
Output voltage range
MIN
MAX
VBST
–0.3
36
VBST wrt LL
–0.3
6
CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET
–0.3
6
PGND, VTTGND
–0.3
0.3
DRVH
–1.0
36
LL
–1.0
30
–5
30
–0.3
6
LL, pulse width < 20 ns
COMP, DRVL, PGOOD, VTT, VTTREF
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
2
150
–65
150
UNIT
V
V
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
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SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
THERMAL INFORMATION
TPS51116-EP
THERMAL METRIC (1)
PWP
UNITS
20 PINS
Junction-to-ambient thermal resistance (2)
θJA
41.2
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
23.9
ψJT
Junction-to-top characterization parameter (5)
1.1
ψJB
Junction-to-board characterization parameter (6)
23.7
θJCbot
Junction-to-case (bottom) thermal resistance (7)
3.6
(1)
(2)
(3)
(4)
(5)
(6)
(7)
27.4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
Supply voltage, V5IN
Voltage range
MIN
MAX
UNIT
V
4.75
5.25
VBST, DRVH
–0.1
34
LL
–0.6
28
VLDOIN, VTT, VTTSNS, VDDQSNS
–0.1
3.6
VTTREF
–0.1
1.8
PGND, VTTGND
–0.1
0.1
S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,
DRVL
–0.1
5.25
–55
125
Operating temperature range, TJ
V
°C
ELECTRICAL CHARACTERISTICS
TJ = −55°C to 125°C, TJ = TA, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IV5IN1
Supply current 1, V5IN
No load, VS3 = VS5 = 5 V,
COMP connected to capacitor
0.8
2
IV5IN2
Supply current 2, V5IN
No load, VS3 = 0 V,
VS5 = 5 V, COMP connected to capacitor
300
610
IV5IN3
Supply current 3, V5IN
No load, VS3 = 0 V,
VS5 = 5 V, VCOMP = 5 V
240
508
IV5INSDN
Shutdown current, V5IN
No load, VS3 = VS5 = 0 V
0.1
1.81
IVLDOIN1
Supply current 1, VLDOIN
No load, VS3 = VS5 = 5 V
1
10
IVLDOIN2
Supply current 2, VLDOIN
No load, VS3 = 5 V, VS5 = 0 V,
0.1
10.5
IVLDOINSDN
Standby current, VLDOIN
No load, VS3 = VS5 = 0 V
0.1
1.5
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μA
3
TPS51116-EP
SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
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ELECTRICAL CHARACTERISTICS (continued)
TJ = −55°C to 125°C, TJ = TA, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VTTREF OUTPUT
VVTTREF
VVTTREFTOL
Output voltage, VTTREF
Output voltage tolerance
VVDDQSNS/2
V
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V,
Tolerance to VVDDQSNS/2
-20
20
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V,
Tolerance to VVDDQSNS/2
-19
19
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.5 V,
Tolerance to VVDDQSNS/2
-16
16
-10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.2 V,
Tolerance to VVDDQSNS/2
–13
13
-19
-40
-83.5
19
40
83.5
2.465
2.500
2.535
VVTTREFSRC
Source current
VVDDQSNS = 2.5 V, VVTTREF = 0 V
VVTTREFSNK
Sink current
VVDDQSNS = 2.5 V, VVTTREF = 2.5 V
mV
mA
VDDQ OUTPUT
TA = 25°C, VVDDQSET = 0 V, No load
-55°C ≤ TA ≤ 125°C, VVDDQSET = 0 V, No load
VVDDQ
Output voltage, VDDQ
VVDDQSET
RVDDQSNS
VDDQSET regulation voltage
Input impedance, VDDQSNS
2.43
2.50
2.56
TA = 25°C, VVDDQSET = 5 V, No load
1.776
1.800
1.830
-55°C ≤ TA ≤ 125°C, VVDDQSET = 5 V, No load
1.762
1.800
1.838
-55°C ≤ TA ≤ 125°C, Adjustable mode, No load
0.75
TA = 25°C, Adjustable mode
-55°C ≤ TA ≤ 125°C, Adjustable mode
3.0
742.5
750
760.5
737
750
763
VVDDQSET = 0 V
215
VVDDQSET = 5 V
180
Adjustable mode
-0.04
VVDDQSET = 0.78 V, COMP = 5 V
-0.06
Input current, VDDQSET
IVDDQDisch
Discharge current, VDDQ
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0 V
IVLDOINDisch
Discharge current, VLDOIN
mV
kΩ
460
VVDDQSET = 0.78 V, COMP = Open
IVDDQSET
V
10
μA
40
mA
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0.5 V
700
mA
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V
1.25
VTT OUTPUT
VVTTSNS
VVTTTOL25
VVTTTOL18
VVTTTOL15
VVTTTOL12
4
Output voltage, VTT
VTT output voltage tolerance
to VTTREF
VTT output voltage tolerance
to VTTREF
VTT output voltage tolerance
to VTTREF
VTT output voltage tolerance
to VTTREF
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V
0.9
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V
0.75
V
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V,
IVTT = 0 A
-21
21
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V,
|IVTT| < 1 A
-31
31
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V,
IVTT = 0 A
-21
21
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V,
|IVTT| < 1 A
-31
31
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V,
IVTT = 0 A
-21
21
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V,
|IVTT| < 1 A
-31
31
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V,
IVTT = 0 A
-21
21
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V,
|IVTT| < 1 A
-31
31
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mV
mV
mV
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SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
TJ = −55°C to 125°C, TJ = TA, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
IVTTTOCLSRC
Source current limit, VTT
TEST CONDITIONS
MIN
TYP
MAX
VVLDOIN = VVDDQSNS = 2.5 V,
VVTT = VVTTSNS = 1.19 V, PGOOD = HI
2.7
3.8
6.2
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V
1.4
2.2
3.2
VVLDOIN = VVDDQSNS = 2.5 V,
VVTT = VVTTSNS = 1.31 V, PGOOD = HI
2.65
3.6
6
2.2
IVTTTOCLSNK
Sink current limit, VTT
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ
1.4
IVTTLK
Leakage current, VTT
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
-11
11
IVTTBIAS
Input bias current, VTTSNS
VS3 = 5 V, VVTTSNS = VVDDQSNS /2
-1.1
1.1
IVTTSNSLK
Leakage current, VTTSNS
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
-1
1
IVTTDisch
Discharge current, VTT
VS3 = VS5 = VVDDQSNS = 0 V, VVTT = 0.5 V
9.5
17
232
300
UNIT
A
3
μA
mA
TRANSCONDUCTANCE AMPLIFIER
gm
Gain
ICOMPSNK
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
COMP maximum sink current
VVDDQSNS = 2.7 V, VCOMP = 1.28 V
364
ICOMPSRC
COMP maximum source
current
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.3 V, VCOMP = 1.28 V
VCOMPHI
COMP high clamp voltage
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.3 V, VCS = 0 V
1.3
1.34
1.38
VCOMPLO
COMP low clamp voltage
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VVDDQSNS = 2.7 V, VCS = 0 V
1.17
1.21
1.25
μS
13
μA
-13
V
DUTY CONTROL
tON
Operating on-time
VIN = 12 V, VVDDQSET = 0 V
520
tON0
Startup on-time
VIN = 12 V, VVDDQSNS = 0 V
125
tON(min)
Minimum on-time
TA = 25°C
100
tOFF(min)
Minimum off-time
TA = 25°C
350
ns
ZERO CURRENT COMPARATOR
VZC
Zero current comparator
offset
-6
0
6
mV
OUTPUT DRIVERS
RDRVH
RDRVL
tD
DRVH resistance
DRVL resistance
Dead time
Source, IDRVH = –100 mA
3
6
0.9
3
3
6
Sink, IDRVL = 100 mA
0.9
3
LL-low to DRVL-on
10
DRVL-off to DRVH-on
20
Sink, IDRVH = 100 mA
Source, IDRVL = –100 mA
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ns
5
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SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012
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ELECTRICAL CHARACTERISTICS (continued)
TJ = −55°C to 125°C, TJ = TA, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.58
0.8
1.1
V
0.1
1.11
μA
INTERNAL BST DIODE
VFBST
Forward voltage
VV5IN-VBST , IF = 10 mA
IVBSTLK
VBST leakage current
VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V
PROTECTIONS
VPGND-CS , PGOOD = HI, VCS < 0.5 V
47
60
70
VPGND-CS , PGOOD = LO, VCS < 0.5 V
18
30
40
VCS > 4.5 V, PGOOD = HI
4
10
20
VCS > 4.5 V, PGOOD = LO
2
5
10
VOCL
Current limit threshold
ITRIP
Current sense sink current
TCITRIP
TRIP current temperature
coefficient
RDS(on) sense scheme, On the basis
of TA = 25°C (1)
VOCL(off)
Overcurrent protection
COMP offset
(VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,
VCS > 4.5 V
VR(trip)
Current limit threshold setting
VV5IN-CS
range
4500
-7
0
mV
μA
ppm/°C
7
mV
30
150
POWERGOOD COMPARATOR
VTVDDQPG
VDDQ powergood threshold
PG in from lower
92%
95%
98%
PG in from higher
102%
105%
108%
PG hysteresis
5%
IPG(max)
PGOOD sink current
VVTT = 0 V, VPGOOD = 0.5 V
2.3
7.5
tPG(del)
PGOOD delay time
Delay for PG in
78
130
mA
205
μs
UNDERVOLTAGE LOCKOUT AND LOGIC THRESHOLD
VUVV5IN
V5IN UVLO threshold
voltage
VTHMODE
MODE threshold
Wake up
Hysteresis
No discharge
3.6
4
4.4
0.19
0.3
0.41
4.7
Non-tracking discharge
0.08
2.5 V output
0.075
0.150
0.255
1.8 V output
3.45
4
4.55
VTHVDDQSET
VDDQSET threshold voltage
VIH
High-level input voltage
S3, S5
VIL
Low-level input voltage
S3, S5
VIHYST
Hysteresis voltage
S3, S5
VINLEAK
Logic input leakage current
S3, S5, MODE
-1
1
VINVDDQSET
Input leakage/ bias current
VDDQSET
-1
1
V
2.2
0.3
0.2
μA
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
VDDQ OVP trip threshold
voltage
tOVPDEL
VDDQ OVP propagation
delay
VUVP
Output UVP trip threshold
tUVPDEL
Output UVP propagation
delay
tUVPEN
Output UVP enable delay
OVP detect
Hysteresis
109%
115%
121%
5%
1.5
UVP detect
70%
Hysteresis
10%
32
μs
cycle
1007
THERMAL SHUTDOWN
TSDN
(1)
6
Thermal SDN threshold
(1)
Shutdown temperature
Hysteresis
160
10
°C
Specified by design. Not production tested.
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100000000.00
10000000.00
Estimated Life (Hrs)
Wirebond Life
1000000.00
100000.00
Operating Life
10000.00
1000.00
95
105
115
125
135
145
155
Operating Junction Temperature ( °C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Sillicon operating life design goal is 10 years at 110°C junction temperature.
Figure 1. Operating and Wirebond Life Derating Chart
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DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
DESCRIPTION
PWP
COMP
8
I/O
Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable gm
amplifier and use D-CAP™ mode.
CS
15
I/O
Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip voltage
setting input for RDS(on) current sense scheme if connected to V5IN through the voltage setting
resistor.
DRVH
19
O
Switching (top) MOSFET gate drive output.
DRVL
17
O
Rectifying (bottom) MOSFET gate drive output.
GND
5
-
Signal ground. Connect to minus terminal of the VTT LDO output capacitor.
LL
18
I/O
MODE
6
I
Discharge mode setting pin. See VDDQ and VTT Discharge Control section.
PGND
16
–
Ground for rectifying (bottom) MOSFET gate driver. Also current sense comparator input(+) and
ground for powergood circuit.
PGOOD
13
O
Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the target
range.
S3
11
I
S3 signal input.
S5
12
I
S5 signal input.
V5IN
14
I
5-V power supply input for internal circuits and MOSFET gate drivers.
VBST
20
I/O
VDDQSET
10
I
VDDQSNS
9
I/O
VLDOIN
1
I
Power supply for the VTT LDO.
VTT
2
O
Power output for the VTT LDO.
VTTGND
3
–
Power ground output for the VTT LDO.
VTTREF
7
O
VTTREF buffered reference output.
VTTSNS
4
I
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.
Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on) current
sense.
Switching (top) MOSFET driver bootstrap voltage input.
VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current
sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for VDDQ output
if VDDQSET pin is connected to V5IN or GND.
PWP PACKAGE
(TOP VIEW)
VLDOIN
VTT
VTTGND
VTTSNS
GND
MODE
VTTREF
COMP
VDDQSNS
VDDQSET
8
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
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VBST
DRVH
LL
DRVL
PGND
CS
V5IN
PGOOD
S5
S3
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FUNCTIONAL BLOCK DIAGRAM
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DETAILED DESCRIPTION
The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a
10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin
HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that
required with DDR/DDR2/DDR3/LPDDR3 memory systems. The switch mode power supply (SMPS) portion
employs external N-channel MOSFETs to support high current for DDR/DDR2/DDR3/LPDDR3 memory
VDD/VDDQ. The preset output voltage is selectable from 2.5 V or 1.8 V. User-defined output voltage is also
possible and can be adjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS
runs an adaptive on-time PWM operation at high-load condition and automatically reduces frequency to keep
excellent efficiency down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying
MOSFET for a low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying
MOSFET for more accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate
one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT
LDO can source and sink up to 1-A peak current with only 20-μF (two 10-μF in parallel) ceramic output
capacitors. VTTREF tracks VDDQ/2 within ±1% of VDDQ. VTT output tracks VTTREF within ±20 mV at no load
condition while ±40 mV at full load. The LDO input can be separated from VDDQ and optionally connected to a
lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing phase. TheTPS51116 is
fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2). The part has two
options of output discharge function when both VTT and VDDQ are disabled. The tracking discharge mode
discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output tracks half of
VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using internal discharge
MOSFETs which are connected to VDDQSNS and VTT. The current capability of these discharge FETs are
limited and discharge occurs more slowly than the tracking discharge. These discharge functions can be disabled
by selecting non-discharge mode.
VDDQ SMPS, Dual PWM Operation Modes
The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.
It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode
uses internal compensation circuit and is suitable for low external component count configuration with an
appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external
compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as
ceramic or specialty polymer capacitors.
These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,
TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is
monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the
output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to
VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This
MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined
by VIN and VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time
control (see PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when
feedback information indicates insufficient output voltage and inductor current information indicates below the
overcurrent limit. Repeating operation in this manner, the controller regulates the output voltage. The
synchronous bottom or the rectifying MOSFET is turned on each OFF state to keep the conduction loss
minimum. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables
seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over
broad range of load current.
In the current mode control scheme, the transconductance amplifier generates a target current level
corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During
the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and
when the inductor current signal comes lower than the target current level, the comparator provides SET signal
to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support
various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is
disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference
during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides
SET signal to initiate the next ON state.
10
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VDDQ SMPS, Light Load Condition
TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This
reduction of frequency is achieved smoothly and without increase of VOUTripple or load regulation. Detail
operation is described as follows. As the output current decreases from heavy load condition, the inductor current
is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary
between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when
this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous
conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next
ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current
increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor
current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the
threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1:
(V IN * V OUT) V OUT
1
I OUT(LL) +
2 L f
V IN
where
•
f is the PWM switching frequency (400 kHz)
(1)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at
IOUT(LL)/10 and 4 kHz at IOUT(LL)/100.
Low-Side Driver
The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is
represented by the internal resistance, which is 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A deadtime to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well
as the high-side gate drive current times 5 V makes the driving power which needs to be dissipated from
TPS51116 package.
High-Side Driver
The high-side driver is designed to drive high-current, low on-resistance, N-channel MOSFET(s). When
configured as a floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also
calculated by the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied
by the flying capacitor between VBST and LL pins. The drive capability is represented by the internal resistance,
which is 3 Ω for VBST to DRVH and 0.9 Ω for DRVH to LL.
Current Sensing Scheme
In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor
sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor
should be connected between the source terminal of the low-side MOSFET and PGND. CS pin is connected to
the MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS
pin. For RDS(on) sensing scheme, CS pin should be connected to V5IN through the trip voltage setting resistor,
RTRIP. In this scheme, CS terminal sinks 10-μA ITRIP current and the trip level is set to the voltage across the
RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that LL pin should be
connected to the drain terminal of the low-side MOSFET. ITRIP has 4500ppm/°C temperature slope to
compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive current
sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense resistor or
the source terminal of the low-side MOSFET.
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PWM Frequency and Adaptive On-Time Control
TPS51116 includes an adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output
voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and
proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time.
Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during
the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In
order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output
becomes 750 mV or larger.
VDDQ Output Voltage Selection
TPS51116 can be used for both of DDR (VVDDQ = 2.5 V) and DDR2 (VVDDQ = 1.8 V) power supply and adjustable
output voltage (0.75 V < VVDDQ < 3 V) by connecting VDDQSET pin as shown in Table 1. Use the adjustable
output voltage scheme for a DDR3 (VVDDQ= 1.5 V) or LPDDR3 (VVDDQ= 1.2 V) application.
Table 1. VDDQSET and Output Voltages
VDDQSET
VDDQ (V)
VTTREF and VTT
GND
2.5
VVDDQSNS/2
NOTE
DDR
V5IN
1.8
VVDDQSNS/2
DDR2
FB Resistors
Adjustable
VVDDQSNS/2
0.75 V < VVDDQ < 3 V (1)
(2)
VTT Linear Regulator and VTTREF
TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking
current up to 1 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic
capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient.
To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should
be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable
operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. It is recommended
to attach two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output
capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop
stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by
the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator
also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-μF ceramic capacitor for
stable operation.
When VTT is not required in the design, following treatment is strongly recommended.
• Connect VLDOIN to VDDQSNS.
• Tie VTTSNS to VTT, and remove capacitors from VTT to float.
• Connect VTTGND and MODE to GND (Non-tracking discharge mode as shown in Table 3)
• Maintain a 0.033-µF capacitor connected at VTTREF.
• Pull down S3 to GND with 1 kΩ of resistance.
A typical circuit for this application is shown in Figure 2
(1)
(2)
12
VVDDQ≥ 1.2 V when used as VLDOIN.
Including DDR3 and LPDDR3
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VIN
TPS51116 PWP
1
VLDOIN
VBST 20
2
VTT
DRVH 19
3
VTTGND
LL 18
4
VTTSNS
DRVL 17
5
GND
PGND 16
6
MODE
7
VTTREF
8
COMP
9
VDDQSNS
VDDQ
0.033 ?F
CS 15
V5IN 14
5VIN
PGOOD 13
S5 12
1 kW
10 VDDQSET
S3 11
PGOOD
S5
UDG-12044
Figure 2. Application Circuit When VTT Is Not Required
Controling Outputs Using the S3 and S5 Pins
In the DDR/DDR2/DDR3/LPDDR3 memory applications, it is important to keep VDDQ always higher than
VTT/VTTREF including both start-up and shutdown. TPS51116 provides this management by simply connecting
both the S3 and S5 pins to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All
of VDDQ, VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ
and VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT
output is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three
outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin
(see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 =
suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2)
Table 2. Sleep Mode Control Using the S3 and S5 Pins
STATE
S3
S5
VDDQ
VTTREF
S0
HI
HI
ON
ON
VTT
ON
S3
LO
HI
ON
ON
OFF (High-Z)
S4/S5
LO
LO
OFF (Discharge)
Off (Discharge)
OFF (Discharge)
Soft-Start and Powergood
The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At
the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold
is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,
the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 μs. The
overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another
45 μs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the
target voltage), then turns off powergood open-drain MOSFET.
The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed
in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood
threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low
and constant current that gives linear ramp up of the output. When the output comes up to the good state, the
overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each
output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood
externally. See Figure 3.
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100%
87%
80%
VVDDQ
VOCL
VPGOOD
VS5
85 µs
45 µs
UDG−04066
Figure 3. VDDQ Soft-Start and Powergood Timing
Soft-start duration, tVDDQSS, tVTTSS are functions of output capacitances.
2 ´ CVDDQ ´ VVDDQ ´ 0.8
+ 85 ms
t VDDQSS =
IVDDQOCP
where
•
IVDDQOCP is the current limit value for VDDQ switcher calculated by Equation 5
t VTTSS =
(2)
CVTT ´ VVTT
IVTTOCL
where
•
IVTTOCL = 2.2 A (typ)
(3)
In both Equation 2 and Equation 3 , no load current during start-up are assumed. Note that both switchers and
the LDO do not start up with full load condition.
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VDDQ and VTT Discharge Control
TPS51116 discharges VDDQ, VTTREF and VTT outputs when S3 and S5 are both low. There are two different
discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.
Table 3. Discharge Selection
MODE
DISCHARGE MODE
V5IN
No discharge
VDDQ
Tracking discharge
GND
Non-tracking discharge
When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors
and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via
VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can
handle up to 1 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off
and the operation mode is changed to the non-tracking-discharge mode.
When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are
connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.
Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In no discharge mode,
TPS51116 does not discharge any output charge.
Current Protection for VDDQ
The SMPS has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. The
trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme
section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV.
For RDS(on) sensing scheme, CS terminal sinks 10 μA and the trip level is set to the voltage across this RTRIP
resistor.
V TRIP (mV) + RTRIP (kW) 10 (mA)
(4)
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load
current at overcurrent threshold, IOCP, can be calculated as shown in Equation 5.
I OCP +
V TRIP
I
V
) RIPPLE + TRIP )
2
RDS(on)
R DS(on) 2
1
L
ǒV IN * V OUTǓ
f
V OUT
V IN
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes less than Powergood level, the VTRIP is cut into half and
the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and
shutdown.
Current Protection for VTT
The LDO has an internally fixed constant overcurrent limiting of 3.8 A while operating at normal condition. This
trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of
±10% of the target voltage.
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Overvoltage and Undervoltage Protection for VDDQ
TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is
connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If
an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.
When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes
high and the circuit latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the
high-side MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP
comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116
latches OFF both top and low-side MOSFETs. This function is enabled after 1007 cycles of SMPS operation to
ensure startup.
V5IN Undervoltage Lockout (UVLO) Protection
TPS51116 has 5-V supply undervoltage lockout protection (UVLO). When the V5IN voltage is lower than UVLO
threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection.
V5IN Input Capacitor
Add a ceramic capacitor with a value between 1.0 μF and 4.7 μF placed close to the V5IN pin to stabilize 5 V
from any parasitic impedance from the supply.
Thermal Shutdown
TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160°C (typ),
SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the
device is cooled down by about 10°C.
16
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APPLICATION INFORMATION
Loop Compensation and External Parts Selection
Current Mode Operation
A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltage
divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the
transfer function of the whole system. Because current mode scheme directly controls the inductor current, the
modulator can be linearized as shown in Figure 4.
Figure 4. Linearizing the Modulator
Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal
model. As a result, a modulated current source including the power inductor can be modeled as a current source
with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model
is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although
the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew
rate of the current source. This means the buck converter’s load transient response, one of the large signal
behaviors, can be improved by using smaller inductance without affecting the loop stability.
Total open loop transfer function of the whole system is given by Equation 6.
H(s) + H 1(s) H 2(s) H 3(s)
(6)
Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of the three blocks is shown starting with
Equation 7.
R2
H 1(s) +
(R2 ) R1)
(7)
H 2(s) + * gm
H 3(s) +
R O ǒ1 ) s
ǒ1 ) s
(1 ) s
ǒ1 ) s
CO
CO
CC
ESR)
RLǓ
CC
R OǓ ǒ1 ) s
RCǓ
C C2
R CǓ
(8)
RL
RS
(9)
There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.
1
w P1 +
ǒCC ROǓ
w P2 +
(10)
1
ǒCO
RLǓ
(11)
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w P3 +
w Z1 +
w Z2 +
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1
ǒCC2
RCǓ
(12)
1
ǒCC
RCǓ
(13)
ESRǓ
(14)
1
ǒCO
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be
kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by Equation 15.
gm RC
gm R C
0.75
R1
f0 + 1
+ 1
2p R1 ) R2 C O RS
2p VOUT C O R S
(15)
Based on small signal analysis above, the external components can be selected by following manner.
1. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 1/4 to 1/2 of maximum output current.
L+
ǒVIN(max) * VOUTǓ
1
I IND(ripple)
f
VOUT
VIN(max)
+
ǒV IN(max) * V OUTǓ
2
I OUT(max)
f
V IN(max)
V OUT
(16)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as shown in Equation 17.
I IND(peak) +
V TRIP
) 1
RDS(on) L f
ǒVIN(max) * VOUTǓ
V OUT
VIN(max)
(17)
2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s
on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order
to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with
the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of
the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency
more at high-load conditions. When using external resistor current sensing, there is no restriction for low
RDS(on). However, the current sensing resistance RS itself affects the efficiency
3. Choose output capacitor(s). When organic semiconductor capacitors (OS-CON) or specialty polymer
capacitors (SP-CAP) are used, ESR to achieve required ripple value at stable state or transient load
conditions determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable
operation. The peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable
state, or ESR times the load current step for a fast transient load response. When ceramic capacitor(s) are
used, the ESR is usually small enough to meet ripple requirement. In contrast, transient undershoot and
overshoot driven by output capacitance becomes the key factor in determining the capacitor(s) required.
4. Determine f0 and calculate RC using Equation 18. Note that higher RC shows faster transient response in
cost of unstableness. If the transient response is not enough even with high RC value, try increasing the out
put capacitance. Recommended f0 is fOSC/4. Then RC can be derived by Equation 19.
V OUT CO
R C v 2p f 0
gm RS
0.75
(18)
R C + 2.8 V OUT C O [mF] R S [mW]
(19)
5. Calculate CC2 . Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. When
ceramic capacitor(s) are used, no need for CC2.
1
1
w z2 +
+ wp3 +
ǒCO ESRǓ
ǒC C2 RCǓ
(20)
C ´ ESR
CC2 = O
RC
18
(21)
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6. Calculate CC. The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it
causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined
by Cc and Rc. Recommended ωz1 is 10 times lower to the f0 frequency.
f
1
f z1 +
+ 0
10
2p C C R C
(22)
7. When using adjustable mode, determine the value of R1 and R2. .
V
* 0.75
R1 + OUT
R2
0.75
(23)
D-CAP™ Mode Operation
A buck converter system using D-CAP™ Mode can be simplified as below.
Figure 5. Linearizing the Modulator
The PWM comparator compares the VDDQSNS voltage divided by R1 and R2 with internal reference voltage,
and determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is high
enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The
DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase.
For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.
f
1
f0 +
v SW
3
2p ESR CO
(24)
As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined
by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have CO in the order of
several 100 μF and ESR in range of 10 mΩ. These makes f0 in the order of 100 kHz or less and the loop is then
stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational
mode.
Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient
amount of feedback signal needs to be provided by external circuit to reduce jitter level.
The required signal level is approximately 15 mV at comparing point. This gives VRIPPLE = (VOUT/0.75) x 15 (mV)
at the output node. The output capacitor’s ESR should meet this requirement.
The external components selection is much simple in D-CAP™ mode.
1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the
Current Mode Operation section.
2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are
recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in
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Equation 25.
V
0.015
ESR + OUT
[ VOUT
I RIPPLE 0.75
I OUT(max)
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60 [mW]
(25)
Thermal Design
Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and
sink directions generate power dissipation from the part. In the source phase, potential difference between
VLDOIN and VTT times VTT current becomes the power dissipation, WDSRC.
W DSRC + ǒVVLDOIN * VVTTǓ
I VTT
(26)
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be
decreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, WDSNK,
is calculated by Equation 27:
W DSNK + VVTT I VTT
(27)
Because this device does not sink AND source the current at the same time and IVTT varies rapidly with time,
actual power dissipation need to be considered for thermal design is an average of above value. Another power
consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN
supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN
supply can be estimated as 1.5 mA or less at normal operational conditions.
These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the
package is calculated by Equation 28,
T J(max) * T A(max)
W PKG +
q JA
(28)
where
• TJ(max) is 150°C
• TA(max) is the maximum ambient temperature in the system
• θJA is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced
PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this
die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat
sink/spread. The typical thermal resistance, 41.2°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land
with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.
Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This
document is available at http:\\www.ti.com.
20
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Layout Considerations
Certain points must be considered before designing a layout using the TPS51116.
• PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET
and high-voltage side of the inductor, should be as short and wide as possible.
• Consider adding a small snubber circuit, consisting of a 3-Ω resitor and a 1-nF capacitor, between LL and
PGND in case a high-frequency surge is observed on the LL voltage waveform.
• All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage
switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.
• VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for
VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide
connection.
• The output capacitor for VTT should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to
sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitor(s).
• Consider adding LPF at VTTSNS when the ESR of the VTT output capacitor(s) is larger than 2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of VTTREF. Avoid any noise generative lines.
• Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding
common impedance to the high current path of the VTT source/sink current.
• GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND
to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid
additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.
• PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25mil) or wider trace. Connect to
source of rectifying MOSFET with shortest possible path.
• The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH,
DRVL or PGOOD.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.
Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground
plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the
package.
Figure 6. D-CAP™ Mode
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Table 4. D-CAP™ Mode Schematic Components
SYMBOL
SPECIFICATION
MANUFACTURER
R1
5.1 kΩ
-
PART NUMBER
R2
100 kΩ
-
R3
75 kΩ
-
R4
(100 × VVDDQ – 75) kΩ
-
R5
5.1 Ω
M1
30 V, 13 mΩ
International Rectifier
IRF7821
M2
30 V, 5 mΩ
International Rectifier
IRF7832
Figure 7. Current Mode
Table 5. Current Mode Schematic Components
22
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
R1
6 mΩ, 1%
Vishay
WSL-2521 0.006
R2
100 kΩ
-
-
R5
5.1 Ω
M0
30 V, 13 mΩ
International Rectifier
IRF7821
M1
30 V, 5 mΩ
International Rectifier
IRF7832
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TYPICAL CHARACTERISTICS
All data in the following graphs are measured from the PWP packaged device.
V5IN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
2.0
1.0
1.8
0.9
IV5IN1 − V5IN Shutdown Current − µA
IV5IN1 − V5IN Supply Current − mA
V5IN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.2
0
−50
0
50
100
0
−50
150
50
100
Figure 8.
Figure 9.
V5IN SUPPLY CURRENT
vs
LOAD CURRENT
VLDOIN SUPPLY CURRENT
vs
TEMPERATURE
10
150
1.0
DDR2
VVTT = 0.9 V
0.9
IVLDOIN − VLDOIN Supply Current − µA
9
IV5IN − V5IN Supply Current − mA
0
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
8
7
6
5
4
3
2
1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−2
−1
0
1
IVTT − VTT Current − A
2
0
−50
Figure 10.
0
50
100
150
TJ − Junction Temperature − °C
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
CS CURRENT
vs
JUNCTION TEMPERATURE
VDDQ DISCHARGE CURRENT
vs
JUNCTION TEMPERATURE
16
14
PGOOD = HI
ITRIP − CS Current − µA
12
10
8
6
PGOOD = LO
4
IDISCH − VDDQ Discharge Current − mA
80
2
0
−50
0
50
100
70
60
50
40
30
20
10
−50
150
0
50
100
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 12.
Figure 13.
VTT DISCHARGE CURRENT
vs
JUNCTION TEMPERATURE
OVERVOLTAGE AND UNDERVOLTAGE THRESHOLD
vs
JUNCTION TEMPERATURE
140
VTRIP − OVP/UVP Trip Threshold − %
IDISCH − VTT Discharge Current − mA
30
25
20
15
10
−50
0
50
100
TJ − Junction Temperature − °C
150
120
VOVP
100
80
VUVP
60
−50
Figure 14.
24
150
0
50
100
TJ − Junction Temperature − °C
150
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
430
450
D-CAP Mode
IVDDQ = 7 A
DDR2
400
fSW − Switching Frequency − kHz
fSW − Switching Frequency − kHz
420
410
400
DDR2
390
DDR
380
350
DDR
300
250
200
150
100
50
370
D−CAP Mode
VIN = 12 V
0
4
12
8
16
20
24
28
0
2
4
6
8
IVDDQ − VDDQ Output Current − A
Figure 16.
Figure 17.
VDDQ OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR)
VDDQ OUTPUT VOLTAGE
vs
INPUT VOLTAGE (DDR2)
1.820
1.820
1.815
1.815
VVDDQ − VDDQ Output Voltage − V
VVDDQ − VDDQ Output Voltage − V
VIN − Input Voltage − V
1.810
1.805
1.800
1.795
1.790
1.785
D−CAP Mode
1.810
IVDDQ = 0 A
1.805
1.800
1.795
IVDDQ = 10 A
1.790
1.785
D−CAP Mode
VIN = 12 V
1.780
10
1.780
0
4
6
8
IVDDQ − VDDQ Output Current − A
2
10
4
Figure 18.
8
12
16
20
24
30
VIN − Input Voltage − V
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
VTT OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR)
VTT OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR2)
0.94
1.30
0.93
1.28
VVTT − VTT Output Voltage − V
VVTT − VTT Output Voltage − V
1.29
1.27
1.26
VVLDOIN = 2.5 V
1.25
1.24
1.23
0.92
0.91
VVLDOIN = 1.8 V
0.90
0.89
VVLDOIN = 1.5 V
0.88
1.22
0.86
1.20
−5
−4
−3 −2 −1
0
1
2
3
IVTT − VTT Output Current − A
4
Figure 21.
VTTREF OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR)
VTTREF OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR2)
0.904
1.251
2
3
DDR2
VVTTREF − VTTREF Voltage − V
0.903
1.250
1.249
1.248
1.247
1.246
1.245
0.902
0.901
0.900
0.899
0.898
0.897
0
5
IVTTREF − VTTREF Current − mA
−5
10
0.896
−10
Figure 22.
26
−1
0
1
IVTT − VTT Output Current − A
Figure 20.
DDR
1.244
−10
−2
−3
5
1.252
VVTTREF − VTTREF Voltage − V
VVLDOIN = 1.2 V
0.87
VVLDOIN = 1.8 V
1.21
−5
0
5
IVTTREF − VTTREF Current − mA
10
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
VTTREF OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR3)
VTT OUTPUT VOLTAGE
vs
OUTPUT CURRENT (DDR3)
0.765
0.79
DDR3
VVLDOIN = 1.5 V
0.78
IVTT - VTT Output Voltage - V
IVTT - VTT Output Voltage - V
0.76
0.755
0.75
0.745
0.77
0.76
0.75
0.74
0.73
0.74
0.72
0.735
-10
0
5
IVTTREF - VTTREF Current - mA
-5
0.71
10
-3
1
0
2
3
IVTT - VTT Output Current - A
Figure 24.
Figure 25.
VDDQ EFFICIENCY (DDR)
vs
VDDQ CURRENT
VDDQ EFFICIENCY (DDR2)
vs
VDDQ CURRENT
100
100
VVDDQ = 2.5 V
VIN = 8 V
VVDDQ = 1.8 V
Efficiency − %
VIN = 12 V
80
VIN = 20 V
70
80
VIN = 12 V
VIN = 20 V
70
60
60
50
0.001
VIN = 8 V
90
90
Efficiency − %
-1
-2
0.1
1
0.01
IVDDQ − VDDQ Current − A
10
50
0.001
Figure 26.
0.01
0.1
IVDDQ − VDDQ Current − A
1
10
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
VVDDQ (50 mV/div)
VVDDQ (50 mV/div)
IVDDQ (2 A/div)
IIND (5 A/div)
VVTTREF (10 mV/div)
VVTT (10 mV/div)
IVDDQ (5 A/div)
t − Time − 2 µs/div
t − Time − 20 µs/div
Figure 28. Ripple Waveforms - Heavy Load Condition
Figure 29. VDDQ Load Transient Response
VVDDQ (50 mV/div)
VVTT (20 mV/div)
S5
VDDQ
VVTTREF
(20 mV/div)
VTTREF
IVTT
(2 A/div)
PGOOD
IVDDQ = IVTTREF = 0 A
t − Time − 100 µs/div
t − Time − 20 µs/div
Figure 30. VTT Load Transient Response
28
Figure 31. VDDQ, VTT, and VTTREF Start-Up Waveforms
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TYPICAL CHARACTERISTICS (continued)
VDDQ
VDDQ
VTTREF
VTTREF
VTT
VTT
S5
S5
IVDDQ = IVTT = IVTTREF = 0 A
IVDDQ = IVTT = IVTTREF = 0 A
t − Time − 200 µs/div
t − Time − 1 ms/div
Figure 32. Soft-Start Waveforms Tracking Discharge
Figure 33. Soft-Stop Waveforms Non-Tracking Discharge
VDDQ BODE PLOT (CURRENT MODE)
GAIN AND PHASE
vs
FREQUENCY
VTT BODE PLOT, SOURCE (DDR2)
GAIN AND PHASE
vs
FREQUENCY
180
80
135
60
40
90
40
90
20
45
20
45
0
0
0
0
80
60
180
Phase
135
−45
−20
Gain
−20
Phase − 5
Gain − dB
Phase − 5
Gain − dB
Phase
−45
Gain
−40
−90
−60
−135
IVDDQ = 7 A
−80
100
−180
1k
10 k
100 k
1M
−40
−90
−60
−135
−80
10 k
IVTT = −1 A
100 k
1M
−180
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
VTT BODE PLOT, SINK (DDR2)
GAIN AND PHASE
vs
FREQUENCY
80
180
60
135
Phase
Gain − dB
20
90
45
0
Gain
0
−20
−45
−40
−90
Phase − °
40
−135
−60
IVTT = 1 A
−80
10 k
100 k
1M
−180
10 M
f − Frequency − Hz
Figure 36.
30
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51116MPWPEP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
51116M
TPS51116MPWPREP
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
51116M
V62/12602-01XE
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
51116M
V62/12602-01XE-T
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
51116M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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