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TPS51120
SLUS670C – JULY 2005 – REVISED JANUARY 2015
TPS51120 Dual, Synchronous Step-Down Controller With 100-mA Standby Regulators for
Notebook System Power
1 Features
3 Description
•
The TPS51120 is a highly sophisticated dual,
synchronous step-down controller. It is a full featured
controller designed to run directly off a three- or fourcell Li-ion battery and provide high-power and 5-V
and/or 3.3-V standby regulation for all the
downstream circuitry in a notebook computer system.
High-current, 100-mA, 5-V or 3.3-V on-board linear
regulators have glitch-free switch over function to
SMPS and can be kept alive independently during
standby state. The pseudo-constant frequency
adaptive on-time control scheme supports full range
of current mode operation including simplified loop
compensation, ceramic output capacitors as well as
seamless transition to reduced frequency operation at
light-load condition. Optional D-CAP mode operation
optimized for SP-CAP or POSCAP output capacitors
allows further reduction of external compensation
parts. Dynamic UVP supports VIN line sag without
latch off by hitting 5-V UVP. No negative voltage
appears at output voltage node during UVLO, UVP,
and OCP, OTP or loss of VIN.
1
•
•
•
•
•
•
•
•
•
•
•
•
3.3-V and 5-V 100-mA Bootstrapped Standby
Regulators with Independent Enables
Selectable D-CAP™ Mode Enables Fast
Transient Response Less than 100 ns
Selectable Low Ripple Current Mode
Less than 1% Internal Reference Accuracy
Selectable PWM-only/Auto-skip Modes
Low-side RDS(on) Loss-less Current Sensing
RSENSE Accurate Current Sense Option
Internal Soft-Start and Integrated VOUT Discharge
Transistors
Integrated 2-V Reference
Adaptive Gate Drivers with Integrated Boost Diode
Powergood for Each Channel with Delay Timer
Fault Disable Mode
Supply Input Voltage Range: 4.5 V to 28 V
2 Applications
The TPS51120 32-pin QFN package is specified from
–40°C to 85°C ambient temperature.
Notebook Computers System Bus and I/O
Device Information(1)
PART NUMBER
TPS51120
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Reference Design for D-CAP Mode Converter
V5FILT
VBAT
EN_2
L2
2.2 µH
2
1
COMP1
VO1
R11
100 kΩ
SKIPSEL
32
11 PGOOD2
PGOOD1 30
TPS51120RHB
(QFN−32)
P_GOOD1
GND
VBAT
EN1 29
EN_1
13 VBST2
VBST1 28
C11
0.1 µF
14 DRVH2
DRVH1 27
C10
20 µF
Q1
IRF7821
L1
4.7 µH
+
+
PowerPAD
CS1
PGND1
17
VIN
DRVL2
VREG5
16
V5FILT
Q4
IRF7832
LL1 26
VREG3
C2A
150 µF
15 LL2
CS2
C2B
150 µF
VO2_GND
3
TONSEL 31
12 EN2
C21
0.1 µF
4
10 EN3
PGND2
VO2
3.3V/6A
Q3
IRF7821
5
VFB1
EN5
EN_LDO3
C10
20 µF
6
GND
9
7
VFB2
EN_LDO5
P_GOOD2
8
COMP2
GND
VO2
R21
100 kΩ
VREF2
C31
1 nF
18
19
20
21
22
23
24
Q2
IRF7832
DRVL1
C1A
150 µF
VO1
5V/6A
C1B
150 µF
25
−
VO1_GND
−
PGND2
PGND1
R22
3.3 kΩ
R50
5.1Ω
C30
10 µF
C51
1 µF
R12
3.6 kΩ
C50
10 µF
VBAT
C30
NA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51120
SLUS670C – JULY 2005 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics.......................................... 6
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 22
7.5 Programming........................................................... 27
8
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application ................................................. 28
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1 Trademarks ........................................................... 33
11.2 Electrostatic Discharge Caution ............................ 33
11.3 Glossary ................................................................ 33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (Feburary 2007) to Revision C
•
2
Page
Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
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SLUS670C – JULY 2005 – REVISED JANUARY 2015
5 Pin Configuration and Functions
4
GND
VFB2
3
5
VO2
TONSEL
2
COMP2
1
32
VFB1
VREF2
SKIPSEL
COMP1
VO1
RHB Package
32-Pin VQFN
Bottom View
7
8
6
9
EN5
31
10
EN3
PGOOD1
30
11
PGOOD2
EN1
29
12
EN2
VBST1
28
13
VBST2
DRVH1
27
14
DRVH2
LL1
26
15
LL2
DRVL2
PGND2
CS2
VREG3
V5FILT
VREG5
VIN
CS1
PGND1
DRVL1
16
25
24 23 22 21 20 19 18 17
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
COMP1
2
O
COMP2
7
O
CS1
23
I
CS2
18
I
DRVH1
27
O
DRVH2
14
O
DRVL1
25
O
DRVL2
16
O
EN1
29
I
EN2
12
I
EN3
10
I
VREG3, 3.3-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to enabled
VREG5 to turn on the regulator.
EN5
9
I
VREG5, 5-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to VBAT to
turn on the regulator.
GND
5
I
Signal ground pin.
LL1
26
I/O
LL2
15
I/O
PGND1
24
I/O
PGND2
17
I/O
PGOOD1
30
O
PGOOD2
11
O
Power-good window comparator open drain output. Pull up with resistor to V5FILT or appropriate signal
voltage. Current capability is 5-mA. PGOOD goes high 1-ms after VFB is within specified limits. Power
bad (terminal goes low) is within 10 μs.
SKIPSEL
32
I
Skip and fault mode selection pin. Refer to Table 5
TONSEL
31
I
On-time selection pin. Refer to Table 1 and Table 5.
V5FILT
20
I
5-V supply input for the entire control circuit. Should be provided from VREG5 via RC filter.
Loop compensation pin (error amplifier output). Connect RC from this pin to GND for proper loop
compensation with current mode operation. Tie this pin to V5FILT for D-CAP mode operation.
Current sense comparator input (-) for resistor sensing scheme. Or, overcurrent trip setting input for
RDS(on) current sense scheme if connected to V5FILT through the threshold setting resistor.
High-side MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, LL-node referenced floating driver. Drive
voltage corresponds to VBST to LL voltage.
Rectifying (low-side) MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, PGND referenced driver. Drive
voltage is VREG5 voltage.
Channel 1 and Channel 2 SMPS enable pins. Connect to 5 V to turn on with internal 3-ms soft-start.
Slower soft-start is possible by applying an external capacitor from each of these pins to ground to
program ramp rate.
High-side MOSFET gate driver return. Also serve as current sense comparator input (-) for RDS(on)
sensing, and input voltage monitor for on-time control circuitry
Ground return for rectifying MOSFET gate driver. Connect PGND2, PGND1 and GND strongly together
near the source of the rectifying FET or the GND connection of the current sense resistor. Also serve as
current sense comparator input (+).
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SLUS670C – JULY 2005 – REVISED JANUARY 2015
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
VBST1
28
I
VBST2
13
I
VFB1
3
I
VFB2
6
I
SMPS feedback input. Connect the feedback resistor divider here for adjustable outputs. Tie these pins to
V5FILT or for fixed output option. Refer to Table 5
VIN
22
I
Supply Input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
VO1
1
I
VO2
8
I
These terminals serve four functions: on-time adjustment, output discharge, VREG5, VREG3 switchover
input and feedback inputs for 5-V, 3.3-V fixed-output option. Connect to positive terminal of respective
switch mode power supply’s output capacitor.
VREF2
4
O
2-V reference output. Capable of ±50-μA, ±2% over 0 - 85°C temperature range. Bypass to GND by 1-nF
ceramic capacitor. Tie this pin to GND disables both SMPS.
VREG3
19
O
3.3-V, 100-mA low dropout linear regulator output. Bypass to PGND by 10-μF ceramic capacitor. Runs
from VIN supply. Shuts off with EN3. Switches over to VO2 when 3.1 V or above is provided.
VREG5
21
O
5-V, 100-mA low dropout linear regulator output. Bypass to PGND by 10-μF ceramic capacitor. Runs from
VIN supply. Internally connected to VBST and DRVL. Shuts off with EN5. Switches over to VO1 when 4.8
V or above is provided.
4
Supply Input for High-side MOSFET Driver. Connect capacitor from this pin to respective LL terminal. An
internal PN diode is connected between VREG5 to each of these pins. User can add external schottky
diode if forward drop is critical to drive the power MOSFET.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
Input voltage
MIN
MAX
VBST1, VBST2
–0.3
36
VBST1, VBST2 wrt LL
–0.3
6
VIN, EN5
–0.3
30
SKIPSEL, TONSEL, EN1, EN2, CS1, CS2,
V5FILT, VFB1, VFB2, EN3, VO1, VO2
–0.3
6
DRVH1, DRVH2
DRVH1, DRVH2 (wrt LL)
LL1, LL2
Output voltage
–1
36
–0.3
6
–1
30
VREF2, VREG3, VREG5, PGOOD1, PGOOD2,
DRVL1, DRVL2, COMP1, COMP2
–0.3
6
PGND1, PGND2
–0.3
0.3
VREF2
Source/sink current
V
V
1
VBST
100
VREG5, VREG3 (source only)
200
TA
Operating ambient temperature
–40
85
TJ
Junction temperature
–40
125
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
Tstg Storage temperature
(1)
UNIT
mA
°C
255
–55
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
6.2 Recommended Operating Conditions
Input voltage, V5FILT
Input voltage range
Output voltage range
MIN
MAX
4.5
5.5
VBST1, VBST2
-0.1
34
VBST1, VBST2 wrt LL
-0.1
5.5
VIN, EN5
-0.1
28
SKIPSEL, TONSEL, EN1, EN2, CS1, CS2, V5FILT, VFB1, VFB2, EN3
-0.1
5.5
VO1, VO2
-0.1
5.5
DRVH1, DRVH2
-0.8
34
DRVH1, DRVH2 (wrt LL)
-0.1
5.5
LL1, LL2
-0.8
28
VREF2, VREG5, VREG3, PGOOD1, PGOOD2, DRVL1, DRVL2, COMP1,
COMP2
-0.1
5.5
PGND1, PGND2
-0.1
VREF2
Source/sink current
UNIT
V
V
V
0.1
0.08
VBST
50
VREG5, VREF3 (source only)
Operating ambient temperature range, TA
-40
85
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mA
100
°C
5
TPS51120
SLUS670C – JULY 2005 – REVISED JANUARY 2015
www.ti.com
6.3 Thermal Information
TPS51120
THERMAL METRIC (1)
RHB
UNIT
32 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
38.5
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.4
Electrical Characteristics
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IINCCAP
Supply current
VIN current, VREG5=VREG3=No
Load, EN3=EN5=FLOAT,
EN1=EN2=5V, CS=5V, COMP
connected to Cap
Current mode
750
1500
IINNOCAP
Supply current
VIN current, VREG5=VREG3=No
Load, EN3=EN5=FLOAT;
D-CAP mode
EN1=EN2=5V, CS=5V, COMP=5V
700
1400
IIN5(STBY)
Stand-by current
VIN current, VREG5=No Load
EN3=0V, EN5=FLOAT,
EN1=EN2=0
5-V only
30
45
IIN3(STBY)
Stand-by current
VIN current, VREG3=No Load
EN3=FLOAT, EN5=0,
EN1=EN2=0
3.3-V only
12
20
100
160
10
20
IIN532(STBY) Stand-by current
VIN current, VREG5=VREG3=VREF2=No Load
EN3=EN5=FLOAT, EN1=EN2=0
IIN(SHDN)
VIN current, EN3=EN5=EN1=EN2=0V
Shut down current
μA
VOUT and VREF2 VOLTAGES
VOUT
Output voltage
VFB2 = 3.3 V, TA= 25°C, No Load
3.241
3.300
3.359
VFB2 = 3.3 V, TA= 0 to 85°C, No Load
3.234
3.300
3.366
VFB2 = 3.3 V, TA= -40 to 85°C, No Load
3.224
3.300
3.376
VFB1 = 5 V, TA= 25°C, No Load
4.910
5.000
5.090
VFB1 = 5 V, TA= 0 to 85°C, No Load
4.900
5.000
5.100
VFB1 = 5 V, TA= -40 to 85°C, No Load
4.885
5.000
5.115
Adjustable mode output range
VADJ
VADJ
Output regulation voltage
Output regulation voltage
tolerance
T
1.0
Adjustable mode
5.5
1.00
V
Adjustable mode, TA= 25°C
-0.9%
0.9%
Adjustable mode, TA= 0 to 85°C
-1.3%
1.3%
Adjustable mode, TA= -40 to 85°C
-1.6%
1.6%
2-V output regulation voltage
IVREF2 ± 50 μA, TA= 25°C
1.97
VVREF2T
2-V output regulation voltage
tolerance
IVREF2 ± 50 μA, TA= 0 to 85°C
1.96
2.04
IVREF2 ± 50 μA, TA= -40 to 85°C
1.95
2.05
IVFB
VFB input current
VVREF2
RDISCHARG Discharge switch resistance
2.00
VFBx=1.02V, COMPx=open
0.02
VFBx=1.02V, COMPx=5V
0.02
VOx=0.5V, TA= 25°C
V
2.03
V
μA
10
20
3.30
3.35
Ω
VREG3 VOLTAGE
VVREG3
VREG3 Output Regulation Voltage IVREG3 = 20 mA, 6V < VIN < 28V, TA= 25°C
VVREG3T
IVREG3
(1)
6
VREG3 Output Voltage Tolerance
VREG3 Output Current
3.25
IVREG3 = 1 - 50 mA , 6V < VIN < 28V, TA= 0 to 85°C
3.21
3.37
IVREG3 = 1 - 100 mA , 6V < VIN < 28V, TA= -40 to
85°C
3.16
3.39
TA = 25°C, VREG3=3.14V
(1)
170
V
mA
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
VLDO3SW
VREG3 Bootstrap Switch
Threshold
RLDO3SW
VREG3 Bootstrap Switch
Resistance
TEST CONDITIONS
MIN
Rising edge of VO2, VREG3 drops to VO2 voltage
TYP
2.85
Hysteresis
MAX
3.10
120
UNIT
V
mV
1.3
3.0
5.00
5.075
Ω
VREG5 VOLTAGE
VVREG5
VREG5 Output Regulation Voltage IVREG5 = 20 mA, 6V < VIN < 28V, TA= 25°C
VVREG5T
VREG5 Output Voltage Tolerance
4.925
IVREG5 = 1 - 50 mA , 6V < VIN < 28V, TA= 0 to 85°C
4.89
5.11
IVREG5 = 1 - 100 mA , 6V < VIN < 28V, TA= -40 to
85°C
4.80
5.15
(1)
IVREG5
VREG5 Output Current
TA = 25°C, VREG5=4.75 V
200
VLDO5SW
VREG5 Bootstrap Switch
Threshold
Rising edge of VO1, VREG5 drops to VO1 voltage
RLDO5SW
VREG5 Bootstrap Switch
Resistance
4.30
Hysteresis
mA
4.85
140
1.3
V
V
mV
3.0
Ω
TRANSCONDUCTANCE AMPLIFIER
μS
Gm
Gain
TA = 25°C
ICOMPSINK
COMP Maximum Sink Current
VFBx=1.05V, COMPx=1.28V
8
280
12
16
ICOMPSRC
COMP Maximum Source Current
VFBx=0.95V, COMPx=1.28V
-15
-11
-7
VCOMPHI
COMP High Clamp Voltage
CSx=0V, VFBx=0.95V
1.26
1.34
1.42
VCOMPLO
COMP Low Clamp Voltage
CSx=0V, VFBx=1.05V
1.08
1.12
1.20
Source, VVBST-DRVH = 1V
3.5
7
Sink, VDRVH-LL = 1V
1.5
3
Source, VVREG5-DRVL = 1V
3.5
7
Sink, VDRVL-PGND = 1V
1.5
3
DRVH-off to DRVL-on, TA= 25°C
20
μA
V
OUTPUT DRIVER
RDRVH
RDRVL
DRVH resistance
DRVL resistance
TD
Dead time
VDTH
DRVH-off threshold
LL to GND (1)
VDTL
DRVL-off threshold
DRVL to GND
DRVL-off to DRVH-on, TA= 25°C
30
ns
60
2
(1)
Ω
V
1.1
INTERNAL BST DIODE
VFBST
Forward Voltage
VVREG5-VBST, IF = 10 mA, TA= 25°C
IRBST
Reverse Current
IBST(LEAK)
VBST Leakage current
0.7
0.8
0.9
VBST = 34 V, VREG5=5V
0.1
1.0
VBST=34V, LL=28V, EN3=EN5=EN1=EN2=0V
0.1
1.0
V
μA
ON-TIME TIMER, INTERNAL SOFT-START and HOUSEKEEPING CLOCK
TON1a
On time, 5V, 180 kHz
VLL1=12V, VOUT1=5V, TONSEL=5V, TA= 25°C
2150
2340
2530
TON1b
On time, 5V, 220 kHz
VLL1=12V, VOUT1=5V, TONSEL=FLOAT, TA= 25°C
1790
1950
2110
TON1c
On time, 5V, 280 kHz
VLL1=12V, VOUT1=5V, TONSEL=2V, TA= 25°C
1370
1490
1610
TON1d
On time, 5V, 380 kHz
VLL1=12V, VOUT1=5V, TONSEL=GND, TA= 25°C
1020
1110
1200
TON2a
On time, 3.3V, 270 kHz
VLL2=12V, VOUT2=3.3V, TONSEL=5V, TA= 25°C
940
1030
1120
TON2b
On time, 3.3V, 330 kHz
VLL2==12V, VOUT1=3.3V, TONSEL=FLOAT, TA=
25°C
780
850
920
TON2c
On time, 3.3V, 430 kHz
VLL2==12V, VOUT1=3.3V, TONSEL=2V, TA= 25°C
580
650
720
TON2d
On time, 3.3V, 580 kHz
VLL2==12V, VOUT1=3.3V, TONSEL=GND, TA= 25°C
430
480
530
TON(MIN)1
Minimum on time, 5V
TA = 25°C, TONSEL=GND, VLL1=28V, VO1=1V
TON(MIN)2
Minimum on time, 3.3V
TA = 25°C, TONSEL=GND, VLL2=28V, VO2=1V
TOFF(MIN)
Minimum off time
TA = 25°C, VFB=0.9V, LL=0.5V
480
TSS
Internal Soft Start Timer
TA = 25°C, ENx>3V
772
70
45
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Electrical Characteristics (continued)
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
SLSS
Internal Soft Start Slope
FCLK
HK clock frequency
TEST CONDITIONS
TA = 25°C, ENx>3V, Slope wrt. VFB
MIN
TYP
230
290
350
0.3
0.6
0.8
(2)
MAX
0.3
UNIT
V/ms
kHz
UVLO/LOGIC THRESHOLD
VENLDOH
LDO enable threshold
VENLDOFL3
EN3, EN5, low to high
Hysteresis
0.2
EN3 pullup voltage
EN3 = FLOAT (OPEN) (2)
1.7
VENLDOFL5
EN5 pullup voltage
EN5= FLOAT (OPEN) (2)
3.3
IENLDOFL
EN3, EN5 pullup current
VENx < 0.5V
VUV(VREG5) VREG5 UVLO threshold
SKIPSEL threshold
4.0
3.8
4.0
4.2
V
Hysteresis
100
200
300
mV
0
0.7
Auto-SKIP Mode Enabled, Faults Off
1.3
2.2
PWM-Only Mode Enabled
2.7
5.5
Fast Switching Frequency
VTONSEL
ISEL
TONSEL threshold
SKIPSEL/TONSEL input current
μA
1.5
Wake up
Auto-SKIP Mode Enabled
VSKIPSEL
V
0
0.7
Medium Switching Frequency #2
1.3
2.2
Medium Switching Frequency #1
2.7
3.0
Slow Switching Frequency
4.5
5.5
SKIPSEL, TONSEL=0V
1
3
SKIPSEL, TONSEL=5V
1
2
0.9
1.2
2.75
2.90
2
3
VENSWSTAT EN1, EN2 SS Start Voltage
BJT Base input, Switcher begins to Track ENx
VENSWEND
EN1, EN2 SS End Voltage
‘Logic High’ Level for Switcher Enable when using
Internal Softstart, 0°C ≤ TA ≤ 85°C
IENSW1,2
EN1, EN2 Pullup Current
EN1, EN2=0.6V
0.5
1
VTHVFB1
VFB1 threshold
5.0V preset output
V5FILT
-0.3
VTHVFB2
VFB2 threshold
3.3V preset output
V5FILT
-0.3
V
μA
V
μA
V
CURRENT SENSE
VOCL
Current limit threshold
Resistor sense scheme , VPGND - VCS voltage,
PGOOD=Hi
ITRIP
CS Sink Current
RDS(ON) sense scheme, PGOOD=Hi, TA= 25°C
TCITRIP
ITRIP temperature Coefficient
RDS(ON) sense scheme, On the basis of 25°C
VOCLoff
OCP Comparator Offset
(VVREG5-CS-VPGND-LL) voltage, VVREG5-CS = 80mV,
RDS(ON) sense
VR(trip)
Current limit threshold setting
range
VV5FILT-VCS voltage
30
VZC
Zero cross detection Comparator
offset
VPGNDx-VLLx voltage, SKIPSEL=0V
-5
1
5
±7%
±10%
±13%
67
80
93
mV
9
10
11
μA
ppm/°
C
4500
-10
0
10
150
mV
POWERGOOD COMPARATOR
Power Bad Threshold
VTH(PG)
PGOOD Threshold
IPG(MAX
PGOOD Sink Current
PGOOD=0.5 V
TPGDEL
PGOOD Delay Timer
Delay for PGOOD in, ‘clks’=HK Clock
Hysteresis
±5%
2.5
5.0
mA
256
clks
UNDERVOLTAGE and OVERVOLTAGE PROTECTION
VOVP
VFBx OVP Trip Threshold
TOVPDEL
VFBx OVP Delay Time
(2)
8
OVP detect
110%
115%
2
120%
ms
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted)
PARAMETER
VUVP
VFBx UVP Trip Threshold
TUVPDEL
VFBx UVP Delay Timer
TEST CONDITIONS
UVP detect
MIN
TYP
MAX
65%
70%
75%
Hysteresis
6%
‘clks’=HK Clock
128
Shutdown temperature
145
UNIT
clks
THERMAL SHUTDOWN
TSDN1
Thermal shutdown threshold
Hysteresis
10
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6.5 Typical Characteristics
900
900
IINCAP= Current Mode
800
IIN − VIN Supply Current − µA
800
IIN − VIN Supply Current − µA
700
600
500
IINNOCAP= D−CAP Mode
400
300
0
50
100
0
TJ − Junction Temperature − °C
5
150
15
20
25
Figure 2. VIN Supply Current vs Input Voltage
140
140
120
120
100
80
60
40
100
80
60
40
20
0
0
50
100
TJ − Junction Temperature − °C
150
5
Figure 3. VIN Standby Current vs Junction Temperature
18
18
IIN(SHDN) − Shutdown Current − µA
20
16
14
12
10
8
6
4
2
10
15
20
VIN − VIN Input Voltage − V
25
Figure 4. VIN Standby Current vs Input Voltage
20
0
−50
10
VIN − VIN Input Voltage − V
IIN532 − Standby Current − µA
IIN532 − Standby Current − µA
300
100
0
−50
IINNOCAP= D−CAP Mode
400
100
20
IIN(SHDN) − Shutdown Current − µA
500
200
Figure 1. VIN Supply Current vs Junction Temperature
10
600
200
0
−50
IINCAP= Current Mode
700
16
14
12
10
8
6
4
2
0
TJ − Junction Temperature − °C
10
15
20
VIN − VIN Input Voltage − V
Figure 5. VIN Shutdown Current vs Junction Temperature
Figure 6. VIN Shutdown Current vs Input Voltage
0
50
100
5
150
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Typical Characteristics (continued)
16
0.5
ITRIP − Current Sense Current − µA
IBATT − Battery Current − mA
14
0.4
0.3
0.2
0.1
AUTO−SKIP
280 kHz (CH1)
430 kHz (CH2)
12
16
20
VIN − VIN Input Voltage − V
600
6
4
600
fSW − Switching Frequency − kHz
500
400
CH1
300
200
0
50
100
TJ − Junction Temperature − °C
150
Figure 8. Current Sense Current vs Junction Temperature
CH2
TONSEL = GND
fSW − Switching Frequency − kHz
8
0
−50
24
Figure 7. No-Load Battery Current vs Input Voltage
100
TONSEL = 2 V
500
CH2
400
300
CH1
200
100
0
0
6
10
14
18
VIN − VIN Input Voltage − V
24
28
Figure 9. Switching Frequency vs Input Voltage
400
6
10
14
18
24
VIN − VIN Input Voltage − V
28
Figure 10. Switching Frequency vs Input Voltage
400
TONSEL = FLOAT
TONSEL = 5 V
350
350
fSW − Switching Frequency − kHz
fSW − Switching Frequency − kHz
10
2
0
8
12
CH2
300
250
200
CH1
150
100
50
300
CH2
250
200
CH1
150
100
50
0
0
6
10
14
18
24
VIN − VIN Input Voltage − V
28
Figure 11. Switching Frequency vs Input Voltage
6
10
14
18
24
VIN − VIN Input Voltage − V
28
Figure 12. Switching Frequency vs Input Voltage
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Typical Characteristics (continued)
600
600
TONSEL = 2 V
500
CH2
Auto−skip
CH2−PWM Only
fSW − Switching Frequency − kHz
fSW − Switching Frequency − kHz
TONSEL = GND
400
CH1−PWM Only
CH1
Auto−skip
300
200
100
500
CH2
Auto−skip
CH2−PWM Only
400
300
CH1−PWM Only
100
0
0.001
0.01
0.1
1
IOUT − Output Current − A
0
0.001
10
Figure 13. Switching Frequency vs Output Current
0.01
0.1
1
IOUT − Output Current − A
400
TONSEL = FLOAT
fSW − Switching Frequency − kHz
TONSEL = 5 V
CH2−PWM Only
300
CH2 Auto−skip
200
CH1−PWM Only
100
300
CH2−PWM Only
CH2 Auto−skip
200
CH1−PWM Only
100
CH1 Auto−skip
CH1 Auto−skip
0
0.001
0.01
0.1
1
0
0.001
10
IOUT − Output Current − A
Figure 15. Switching Frequency vs Output Current
0.01
0.1
1
IOUT − Output Current − A
10
Figure 16. Switching Frequency vs Output Current
150
5.100
140
130
120
OVP
100
90
80
70
UVP
60
VREG5 − VREG5 Output Voltage − V
VOVP, VUVP − OVP/UVP Threshold − %
10
Figure 14. Switching Frequency vs Output Current
400
fSW − Switching Frequency − kHz
CH1
Auto−skip
200
5.050
5.000
50
0
−50
4.950
0
50
100
TJ − Junction Temperature − °C
0
Figure 17. OVP/UVP Threshold Voltage vs Junction
Temperature
12
20
40
60
80
100
IVREG5 − VREG5 Output Current − mA
Figure 18. VREG5 Output Voltage vs Output Current
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3.340
2.020
3.320
2.015
VREF2 − VREF2 Output Voltage − V
VREG3 − VREG3 Output Voltage − V
Typical Characteristics (continued)
3.300
3.280
3.260
3.240
3.220
2.010
2.005
2.000
1.995
1.990
1.985
3.200
0
20
40
60
80
1.980
−100 −80 −60
100
Figure 19. VREG3 Output Voltage vs Output Current
20
40
60
80 100
Figure 20. VREF2 Output Voltage vs Output Current
3.390
5.050
PWM Only
VOUT2 − 3.3−V Output Voltage − V
PWM Only
VOUT1 − 5-V Output Voltage − V
−40 −20 0
IREF2 − VREF2 Output Current − µA
IVREG5 − VREG3 Output Current − mA
5.025
5.000
Auto−skip
4.975
4.950
0.001
0.01
0.1
1
IOUT1 − 5-V Output Current − A
3.330
Auto−skip
3.300
3.270
0.001
10
Figure 21. 5-V Output Voltage vs Output Current
3.360
0.01
0.1
1
IOUT2 − 3.3-V Output Current − A
Figure 22. 3.3-V Output Voltage vs Output Current
3.32
5.050
VOUT2 − 3.3-V Output Voltage − V
VOUT1 − 5-V Output Voltage − V
3.32
5.025
5.000
IO = 6 A
4.975
IO = 0 A
4.950
3.31
3.33
IO = 6 A
3.30
IO = 0 A
3.28
3.27
6
8
10
12 14 16 18 20 22
VIN − VIN Input Voltage − V
24
6
26
8
10
12
14
16
18
20
22
24
26
VIN − VIN Input Voltage − V
Figure 23. 5-V Output Voltage vs Input Voltage
Figure 24. 3.3-V Output Voltage vs Input Voltage
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Typical Characteristics (continued)
100
100
Auto−Skip
Auto−Skip
80
VIN = 8 V
VIN = 8 V
VIN = 12 V
η − Efficiency − %
η − Efficiency − %
80
VIN = 8 V
60
VIN = 20 V
40
VIN = 12 V
VIN = 8 V
60
VIN = 20 V
40
VIN = 12 V
VIN = 12 V
20
20
PWM Only
5-V Switcher ON
VIN = 20 V
PWM Only
0
0.001
0.01
0.1
1
10
0
0.001
IOUT1 − 5−V Output Current − A
Figure 25. 5-V Efficiency vs Output Current
14
VIN = 20 V
0.01
0.1
1
IOUT1 − 3.3−V Output Current − A
10
Figure 26. 3.3-V Efficiency vs Output Current
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7 Detailed Description
7.1 Overview
The TPS51120 is a highly sophisticated dual synchronous buck controller targeted for notebook I/O and system
bus supply solutions. It support both D-CAP mode and current mode. With D-CAP control mode implemented,
compensation network can be removed. Besides, the fast transient response also reduced the output
capacitance. In case very low output ripple voltage needed, current mode can be implemented with simplified
loop compensation and ceramic output capacitors.
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7.2 Functional Block Diagram
Figure 27. Block Diagram (One Channel Only Shown)
16
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7.3 Feature Description
7.3.1 PWM Operation
The switching mode power supply (SMPS) block of TPS51120 supports an adaptive on time control pulse-widthmodulation (PWM). Switching frequency is selectable from four choices. The TPS51120 supports both true
current mode control and D-CAP mode control, selectable up to the requirements from system design. All Nchannel MOSFET totem-pole architecture is employed for external switches. The synchronous top (high-side)
MOSFET is turned on, or is “SET”, at the beginning of each cycle. This MOSFET is turned off, or is “RESET”
after a constant “on-time” period which is defined by the frequency of customer’s choice and input and output
voltage ratio. For different control mode, the condition for the top MOSFET turn on again is different.
If current mode is implemented, then the top MOSFET is turned on again if inductor current is reduced to meet
both conditions of:
1. the current level corresponds to the error amount of output voltage and,
2. below the overcurrent limit level
If D-CAP mode is implemented, then the top MOSFET is turned on again when both of below conditions is met:
1. the internal or external feedback voltage cross with the internal 1-V reference and,
2. the inductor current below the overcurrent limit level
Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom
(lowside) or the rectifying MOSFET is turned on each cycle in the negative phase to the top MOSFET to keep
the conduction loss minimum. The rectifying MOSFET turns off on the event reverse inductor current flow is
detected. This enables seamless transition to skip mode function so that high efficiency is kept over a broad
range of load current. At the beginning of the soft start period, the rectifying MOSFET remains in the off state
until the top MOSFET is turned on for at least once.
7.3.2 Adaptive On-Time Control
The TPS51120 employs adaptive on time control scheme and does not have a dedicated oscillator on board.
However, it works almost constant frequency over the entire input voltage range (pseudo-constant frequency) by
feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is controlled inverse
proportional to the input voltage and proportional to the output voltage so that the duty ratio is kept as VOUT/VIN
technically with the same cycle time. The input voltage monitoring is accomplished through sensing the LL node,
not at VIN node, during the ‘ON’ state. This eliminates the influence of the voltage drop across the top MOSFET
to the frequency especially in heavy load condition. The VIN pin is not used for the on-time control but used only
for the 5 V and 3.3 V regulators’ supply. The switching frequency is selectable from four combinations shown in
the table below by setting TONSEL pin voltage. This allows the system design to pursue highest efficiency (5
V/180 kHz, 3.3 V/270 kHz), smallest components size (5 V/380 kHz, 3.3 V/580 kHz) or a good balance of both in
the medium. Also shown in the table are the typical on-time for each frequency and 5 V, 3.3 V outputs at
VIN=12. Output voltage feed-forward is enabled after the output voltage exceeds 1.0 V in order to achieve stable
start up.
Table 1. Frequency Selection and Typical On-Time
TONSEL CONNECTION
CH1(LL1=VIN=12 V)
CH2 (LL2=VIN=12 V)
FREQUENCY (kHz)
ON-TIME @ 5 V (ns)
FREQUENCY (kHz)
ON-TIME @ 3.3 V (ns)
V5FILT
180
2340
270
1030
FLOAT (OPEN)
220
1950
330
850
VREF2
280
1490
430
650
GND
380
1111
580
480
7.3.3 Light Load Operation
TPS51120 automatically reduces switching frequency at light load condition to maintain high efficiency. This
reduction of frequency is achieved smoothly and without an increase in load regulation. Detail operation is
described as follows. As the output current decreases from heavy load condition, the inductor current is also
reduced and eventually comes to the point that its ‘valley’ touches zero current, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero
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Feature Description (continued)
inductor current is detected. The on-time is kept the same as that in the heavy load condition. As the load current
further decreases, the converter runs in discontinuous conduction mode and it takes longer and longer to
discharge the output capacitor to the level that requires next ‘ON’ cycle. This results in reducing the switching
frequency. In reverse, when the output current increases from light load to heavy load, switching frequency
increases to the constant predetermined frequency as the inductor current reaches to the continuous conduction.
The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and
discontinuous conduction mode) can be calculated as shown in Equation 1.
I OUT(LL) +
2
1
L
ǒV IN * V OUTǓ
f
V OUT
V IN
(1)
where f is the PWM switching frequency which is determined by TONSEL pin. Switching frequency versus output
current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportional to the
output current from the IOUT(LL) given in Equation 1.
7.3.4 Forced PWM Operation
Tying SKIPSEL to V5FILT or leaving it float force the part to operate in continuous conduction mode for entire
load range by disabling zero inductor current detection. Switching frequency is kept at the frequency selected by
TONSEL input. System designers may want to use this mode to avoid certain frequency in light load condition
with the cost of low efficiency. However, please be aware the output has a capability to both sink and source
current in this mode. If the output terminal is connected to a voltage source higher than the regulated voltage, the
converter sinks current from the output and boosts the charge into the input capacitor. This may cause
unexpected high voltage at VIN and may damage the part.
7.3.5 5-V, 100-mA, LDO and Switchover (VREG5)
A 5-V, 100-mA linear regulator is integrated in the TPS51120. This low drop-out (LDO) regulator services the
main analog supply rail for the IC and provides the current for the gate drivers. The regulator is a PMOS type
with transconductance control and the pole is determined by the value of output capacitance. Typically, the value
of this capacitor must be greater than 4.7 μF. A 10-μF ceramic capacitor is recommended for a typical design.
Current limit and thermal protection are included in the regulator. Additionally, if the VO1 voltage exceeds 4.8 V,
then the regulator is switched off and the 5V rails are bootstrapped to the 5-V switcher output, improving the
efficiency of the converter. A glitch-free switchover is accomplished. The VREG5 output voltage does not show a
short “glitch” down to 4.8 V when this bootstrapping action is taken. The switchover impedance from VO1 to
VREG5 is typically 1.3 Ω. Standby current is designed for 30-μA operation allowing the user to leave the
regulator alive while maintaining maximum battery life. The EN5 pin is a high voltage input and can be tied to
VBAT or left open to enable the 5-V regulator. This 5-V regulator must be enabled prior to enable switching
regulators. Pull EN5 to ground to shut off the regulator. Disabling the regulator does not promise shutting down
the switchers once 5 volts is supplied via the bootstrap path. Because switchover occurs, the 5-V switcher MUST
be turned off with the LDO in order to shut down the device. EN5 does NOT function as a master disable.
7.3.6 3.3-V, 100-mA, LDO and Switchover (VREG3)
A 3.3-V, 100-mA linear regulator is integrated as a second regulator in the TPS51120. This LDO provides a
handy standby supply for 3.3 V ‘Always On’ voltages in the notebook system. The characteristics of this LDO are
identical to the 5V LDO except for the switchover voltage. Apply 10-μF ceramic capacitor from VREG3 to PGND
in adjacent to the device. If the VO2 voltage exceeds 3.1 V, then this regulator is switched off and the 3.3 V rail
is bootstrapped to the 3.3 V switcher. Note if the VO2 voltage is set higher by external feedback dividers, for
example 5 V, that high voltage is presented at VREG3 after switchover. The EN3 pin is a low voltage input that
can be tied to V5FILT or left open to enable the 3.3-V regulator. This 3.3-V regulator can be turned on or kept
alive independent to the 5-V regulator.
18
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Feature Description (continued)
7.3.7 2-V, 50-uA Sink - Source Reference (VREF2)
This is a handy reference for generating auxiliary voltages. The tolerance is ±2% over 50-μA load and 0°C to
85°C ambient temperature ranges. The four-state logic (SKIPSEL, TONSEL) takes advantage of this reference
for additional selection modes. This reference is enabled when both EN3 and EN5 become high, shuts down
after both switchers are turned off and VREG5 or VREG3 is shut down. Please refer to Table 3. If this output is
forcibly tied down to ground, both SMPS are turned off without latch. Bypass VREF2 pin to GND by a 1-nF
capacitor.
7.3.8 Low-Side Driver
The low-side gate driver, DRVL, is designed to drive high current low RDS(on) N-channel MOSFET(s). The
maximum drive voltage is 5.5 V which is delivered from VREF5 pin. The instantaneous drive current is supplied
from the output capacitor at the VREF5 pin. The average drive current is equal to the FET’s gate charge at
VGS=5 V times switching frequency. The VREG5 pin voltage may contain high frequency noise due to parasitic
inductance by wiring and pointing current flow into the gate capacitor. The drive capability is represented by its
internal resistance, which are 3.5 Ω for VREG5 to DRVL and 1.5 Ω for DRVL to PGND. Adaptive dead time
control generates delay times between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top
MOSFET on, preventing the totem-pole switches to shoot through. Top MOSFET off is detected as LL-node
voltage declining below 2 V. Bottom MOSFET off is detected as DRVL voltage become 1.1 V.
7.3.9 High-Side Driver
The high-side gate driver, DRVH, is designed to drive high current, low RDS(on) N-channel MOSFET(s). When
configured as a LL-node referenced floating driver, connect 0.1-μF ceramic capacitor between corresponding
VBST pin and LL pin. A 5-V bias voltage is delivered from VREG5 supply. VBST is internally connected to
VREG5 through a high voltage PN diode. This internal diode provides sufficient gate voltage for ordinary 4.5-V
drive power MOSFETs and helps reducing external component. However, in the case where the gate bias
voltage is critical for driving the top MOSFET, application designer may add an external schottky diode from
VREG5 pin to VBST pin. Note schottky diodes have quite high reverse leakage current at high temperature. The
instantaneous drive current is supplied by the flying capacitor connected between VBST and LL pins. The
average drive current is equal to the gate charge at VGS=5 V times switching frequency. The drive capability is
represented by its internal resistance, which are 3.5-Ω for VBST to DRVH and 1.5Ω for DRVH to LL. The
maximum recommended voltage that can be applied between DRVH pin and LL pin is 5.5 V, DRVH pin to PGND
pin is 34 V.
7.3.10 Soft-Start
The TPS51120 has an internal 3-ms voltage-servo soft start for each channel. When the EN1 or EN2 pin
exceeds 0.9 V, an internal DAC begins ramping up the reference voltage. Smooth control of the output voltage
during start up is maintained. However, if a slower soft-start is required, an external capacitor may be tied from
the EN1 or EN2 pin to GND. In this case, the TPS51120 charges the external capacitor with the integrated 2-μA
current source. The lower of either the EN voltage slew rate or the internal soft start slew rate dominates the
start-up ramp. In addition, if tracking discharge is required, the EN pin can be used to control the output voltage
discharge smoothly. An approximate value for the soft start reference voltage as a function of EN voltage is
VSSREF = (VENX – 0.9)/1.5 < 1 V. At the beginning of soft-start period, the rectifying MOSFET maintains an off
state until the top MOSFET is turned on for at least once. This prevents high negative current to flow back from
the output capacitor in the event of output capacitor pre-charged condition.
7.3.11 Soft-Stop
Discharge mode or ‘Soft Stop’ is always on during Faults or Disable. In this mode, an event that would cause the
switcher to be turned off (EN1 or EN2 low, OVP, UVP, UVLO) causes the output to be discharged through 10-Ω
transistor inside the VO terminal. The external rectifying MOSFET is not turned on for the soft off operation to
avoid a chance to cause negative voltage at the output. Soft-stop time constant is a function of the output
capacitance and the resistance of the discharge transistor. This discharge ensures that, upon restart, the
regulated voltage always starts from zero volts. In case a SMPS is restarted before discharge completion, softstop is terminated and the switching resumes after the reference level comes back to the remaining output
voltage.
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Feature Description (continued)
7.3.12 Powergood
The TPS51120 has dedicated powergood output for each SMPS, PGOOD1 and PGOOD2. The PGOOD
monitors are open drain 5-mA pull down outputs. These outputs are low on startup and stay low until the switcher
feedback voltages are within a specified range for 256 clocks or approximately 1 ms. If the VFB pin falls outside
the 10% tolerance band, the respective PGOOD pin goes low within microseconds. Then if the VFB pin comes
back within 5% of target (1 V) for greater than 1 ms, then the respective PGOOD pin goes high again. The
PGOOD pin should be typically pulled up through a 100 kΩ or greater value resistor to the V5FILT pin. Both
PGOOD pins go low during fault conditions (Thermal Shutdown, UVLO, UVP, OVP) and Disable.
7.3.13 Current Sensing and Overcurrent Protection
The SMPS has cycle-by-cycle over current limiting. The inductor current is monitored during the rectifying
MOSFET is on and the controller does not allow the next ON cycle while the current level is above the trip
threshold. In order to provide good accuracy and cost effective solution, TPS51120 supports both of external
resistor sensing and MOSFET RDS(on) sensing which are selected by CS terminal connection. For resistor
sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of the
bottom MOSFET and PGND. CS pin is connected to the bottom MOSFET source terminal node. The inductor
current is monitored by the voltage between PGND pin and CS pin. In this scheme, the trip level is fixed value of
80 mV. For RDS(on) sensing scheme, CS terminal is connected to V5FILT through a trip voltage setting resistor
RTRIP. In this scheme, CS terminal sinks 10-μA ITRIP current and the trip level is set to the voltage across the
RTRIP. The trip level should be in the range of 30 mV to 150 mV. This allows designer to select a variety of
MOSFETs for the bottom arm. The inductor current is monitored by the voltage between PGND pin and LL pin so
that LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/°C temperature
slope, with respect to its 25°C value, to compensate the temperature dependency of the RDS(on). In either
scheme, PGND is used as the positive current sensing node so that PGND pin should be connected to the
proper current sensing device, i.e. the sense resistor or the source terminal of the bottom MOSFET. In an
overcurrent condition, since the current to the output capacitor is limited while the load drags more, the output
voltage tends to go down. It ends up with passing into the undervoltage protection and latches off as both DRVH
and DRVL are at low level.
Table 2. Current Sensing Connection
CS
Threshold
Temperature
Coefficient (ppm/°C)
RDS(on) sensing
V5FILT
ITRIP × RTRIP / RDS(on)
4500
RSENSE sensing
Bottom FET source node (=RSENSE (-) node)
80 mV / RSENSE
none
7.3.14 Overvoltage Protection
For over voltage protection (OVP), the TPS51120 monitors VFB voltage. When the VFB voltage is higher than
115% of the target, the OVP comparator output goes high and the circuit latches both switchers. The offending
channel is latched DRVH low and DRVL high, the other channel is simply latched as DRVH and DRVL at low. Be
aware negative voltage may appear at the output terminal of the offending channel because of LC resonant
configured by the power inductor and the output capacitor. The system designer is responsible to this negative
voltage if any protection is need. The OVP propagation delay is less than 3 μs.
7.3.15 Undervoltage Protection
For under voltage protection (UVP), the TPS51120 monitors VFB voltage. When the VFB voltage is lower than
70% of the target and the UVP comparator output goes high, the internal UVP delay counter begins count. After
the 128 clocks, approximately 0.5 ms, TPS51120 latches off both channels as DRVH and DRVL at low. This
function is enabled after the softstart reference has exceeded the internal 1-V reference operation to ensure
startup. Please refer to Table 4.
20
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Feature Description (continued)
7.3.16 5-V Supply and UVLO Protection
TPS51120 has two 5-V terminals. VREG5 is the output of 5-V linear regulator. This terminal also serves as input
pin for the gate driver circuits. Internal switchover FET is connected between this pin and VO1. V5FILT is the VCC
supply input for the control circuitry on the chip. Connect with R-C low pass filter from VREG5 to this V5FILT to
eliminate spiky high frequency noise. State definition pins such as SKIPSEL, TONSEL, VFB (fixed output case)
and COMP (for D-CAP mode) or CS resistors that need stable 5V should refer to V5FILT. The part has 5-V
supply under voltage lock out protection (UVLO) to prevent unpredictable operation under insufficient power. The
TPS51120 monitors VREG5 voltage. When the VREG5 voltage is lower than UVLO threshold, the SMPS’s are
shut off. The output discharge or ‘soft stop’ feature is enabled for the channel one and channel two. However,
because the discharge circuit derives its power from the 5-V line, power must be presented long enough to
ensure that discharge is complete during shutdown. Also, during power up, the TPS51120 attempts to discharge
the output capacitor until the UVLO (on) threshold is reached. A 5-V UVLO is non-latch protection and is
automatically resumed up on 5-V recovery.
7.3.17 VIN Line Sag Protection (Dynamic UVP)
Since the TPS51120 serves primarily as system power (i.e. used for generating 3.3 V and 5 V) it is very
important that the system not enter UVP if the VIN supply has dropped below 6V. UVP would be caused by the
5-V output dropping due to input line sag. When the VIN pin drops below the 5-V regulator voltage, the 5-V
regulator ‘tracks’ VIN (LDO operation). The UVP threshold is adjusted downward when the VREG5 is below
4.8 V. This ensures that 5-V supply UVLO trips before the latching UVP condition occurs and the system power
can recover normally when VIN recovers. This feature is very useful for transient VIN events such as adapter
insertion
7.3.18 Thermal Shutdown
The TPS51120 employs thermal shutdown for the switchers at 145°C. This is a non-latch protection with
hysteresis of 10°C. Both switching regulators and both internal regulators stop. VREG5 and VREG3 LDOs may
not turn on if the part is preheated above the recovery temperature before starting up. Reduce the temperature to
or below TA = 85°C to resume operation safely.
Table 3. Enable Logic States (Vout1=5 V, Vout2=3.3 V)
EN3
EN1
EN2
VREG5
VREG3
VREF2 (2)
SMPS1
SMPS2
Low
Low
High or Low
High or Low
Off
Off
Off
Off
Off
Low-to-High
Low
High or Low
High or Low
LDO 5 V
Off
Off
Off
Off
EN5
(1)
Low
Low-to-High
High or Low
High or Low
Off
LDO 3.3 V
Off
Off
Off
Low-to-High
Low-to-High
Low
Low
LDO 5 V
LDO 3.3 V
On
Off
Off
High
High
Low
Low-to-High
LDO 5 V
SW 3.3 V
On
Off
On
High
High
Low-to-High
Low
SW 5 V
LDO 3.3 V
On
On
Off
High
High
High
High
SW 5 V
SW 3.3 V
On
On
On
High-to-Low
High-to-Low
High
High
SW 5 V
SW 3.3 V
On
On
On
High
High
High-to-Low
High-to-Low
LDO 5 V
LDO 3.3 V
On
Off
Off
High-to-Low
High
High-to-Low
High
Off
LDO 3.3 V
Off
Off
Off
High
High-to-Low
High
High-to-Low
SW 5 V
Off
On
On
Off
High
High-to-Low
Low
High-to-Low
LDO 5 V
Off
Off
Off
Off
High-to-Low
High
Low
Low
Off
LDO 3.3 V
Off
Off
Off
High
High-to-Low
Low
Low
LDO 5 V
Off
Off
Off
Off
(1)
(2)
Because of Switch-over, the 5-V switcher MUST be turned off with the LDO in order to shut down the device. EN5 does NOT function as
a master DISABLE.
Forcing VREF2 output to ground disables SMPS1 and SMPS2 without latch.
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Feature Description (continued)
Table 4. Protection States (Vout1 = 5 V, Vout2 = 3.3 V)
DRVH1
DRVL1
DRVH2
DRVL2
PGOOD1
PGOOD2
VREG5
VREG3
VREF2
FOR
RESTART
UVPch1
Low
Low
Low
Low
Low/Low
LDO 5 V
LDO 3.3 V
On
Toggle EN1
UVPch2
Low
Low
Low
Low
Low/Low
LDO 5 V
LDO 3.3 V
On
Toggle EN2
OVPch1
Low
High
Low
Low
Low/Low
LDO 5 V
LDO 3.3 V
On
Toggle EN1
OVPch1
Low
Low
Low
High
Low/Low
LDO 5 V
LDO 3.3 V
On
Toggle EN2
Thermal SHDN
Low
Low
Low
Low
Low/Low
Off
Off
Off
Lower Package
Temperature
VIN < 5.0
Normal
Normal
Normal
Normal
Low/Normal
SW 5 V
SW 3.3 V
On
Raise VIN
VREG
UVLO
Low
Low
Low
Low
Low/Low
LDO but
dropping
LDO 3.3 V
On
Raise VIN,
Reduce 5V
current
OCPch1
Limited
Duty
Estended
Duty
Normal
Normal
Low/Normal
LDO 5 V
SW 3.3 V
On
Reduce CH1
Current
OCPch2
Normal
Normal
Limited
Duty
Estended
Duty
Normal/Low
SW 5 V
LDO 3.3 V
On
Reduce CH2
Current
EN1 Low
Low
Low
Normal
Normal
Low/Normal
LDO 5 V
SW 3.3 V
On
Float or tie to
VREG5
EN2 Low
Normal
Normal
Low
Low
Normal/Low
SW 5 V
LDO 3.3 V
On
Float or tie to
VREG5
EN1, EN2, EN3
Low
Low
Low
Low
Low
Low/Low
LDO 5 V
Off
Off
Float EN3, then
float EN1,2 or
tie to VREG5
EN5, EN1 Low
Low
Low
Low
Low
Low/Low
Off
LDO 3.3 V
Off
Float EN5 or tie
to VBAT, tie
EN1 to VREG5
7.4 Device Functional Modes
7.4.1 Current Mode
The current mode scheme is a sequence of feedback control described as follows. The output voltage is
monitored at the middle point of voltage divider resistors and fed back to a transconductance amplifier. The
amplifier outputs target current level proportional to error amount between the feedback voltage and the internal
1 V reference voltage. The inductor current level is monitored during the off-cycle, when rectifying MOSFET is
turned on. The PWM comparator compares the inductor current signal with this target current level that is
indicated at the COMP pin voltage. When both signals are equal (at the valley of the current sense signal), the
comparator provides the “SET” signal to the gate driver latch. The current mode option has relatively higher
flexibility by the external compensation network provided to the COMP pin. And it is suitable for lowest ripple
design with output capacitor(s) having ultra-low ESR. When sensing the inductor current, accuracy and cost
always trades off. In order to give the circuit designer a choice between these two, TPS51120 supports both of
external resistor sensing and MOSFET RDS(on) sensing. Please contact factory for current mode EVM with RSENSE
capability.
22
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Device Functional Modes (continued)
C23
180 pF
R24
15 kΩ
R25
16.5 kΩ
C13
220 pF
C22
1 nF
C12
R14
2.2 nF 11 kΩ
R24
33 kΩ
2
1
VO1
10 EN3
3
COMP1
EN_LDO3
EN5
R21
100 kΩ
4
VFB1
9
5
VREF2
EN_LDO5
6
GND
GND
7
VFB2
8
VO2
GND
COMP2
C31
1 nF
V5FILT
R15
26.7 kΩ
R14
33 kΩ
SKIPSEL
R11
12 mΩ
TONSEL 31
PowerPad
GND
11 PGOOD2
P_GOOD2
V5FILT
32
PGOOD1 30
P_GOOD1
VBAT
Q3
IRF7821
L2
1.2 μH
VO2
1.5 V/6 A
12 EN2
EN_2
VBAT
C21
0.1 μF
EN1 29
TPS51120RHB
(QFN32)
13 VBST2
VBST1 28
14 DRVH2
DRVH1 27
C11
0.1 μF
Q1
IRF7821
L1
2.2 μH
+
+
15 LL2
21
PGND1
20
CS1
19
VREG5
18
VIN
17
VREG3
PGND2
20 μF
C2B
EEFUE0E221R
CS2
DRVL2
16
C2A
EEFUE0E221R
22
23
24
R50
5.1 Ω
R20
12 mΩ
C30
10 μF
−
PGND2
VO1
1.8 V/6 A
LL1 26
V5FILT
Q4
IRF7832
VO2_GND
EN_1
C51
1 μF
DRVL1
25
VBAT
C50
10 μF
Q2
IRF7832
20 mF
C1B
EEFUE0E221R
R10
12 mΩ
−
VO1_GND
C1A
EEFUE0E221R
PGND1
Figure 28. Current Mode, External 1.8-V / 6-A, 1.5-V / 6-A, RSENSE Sensing
7.4.1.1 Current Mode Operation
A buck converter using TPS51120 current mode operation can be partitioned into three portions, a voltage
divider, an error amplifier and a switching modulator. By linearizing the s witching modulator, we can derive the
transfer function of the whole system. Since current mode scheme directly controls the inductor current, the
modulator can be linearized as shown in Figure 29.
Figure 29. Linearizing the Modulator
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Device Functional Modes (continued)
Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal
model. As a result, a modulated current source including the power inductor can be modeled as a current source
with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model
is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although
the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew
rate of the current source. This means the buck converter’s load transient response, one of the large signal
behaviors, can be improved by using smaller inductance without affecting the loop stability.
Total open loop transfer function of the whole system is given by Equation 2.
H(s) + H 1(s) H 2(s) H 3(s)
(2)
Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of three block is shown in Equation 3
through Equation 5.
R2
H 1(s) +
ǒR2 ) R1Ǔ
(3)
R O ǒ1 ) s
H 2(s) + * Gm
H 3(s) +
ǒ1 ) s
(1 ) s
CO
ǒ1 ) s
CO
CC
ESR)
RLǓ
CC
RCǓ
R OǓ ǒ1 ) s
C C2
R CǓ
(4)
RL
RS
(5)
There are three poles and two zeros in H(s). Each pole and zero is given by Equation 6 through Equation 10.
1
w P1 +
ǒCC ROǓ
w P2 +
w P3 +
w Z1 +
w Z2 +
(6)
1
ǒCO
RLǓ
(7)
1
ǒCC2
RCǓ
(8)
1
ǒCC
RCǓ
(9)
1
ǒCO
ESRǓ
(10)
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be
kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by next
equation Equation 11.
Gm RC + 1
1.0
Gm R C
R2
f0 + 1
2p R1 ) R2
2p VOUT
CO
RS
CO
RS
(11)
Based on small signal analysis above, the external components can be selected by following manner.
1. Choose the inductor.The inductance value should be determined to give the ripple current of approximately
1/4 to 1/2 of maximum output current.
L+
ǒVIN(max) * VOUTǓ
1
I IND(ripple)
f
VIN(max)
VOUT
+
ǒV IN(max) * V OUTǓ
2
I OUT(max)
f
V IN(max)
V OUT
(12)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 13.
24
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Device Functional Modes (continued)
I IND(peak) +
V TRIP
) 1
RDS(on) L f
ǒVIN(max) * VOUTǓ
V OUT
VIN(max)
(13)
2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s
on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order
to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with
the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of
the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency
more at high load conditions. When using external resistor current sensing, there is no restriction for low
RDS(on). However, the current sensing resistance RS itself affects the efficiency.
3. Choose output capacitor(s). If organic semiconductor capacitors (OS-CON) or specialty polymer capacitors
(SP-CAP), are used, the ESR to achieve required ripple value at a stable state or transient load condition
determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The
peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR
times the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR is
small enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven by
output capacitance becomes the key factor to determine the capacitor(s).
4. Determine f0 and calculate RC using Equation 14. Note that higher RC shows faster transient response in
cost of unstableness. If the transient response is not enough even with high RC value, try increasing the
output capacitance. Recommended f0 is f/4.
CO
R C v 2p f 0 V OUT
RS
Gm
(14)
5. Calculate CC2. The purpose of this capacitance is to cancel the zero caused by ESR of the output capacitor.
If ceramic capacitor are used, there is no need for CC2.
1
1
w z2 +
+ wp3 +
ǒCO ESRǓ
ǒC C2 RCǓ
(15)
C C2 +
CO
ESR
RC
(16)
6. Calculate CC. Purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it
causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined
by CC and RC. Recommended ωz1 is 10 times lower to the f0 frequency.
f
1
f z1 +
+ 0
10
2p C C R C
(17)
7. In case of adjustable mode, determine the value of R1 and R2. Recommended R2 value is from 10 kΩ to
20 kΩ. Determine R1 using Equation 18.
R 1 + ǒVOUT * 1.0Ǔ
R2
(18)
7.4.2 D-Cap Mode
The D-CAP mode operation is enabled by tying the COMP pin to V5FILT. In this mode, the PWM comparator
monitors the feedback voltage directly and compares the voltage with the internal 1-V reference. When both
signals are equal at the valley of the voltage sense signal, the comparator provides the “SET” signal to the top
MOSFET gate driver. Because the compensation network is implemented on the part and the output waveform
itself is used as the error signal, external circuit design is largely simplified. Another advantage of the D-CAP
mode is its inherent fast transient response. A trade-off is a sufficient amount of ESR required in the output
capacitor. SPCAP or POSCAP is recommended. The inductor current information is still used in the D-CAP
mode for over current protection and light load operation. Do NOT neglect current sensing design in this mode.
To summarize, the D-CAP mode is suitable for the lowest external component count with the fastest transient
response, but with relatively large ripple voltage. It is easy to design the loop once appropriate output capacitor
and inductor current ripple is selected.
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Device Functional Modes (continued)
V5FILT
C31
1 nF
VBAT
EN_2
L2
2.2 µH
3
2
1
Q3
IRF7821
VREF2
VFB1
COMP1
VO1
SKIPSEL
32
TONSEL 31
11 PGOOD2
PGOOD1 30
TPS51120RHB
(QFN−32)
12 EN2
C21
0.1 µF
R11
100 kΩ
P_GOOD1
GND
VBAT
EN1 29
EN_1
13 VBST2
VBST1 28
C11
0.1 µF
14 DRVH2
DRVH1 27
C10
20 µF
Q1
IRF7821
L1
4.7 µH
+
+
PowerPAD
CS1
PGND1
17
VIN
DRVL2
VREG5
16
V5FILT
Q4
IRF7832
LL1 26
VREG3
C2A
150 µF
15 LL2
CS2
C2B
150 µF
VO2_GND
4
10 EN3
PGND2
VO2
3.3V/6A
5
EN5
EN_LDO3
C10
20 µF
6
GND
9
7
VFB2
EN_LDO5
P_GOOD2
8
COMP2
GND
VO2
R21
100 kΩ
18
19
20
21
22
23
24
Q2
IRF7832
DRVL1
C1A
150 µF
VO1
5V/6A
C1B
150 µF
25
−
VO1_GND
−
PGND1
R22
3.3 kΩ
PGND2
R50
5.1Ω
C30
10 µF
C51
1 µF
R12
3.6 kΩ
C50
10 µF
VBAT
C30
NA
Figure 30. D-Cap Mode, Fixed 5-V / 6-A, 3.3-V/6-A, RDS(on) Sensing
7.4.2.1 D-Cap Mode Operation
A buck converter system using D-CAP mode can be simplified as shown in Figure 31.
Figure 31. Linearizing the Modulator
The VO voltage is compare with internal reference voltage after divider resistors (Internal resistor mode. For
adjustable mode, the comparison is directly at VFB). The PWM comparator determines the timing to turn on top
MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on
cycle (or the end of off cycle) substantially constant. The DC output voltage may have line regulation due to
ripple amplitude that slightly increases as the input voltage increase.
For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.
f
1
f0 +
v SW
3
2p ESR CO
(19)
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Device Functional Modes (continued)
As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP mode is determined by
the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several
100 μF and ESR in range of 10 mΩ. These produce an f0 in the order of 100 kHz or less and the loop is stable.
However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode.
Although D-CAP mode provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient
amount of feedback signal needs to be provided by external circuit to reduce jitter level. The required signal level
is approximately 15 mV at comparing point, either the internal or external VFB voltages. The output capacitor’s
ESR should meet this requirement.
The external components selection is much simple in D-CAP mode.
1. Choose inductor based on frequency and acceptable ripple current.
2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are
recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in
Equation 20.
V
0.015
ESR + OUT
I RIPPLE
(20)
7.5 Programming
The TPS51120 has varieties of configurations choice. It is important to tailor appropriately with regard to the
system design requirements. Table below shows programming table for the control scheme selection, frequency
selection, output voltage selection and skip selection. Faults-off disables UVP, OVP and UVLO. This is mainly
intended for debugging purpose. Enable states and possible connections for the LDO’s EN3, EN5 pins and
SMPS’s EN1, EN2 pins are also shown.
Table 5. Function Programming Table
PIN
GND
VREF2
FLOAT
V5FILT
COMP
N/A
N/A
Current Mode
(apply R-C network)
D-CAP Mode
TONSEL (CH1/CH2) [kHz]
380 / 580
280 / 430
220 / 330
180 / 270
VFB1
Adjustable output (connect to the resistor divider)
5V fixed output
VFB2
Adjustable output (connect to the resistor divider)
3.3 V fixed output
SKIPSEL
AUTO-SKIP
AUTO-SKIP (FAULTS OFF)
PWM
PWM
EN1, EN2
Switcher Off
Not used
Switcher on
Switcher on
EN3, EN5
LDO Off
Not used
LDO on
LDO on (EN3 only)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51120 is typically used as a dual-synchronous buck controller, which convert an input voltage ranging
from 4.5V to 28 V, to output voltage ranging 1V to 5.5 V, targeted for notebook I/O and low voltage system bus
supply solutions.
8.2 Typical Application
V5FILT
C31
1 nF
2
1
Q3
IRF7821
VREF2
VFB1
COMP1
VO1
SKIPSEL
32
TONSEL 31
P_GOOD1
GND
VBAT
PGOOD1 30
TPS51120RHB
(QFN−32)
12 EN2
C21
0.1 µF
R11
100 kΩ
EN1 29
EN_1
13 VBST2
VBST1 28
C11
0.1 µF
14 DRVH2
DRVH1 27
C10
20 µF
Q1
IRF7821
L1
4.7 µH
+
+
PowerPAD
VIN
CS1
PGND1
17
VREG5
DRVL2
V5FILT
16
VREG3
Q4
IRF7832
LL1 26
CS2
C2A
150 µF
15 LL2
PGND2
C2B
150 µF
VO2_GND
3
11 PGOOD2
EN_2
VO2
3.3V/6A
4
10 EN3
VBAT
L2
2.2 µH
5
EN5
EN_LDO3
C10
20 µF
6
GND
9
7
VFB2
EN_LDO5
P_GOOD2
8
COMP2
GND
VO2
R21
100 kΩ
18
19
20
21
22
23
24
Q2
IRF7832
DRVL1
C1A
150 µF
VO1
5V/6A
C1B
150 µF
25
−
VO1_GND
−
PGND1
R22
3.3 kΩ
PGND2
R50
5.1Ω
C30
10 µF
C51
1 µF
R12
3.6 kΩ
C50
10 µF
VBAT
C30
NA
Figure 32. D-Cap Mode, Fixed 5-V / 6-A, 3.3-V/6-A, RDS(on) Sensing
8.2.1 Design Requirements
Table 6. Design Parameters
28
DESIGN PARAMETER
VALUE
Input Voltage Range
4.5 V to 28 V
Channel 1 Output Voltage
5V
Channel 1 Output Current
6A
Channel 2 Output Voltage
3.3 V
Channel 2 Output Current
6A
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8.2.2 Detailed Design Procedure
1. Determine output voltage. Since 5 V and 3.3 V is the default fixed output voltage, tie VFB1 and VFB2 to
V5FILT to choose the internal feedback resistor divider.
2. Choose control mode. Tie COMP1 and COMP2 to V5FILT to choose D-CAP control mode.
3. Choose switching frequency. Tie TONSEL to VREF2, choose 280kHz/430kHz for channel1 and channel2
respectively.
4. Choose the inductor. To make the inductor ripple current at ½ of maximum output current, calculate
inductance according to Equation 12 as below:
2
(28V - 5V) ´ 5V
´
= 4.9uH
L1 =
6A ´ 280kHz
28V
(21)
2
(28V - 3.3V) ´ 3.3V
´
= 2.2uH
L2 =
6A ´ 430kHz
28V
(22)
4.7-uH and 2.2-uH inductor is chosen for channel1 and channel2 respectively. Check inductor specification,
make sure the saturation current is higher than peak inductor current in this application with enough room.
5. Choose the output capacitor. To get an acceptable jitter level, approximately 15mV ripple at comparing
point is needed. Refer to Equation 20. This require the minimum ESR of output capacitors for channel1 and
channel2 is:
ESR1 = (Vout1 × 0.015) ÷ Iripple1 = (5 V × 0.015) ÷ 3 A = 25 mΩ
ESR2 = (Vout2 × 0.015) ÷ Iripple2 = (3.3 V × 0.015) ÷ 3 A = 16.5 mΩ
(23)
(24)
Choose 2pcs 150-uF/50-mΩ SP-CAP in parallel, the equivalent capacitance and ESR is 300 uF and 25 mΩ,
meet above requirement.
0dB frequency f0 calculated as below:
1
f0 =
= 21kHz
2p ´ 25mW ´ 300uF
(25)
F0 is much less than 1/3 of the switching frequency, loop should be stable.
8.2.3 Application Curves
VOUT2 (100 mV/div)
VOUT1 (100 mV/div)
IIND (5 A/div)
IIND (5 A/div)
IOUT2 (5 A/div)
IOUT1 (5 A/div)
t − Time − 20 µs/div
t − Time − 20 µs/div
Figure 33. 5-V Load Transient Response
Figure 34. 3.3-V Load Transient Response
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EN1 (5 V/div)
EN2 (5 V/div)
VO1 (2 V/div)
VO2 (2 V/div)
PGOOD1 (5 V/div)
PGOOD2 (5 V/div)
t − Time − 1 ms/div
t − Time − 1 ms/div
Figure 35. 5-V Startup Waveforms
Figure 36. 3.3-V Startup Waveforms
VREG5 (200 mV/div)
VREG3 (200 mV/div)
VO2 (200 mV/div)
VO1 (200 mV/div)
t − Time − 1 ms/div
t − Time − 1 ms/div
Figure 37. 5-V Switchover Waveforms
Figure 38. 3.3-V Switchover Waveforms
EN1 (5 V/div)
EN2 (5 V/div)
VO1 (5 V/div)
VO2 (5 V/div)
PGOOD1 (5 V/div)
PGOOD2 (5 V/div)
DRVL1 (5 V/div)
DRVL2 (5 V/div)
t − Time − 1 ms/div
t − Time − 1 ms/div
Figure 39. 5-V Soft-Stop Waveforms
30
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Figure 40. 3.3-V Soft-Stop Waveforms
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9 Power Supply Recommendations
The TPS51120 is designed to operate from input supply voltage in the range of 4.5 V to 28 V. Make sure power
supply voltage in this range.
10 Layout
10.1 Layout Guidelines
Certain points must be considered before starting a layout work using the TPS51120.
• Connect RC low-pass filter from VREG5 to V5FILT, 1 μF and 5.1 Ω are recommended. Place the filter
capacitor close to the device, within 12 mm (0.5 inches) if possible.
• VREG5 and VREG3 require at least 4.7 μF, VREF2 requires a 1-nF ceramic bypass capacitor which should
be placed close to the device and traces should be no longer than 10 mm.
• Connect the overcurrent setting resistors from CSx to V5FILT (NOT VREG5) and close to the device, right
next to the device if possible. The trace from CSx to V5FILT should avoid coupling to high-voltage switching
node.
• In the case of using adjustable output voltage with an external resistor divider, the discharge path (VOx)
should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace, and
use 1.5 mm or wider trace with no loops. Make the feedback current setting resistor (the resistor between
VFBx to GND) is tied close to the device’s GND. Place on the component side and avoid vias between this
resistor and the device.
• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace.
• All sensitive analog traces and components such as VOx, COMPx, VFBx, VREF2, GND, ENx, PGOODx,
CSx, V5FILT, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx,
DRVLx or DRVHx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace
from power traces and components.
• Gather ground terminal of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as
possible. GND (signal ground) and PGNDx (power ground) should be connected strongly together near the
device. PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Three by three or more vias with a 0.33-mm (13mils) diameter connected from the thermal land
to the internal ground plane should be used to help dissipation. Do NOT connect PGNDx to this thermal land
underneath the package.
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10.2 Layout Example
VOUT1
OUTPUT
INDUCTOR
OUTPUT
CAPACITOR
LL1
LL1
DRVL1
DRVH1
EN1
VBST1
D
TONSEL
D
PGOOD1
D
SKIPSEL
D
G
D
S
D
G
S
D
S
PGND1
COMP1
CS1
VFB1
VIN
SGND
GND
V5FILT
VFB2
VREG3
VIN
INPUT
CAPACITOR
GND
VREG5
VREF2
S
D
S
VO1
S
GND
ROUTE ON
OPPOSITE
SIDE
VIN
SGND
COMP2
DRVL2
LL2
DRVH2
VBST2
PGND2
EN2
EN5
V5FILT
EN3
VO2
PGOOD2
CS2
S
D
S
D
D
S
D
D
G
D
S
D
S
D
S
CONNECTED
TO POWER
GND ON
INTERNAL OR
BOTTOM
LAYER
GND
G
LL2
OUTPUT
CAPACITOR
VOUT2
OUTPUT
INDUCTOR
VIA to Ground Plane
Figure 41. Layout Example
32
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11 Device and Documentation Support
11.1 Trademarks
D-CAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51120RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51120
TPS51120RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51120
TPS51120RHBTG4
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51120
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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