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Table of Contents
User’s Guide
TPS51125A Buck Controller Evaluation Module User's
Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Performance Specification Summary................................................................................................................................... 2
3 Schematic................................................................................................................................................................................3
4 Test Setup and Results.......................................................................................................................................................... 4
5 Configuration.......................................................................................................................................................................... 5
6 Physical Layouts.................................................................................................................................................................... 6
7 List of Materials.......................................................................................................................................................................8
8 References.............................................................................................................................................................................. 9
9 Revision History......................................................................................................................................................................9
Trademarks
Out-of-Audio™ is a trademark of Texas Instruments.
D-CAP™ is a trademark of to.
is a trademark of TI.
All trademarks are the property of their respective owners.
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1
Introduction
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1 Introduction
The TPS51125A is a cost effective, dual-synchronous buck controller targeted for notebook system power
supply solutions. It provides 5-V and 3.3-V LDOs and requires few external components. The 270-kHz VCLK
output can be used to drive an external charge pump, generating gate drive voltage for the load switches without
reducing the efficiency of the main converter. The TPS51125A supports high-efficiency, fast transient response
and provides a combined power-good signal. Out-of-Audio™ mode light-load operation enables low acoustic
noise at much higher efficiency than conventional forced PWM operation. Adaptive on-time D-CAP™ control
provides convenient and efficient operation. The part operates with supply input voltages ranging from 5.5 V to
28 V and supports output voltages from 2 V to 5.5 V.
The TPS51125AEVM evaluation module is a high-efficiency, dual synchronous buck converter providing 5 V at
8 A and 3.3 V at 8 A from 8-V to 25-V input.
2 Performance Specification Summary
Table 2-1 gives the EVM performance specifications and qualifications.
Table 2-1. Performance Specification Summary
SPECIFICATION
VIN
Input voltage range
TEST CONDITIONS
Voltage applied to VBAT
MIN
TYP
8
MAX
25
UNITS
V
CHANNEL1
VOUT
Output voltage
f
Operating frequency
VTONSEL = VVREF, VVIN = 12 V, IOUT = 6 A
5
IOUT
Output current
8 V ≤ VVIN ≤ 25 V
IOC
Overcurrent limit
VVIN = 12 V
245
8
10
V
kHz
A
CHANNEL2
2
VOUT
Output voltage
f
Operating frequency
VTONSEL = VVREF, VVIN = 12 V, IOUT = 6 A
IOUT
Output current
8 V ≤ VVIN ≤ 25 V
IOC
Overcurrent limit
VVIN = 12 V
TPS51125A Buck Controller Evaluation Module User's Guide
3.3
V
305
kHz
8
10
A
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Schematic
3 Schematic
Figure 3-1. TPS51125A-EVM Schematic Diagram
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3
Test Setup and Results
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4 Test Setup and Results
4.1 Test Setup
Connect the test equipment and TPS51125AEVM board as shown in Figure 4-1.
DMM4
_
+
DMM1
_
+
Oscilloscope
CH1
1MW
TP1
CN1
+
Electronic
Load1
+
_ DMM3
VO1
_
+
VO1_GND
VBAT
_
_
Electronic
Load2
VBAT_GND
VO2_GND
CN2
+
VO2
12V/10A
Power Supply
HPA557
TPS51125AEVM
_
+
DMM2
CH2
Oscilloscope
Figure 4-1. Equipment Setup for TPS51125AEVM Board
4.2 Test Procedure
1. Ensure the switches SW1 (ENTRIP1), SW2 (ENTRIP2), and SW3 (EN0) are in the “OFF” position.
2. Ensure the shunt jumper for JP1 is set to 5-pin to 6-pin (Med1), and the shunt jumper for JP2 is set 3-pin to
4-pin (Auto-skip).
3. Apply appropriate VBAT voltage to VBAT and VBAT_GND terminals.
4. Turn on SW3 (EN0), and both VREG5 (5V-LDO) and VREG3 (3.3V-LDO) start up.
5. When SW3 stays on, VREF (2V-REF) is enabled.
6. When SW3 stays on and turn on SW1 (ENTRIP1), CH1-output starts up.
7. When SW3 stays on and turn on SW2 (ENTRIP2), CH2-output starts up.
4.3 Start-Up Performance
Figure 4-2. 5-V Start-Up Waveforms
4
TPS51125A Buck Controller Evaluation Module User's Guide
Figure 4-3. 3.3-V Start-Up Waveforms
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Configuration
Figure 4-5. 3.3-V Load Transient Response
Figure 4-4. 5-V Load Transient Response
5 Configuration
This EVM can be set at a configuration of the user's choice. Please refer to the following specific configuration
setting sections.
5.1 Switching Frequency Selection
The switching frequency can be set by the TONSEL pin using JP1 on the EVM. The default setting is 245 kHz
for CH1 and 305 kHz for CH2.
Table 5-1. Switching Frequency Selection
TONSEL
CONNECTION
SWITCHING FREQUENCY (kHz)
CH1
CH2
GND (SLOW)
200
250
VREF (MED1)
245
305
VREG3 (MED2)
300
375
VREG5 (FAST)
365
460
5.2 Operation Mode Selection
Operation mode can be set by the SKIPSEL pin using JP2 on the EVM. The default setting on the EVM is
auto-skip mode.
Table 5-2. Operation Mode Selection
SKIPSEL CONNECTION
OPERATION MODE
GND
PWM only
VREF
Auto skip
VREG5
Out-of-Audio™
5.3 VCLK ON/OFF Selection
The VCLK drive for the charge-pump can be disabled by pulling down EN0 with 620 kΩ of resistance using S1
on the EVM.
Table 5-3. VLCK Control
END CONNECTION
VCLK
OPEN
ENABLED
Pull down to GND with 620 kΩ
DISABLED
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5
Physical Layouts
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6 Physical Layouts
This section provides the board layout and assembly drawings for the EVM, that include the top layer (Figure
6-1), the bottom layer (Figure 6-2), and inner layer views (Figure 6-3 and Figure 6-4) of the EVM.
Figure 6-1. Top Layer Routing
Figure 6-2. Bottom Layer Routing
6
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Physical Layouts
Figure 6-3. Inner Layer 1
Figure 6-4. Inner Layer 2
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7
List of Materials
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7 List of Materials
List of materials for the TPS51125A-EVM.
Table 7-1. TPS51125A Bill of Materials
RERERENCE
DESIGNATOR
QTY
C1, C2, C3, C4, C13,
C23
6
Capacitor, Ceramic, 0.1 µF, 50 V, X5R, 10%
0603
muRata
GRM188B31H104K
C5
1
Capacitor, Ceramic, 1 μF, 25 V, X5R, 10%
0805
TDK
C2012X7R1E105K
C6, C7, C24, C25
4
Capacitor, Ceramic, 10 μF, 25 V, BJ, M
1210
Taiyo Yuden
TMK325BJ106MM
C8, C9, C14, C16,
C18, C26
0
Capacitor
0603
Any
Any
C10, C21
0
Capacitor
7343 (D)
Any
Any
C11, C22
2
Capacitor, POS, 330 μF, 6.3 V, 25 mΩ, 20%
7343 (D)
SANYO
6TPE330ML
C12, C20
0
Capacitor
0805
Any
Any
C15, C17
2
Capacitor, Ceramic, 10 μF, 6.3 V, X5R, 10%
0805
TDK
C2012X5R0J106K
C19
1
Capacitor, Ceramic, 0.22 µF, 16 V, B, 10%
0603
muRata
GRM188B11C224K
CN1, CN2
2
Adaptor, 3.5-mm probe clip ( or 131-5031-00)
0.2
Tektronix
131-4244-00
D1
1
Diode, Schottky Barrier Array, 40 mA, 40 V
SOT363
Diodes
BAS40DW-04
D2, D5
0
Diode, Schottky, 0.5 A, 30 V
SOD123
Any
Any
D3, D4
2
Diode, Schottky, 3 A, 20 V
SMA
Rohm
RSX501LA-20 or
RSX501L-20
JP1
1
Header, 2×4-pin, 100 mil spacing (36-pin strip)
0.20 × 0.40 in
Sullins
PTC36DAAN
JP2
1
Header, 2×3-pin, 100 mil spacing (36-pin strip)
0.20 × 0.30 in
Sullins
PTC36DAAN
L1, L2
2
Inductor, high-current, 5.9 mΩ, 14 A, SMT
0.425 × 0.45 in
Toko
FDA1055-3R3M
Q1, Q3
2
MOSFET, N-channel, 30 V, 13.6 A, 9.1 mΩ
SO8
IR
IRF7821
Q2, Q4
2
MOSFET, N-channel, 30 V, 10 A, 12 mΩ
SO8
Fairchild
FDS6690AS
R1, R3, R8, R11,
R13, R14
6
Resistor, Chip, 0 Ω, 1/16 W, 1%
0603
Std
Std
R2, R16
2
Resistor, Chip, 5.1 Ω, 1/16W, 1%
0603
Std
Std
R4
1
Resistor, Chip, 30 kΩ, 1/16W, 1%
0603
Std
Std
R5
1
Resistor, Chip, 100 kΩ, 1/16W, 1%
0603
Std
Std
R6, R10
2
Resistor, Chip, 130 kΩ, 1/16W, 1%
0603
Std
Std
R7, R9
2
Resistor, Chip, 20 kΩ, 1/16W, 1%
0603
R12
1
Resistor, Chip, 13 kΩ, 1/16W, 1%
0603
Std
Std
R15
1
Resistor, Chip, 620 Ω, 1/16W, 1%
0603
Std
Std
S1
1
Header, 2-pin, 100 mil spacing, (36-pin strip)
0.2 × 0.2 in
Sullins
PTC36SAAN
SW1, SW2
2
Switch, ON-ON mini toggle
0.28 × 0.18 in
Nikkai
G-12AP
TP1, TP2, TP3, TP4,
TP5, TP6, TP7
7
Test point, yellow, through-hole
U1
1
Dual synchronous step-down controller with
OOA operation and 100-mA LDO
VBAT, VBAT_GND,
VO1, VO1_GND,
VO2, VO2_GND
6
Pin, wiring terminal
1
Printed circuit board
3
Shunt, 2POs, gold
4
Standoff M/F hex 4-40 nylon
4
8
DESCRIPTION
Nut hex 4-40 nylon
TPS51125A Buck Controller Evaluation Module User's Guide
SIZE
MFR
Std
0.125 × 0.125 in Keystone
QFN-24
0.12(D) × 0.4 in
0.625 in
5014
TI
TPS51125ARGE
Mill Max
3138-2-00-15-00-00-080
3.5 × 2.7 × 0.062
Any
in
0.100 × 0.200
inch
PART NUMBER
TPS51125AEVM
Molex
15-29-1025
Keystone
4803
Building
Fasteners
NY HN 440
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References
8 References
Texas Instruments, TPS51125A Dual-Synchronous Buck Controller data sheet
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2010) to Revision A (January 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
• Updated the user's guide title............................................................................................................................. 2
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