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TPS51206
SLUSAH1E – MAY 2011 – REVISED JULY 2018
TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered
Reference for DDR2, DDR3, DDR3L, and DDR4
1 Features
3 Description
•
The TPS51206 device is a sink and source double
date rate (DDR) termination regulator with VTTREF
buffered reference output. It is specifically designed
for low-input voltage, low-cost, low-external
component count systems where space is a key
consideration. The device maintains fast transient
response and only requires 1 × 10-µF of ceramic
output capacitance. The device supports a remote
sensing function and all power requirements for
DDR2, DDR3 and Low-Power DDR3 (DDR3L), and
DDR4 VTT bus. The VTT current capability is ±2-A
peak. The device supports all of the DDR power
states, putting VTT to High-Z in S3 state (suspend to
RAM) and discharging VTT and VTTREF in S4 or S5
state (suspend to disk).
1
•
•
•
•
•
•
Supply Input Voltage: Supports 3.3-V Rail and 5-V
Rail
VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
VTT Termination Regulator
– Output Voltage Range: 0.5 V to 0.9 V
– 2-A Peak Sink and Source Current
– Requires Only 10-μF MLCC Output Capacitor
– ±20 mV Accuracy
VTTREF Buffered Reference
– VDDQ/2 ± 1% Accuracy
– 10-mA Sink and Source Current
Supports High-Z in S3 and Soft-Stop in S4 and S5
with S3 and S5 Inputs
Overtemperature Protection
10-Pin, 2 mm × 2 mm SON (DSQ) Package
The TPS51206 device is available in 10-Pin, 2 mm ×
2 mm SON (DSQ) PowerPAD™ package and
specified from –40°C to 105°C.
Device Information(1)
2 Applications
•
•
•
PART NUMBER
DDR2, DDR3, DDR3L, and DDR4 Memory Power
Supplies
SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination
Telecom and Datacom, GSM Base Station, LCDTV and PDP-TV, Copier and Printer, Set-top Box
TPS51206
PACKAGE
BODY SIZE (NOM)
WSON (10)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application
TPS51206
VDDQ
1
VDDQSNS
2
VLDOIN
S3_SLP
7
S3
S5_SLP
9
S5
5 V or 3.3 V
Supply
VTT
3
VTTSNS
5
PGND
4
VTTREF
6
GND
8
VTT
VTTREF
10 VDD
PowerPad
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51206
SLUSAH1E – MAY 2011 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
10.3 Thermal Considerations ....................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2018) to Revision E
Page
•
Changed "specified from –40°C to 85°C" to "specified from –40°C to 105°C" in Description .............................................. 1
•
Changed maximum operating temperature from "85 °C" to "105 °C" in Recommended Operating Conditions table ........... 4
Changes from Revision C (August 2016) to Revision D
•
Page
Added VTTREF tolerance at 100 μA condition ..................................................................................................................... 5
Changes from Revision B (December 2014) to Revision C
Page
•
Added references to DDR4 compatibility .............................................................................................................................. 1
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 19
•
Added Community Resources section ................................................................................................................................. 19
Changes from Revision A (October 2013) to Revision B
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (MAY 2011) to Revision A
•
2
Page
Page
Added minimum and maximum values to the wake up condition of the VDD UVLO threshold voltage specification ........... 5
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SLUSAH1E – MAY 2011 – REVISED JULY 2018
5 Pin Configuration and Functions
DSQ Package
10-Pin WSON
Top View
VDD
VDDQSNS
1
10
VLDOIN
2
9
S5
VTT
3
8
GND
PGND
4
7
S3
VTTSNS
5
6
VTTREF
Thermal Pad
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
8
–
Signal ground
PGND
4
–
Power GND for VTT LDO
S3
7
I
S3 signal input
S5
9
I
S5 signal input
VDD
10
I
Device power supply input (3.3 V or 5 V)
VDDQSNS
1
I
VDDQ sense input, reference input for VTTREF
VLDOIN
2
I
Power supply input for VTT/ VTTREF
VTT
3
O
Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability. No maximum
limit for VTT output capacitance.
VTTREF
6
O
VTTREF buffered reference output. Connect to MLCC between 0.22-µF and 1-µF for stability. The
VTTREF pin can not be open.
VTTSNS
5
I
VTT LDO voltage sense input
Thermal Pad
—
Solder to the ground plane for increased thermal performance.
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TPS51206
SLUSAH1E – MAY 2011 – REVISED JULY 2018
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Input voltage
(2)
Output voltage
(2)
MIN
MAX
UNIT
VDD, S3, S5
–0.3
7
V
VLDOIN, VTTSNS, VDDQSNS
–0.3
3.6
PGND
–0.3
0.3
VTT, VTTREF
V
–0.3
3.6
Operation junction temperature, TJ
-40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings(1) may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
Supply voltage
VDD
Input voltage range (1)
Output voltage
range (1)
MAX
UNIT
6.5
S3, S5
–0.1
6.5
VLDOIN, VTTSNS, VDDQSNS
–0.1
3.5
PGND
–0.1
0.1
VTT, VTTREF
–0.1
3.5
V
–40
105
°C
Operating free-air temperature, TA
(1)
NOM
3.1
V
V
All voltage values are with respect to the network ground terminal unless otherwise noted.
6.4 Thermal Information
TPS51206
THERMAL METRIC (1)
DSQ (WSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
70.3
RθJC(top)
Junction-to-case (top) thermal resistance
46.3
RθJB
Junction-to-board thermal resistance
33.8
ψJT
Junction-to-top characterization parameter
2.9
ψJB
Junction-to-board characterization parameter
33.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
16.3
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.5 Electrical Characteristics
Over operating free-air temperature range, VVDD = 5 V, VLDOIN is connected to VDDQSNS, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVDD(S0)
VDD supply current, in S0
TA = 25°C, No load, VS3 = VS5 = 5 V,
VVDDQSNS = 1.8 V
IVDD(S3)
VDD supply current, in S3
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
VVDDQSNS = 1.8 V
IVDDSDN
VDD shutdown current, in S4 and S5
TA = 25°C, No load, VS3 = VS5 = 0 V,
VVDDQSNS = 1.8 V
1
μA
IVLDOIN(S0)
VLDOIN supply current, in S0
TA = 25°C, No load, VS3 = VS5 = 5 V,
VLDION = 1.8 V
5
μA
IVLDOIN(s3)
VLDOIN supply current, in S3
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
VLDION = 1.8 V
5
μA
IVLDOINSDN
VLDOIN shutdown current, in S4 and
S5
TA = 25°C, No load, VS3 = VS5 = 0 V,
VLDION = 1.8 V
5
μA
170
μA
80
μA
VTTREF OUTPUT
VVTTREF
VVTTREFTOL
Output voltage
Output voltage tolerance to VVDDQSNS
VVDDQSNS/2
V
|IVTTREF|≤ 10 mA, 1.5 V ≤ VVDDQSNS ≤ 1.8 V
49%
51%
|IVTTREF|≤ 10 mA, 1.2 V ≤ VVDDQSNS < 1.5 V
48.75%
51.25%
|IVTTREF|≤ 100 μA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V
49%
51%
IVTTREFSRC
Source current
VVDDQSNS = 1.8 V, VVTTREF = 0 V
10
IVTTREFSNK
Sink current
VVDDQSNS = 0 V, VVTTREF = 1.8 V
10
IVTTREFDIS
VTTREF Discharge current
TA = 25°C, VS3 = VS5 = 0V, VVTTREF = 0.5 V
mA
mA
1.3
mA
VTT OUTPUT
VVTT
Output voltage
VVTTTOL
Output voltage tolerance to
VVDDQSNS/2
VVDDQSNS/2
V
|IVTT|≤ 10 mA, 1.4 V ≤ VVDDQSNS ≤ 1.8 V
–20
20
|IVTT|< 1 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V (1)
–30
30
|IVTT| < 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V (1)
–40
40
|IVTT|≤ 10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.4 V
–20
20
|IVTT| < 1 A, 1.2 V ≤ VVDDQSNS ≤ 1.4 V (1)
–30
30
|IVTT|< 1.5 A, 1.2 V ≤ VVDDQSNS < 1.4 V (1)
–40
40
mV
IVTTOCLSRC
Source current limit
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V
2
A
IVTTOCLSNK
Sink current limit
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 1.1 V
2
A
IVTTLK
Leakage current
TA = 25°C , VS3 = 0 V, VS5 = 5 V,
VVTT = VVTTREF
IVTTSNSBIAS
VTTSNS input bias current
VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF
IVTTSNSLK
VTTSNS leakage current
VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF
VTT Discharge current
TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
VVTT = 0.5 V
VDDQSNS input current
VVDDQSNS = 1.8 V
IVTTDIS
5
μA
–0.1
0.1
μA
–0.1
0.1
μA
7
mA
30
μA
VDDQ INPUT
IVDDQSNS
UVLO/LOGIC THRESHOLD
VVDDUV
VDD UVLO threshold voltage
VLL
S3 and S5 low-level voltage
VLH
S3 and S5 high-level voltage
VLHYST
S3 and S5 hysteresis voltage
ILHLK
S3 and S5 input leak current
Wake up
2.67
Hysteresis
2.90
3.00
0.2
0.5
1.8
V
V
V
0.3
–1
V
1
μA
OVER-TEMPERATURE PROTECTION
TOTP
(1)
Over temperature protection
Shutdown temperature (1)
Hysteresis (1)
150
10
°C
Ensured by design. Not production tested.
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6.6 Typical Characteristics
300
5
VDD Shutdown Current (µA)
VDD Supply Current (µA)
250
200
150
100
50
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
VLDOIN Shutdown Current (µA)
VLDOIN Supply Current (µA)
3
2
1
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
95
110 125
3
2
1
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
Figure 4. VLDOIN Shutdown Current vs. Junction
Temperature
0.920
0.770
TA = −40°C
TA = 25°C
TA = 85°C
0.915
0.910
0.905
0.900
0.895
0.890
VVDDQSNS = 1.8 V
VVDD = 5 V
−8
−6
−4
−2
0
2
4
VTTREF Current (mA)
0.760
0.755
0.750
0.745
0.740
0.735
6
8
Figure 5. VTTREF Load Regulation (0.9 V)
TA = −40°C
TA = 25°C
TA = 85°C
0.765
VTTREF Voltage (V)
VTTREF Voltage (V)
5
20 35 50 65 80
Junction Temperature (°C)
4
0
−40 −25 −10
110 125
Figure 3. VLDOIN Supply Current vs. Junction Temperature
6
1
5
4
0.880
−10
2
Figure 2. VDD Shutdown Current vs. Junction Temperature
5
0.885
3
0
−40 −25 −10
110 125
Figure 1. VDD Supply Current vs. Junction Temperature
4
10
VVDDQSNS = 1.5 V
VVDD = 5 V
0.730
−10
−8
−6
−4
−2
0
2
4
VTTREF Current (mA)
6
8
10
Figure 6. VTTREF Load Regulation (0.75 V)
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Typical Characteristics (continued)
0.690
0.615
TA = −40°C
TA = 25°C
TA = 85°C
0.610
VTTREF Voltage (V)
VTTREF Voltage (V)
0.685
0.680
0.675
0.670
0.665
−8
−6
0.605
0.600
0.595
0.590
VVDDQSNS = 1.35 V
VVDD = 5 V
0.660
−10
−4
−2
0
2
4
VTTREF Current (mA)
6
8
TA = −40°C
TA = 25°C
TA = 85°C
VVDDQSNS = 1.2 V
VVDD = 5 V
0.585
−10
10
−8
Figure 7. VTTREF Load Regulation (0.675 V)
8
10
TA = −40°C
TA = 25°C
TA = 85°C
0.790
0.780
0.920
VTT Voltage (V)
VTT Voltage (V)
0.930
0.910
0.900
0.890
0.880
0.870
0.770
0.760
0.750
0.740
0.730
0.720
VVDDQSNS = 1.8 V
VVDD = 5 V
0.850
−2.0
−1.5
−1.0
0.710
−0.5
0.0
0.5
VTT Current (A)
1.0
1.5
VVDDQSNS = 1.5 V
VVDD = 5 V
0.700
−2.0
2.0
Figure 9. VTT Load Regulation (0.9 V)
−1.5
−1.0
−0.5
0.0
0.5
VTT Current (A)
1.0
1.5
2.0
Figure 10. VTT Load Regulation (0.75 V)
0.725
0.650
TA = −40°C
TA = 25°C
TA = 85°C
0.715
0.705
TA = −40°C
TA = 25°C
TA = 85°C
0.640
0.630
0.695
VTT Voltage (V)
VTT Voltage (V)
6
0.800
TA = −40°C
TA = 25°C
TA = 85°C
0.940
0.685
0.675
0.665
0.655
0.645
0.635
−4
−2
0
2
4
VTTREF Current (mA)
Figure 8. VTTREF Load Regulation (0.6 V)
0.950
0.860
−6
0.620
0.610
0.600
0.590
0.580
0.570
VVDDQSNS = 1.35 V
VVDD = 5 V
0.625
−1.5
−1.0
−0.5
0.0
0.5
VTT Current (A)
0.560
1.0
1.5
VVDDQSNS = 1.2 V
VVDD = 5 V
0.550
−1.5
Figure 11. VTT Load Regulation (0.675 V)
−1.0
−0.5
0.0
0.5
VTT Current (A)
1.0
Figure 12. VTT Load Regulation (0.6 V)
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Typical Characteristics (continued)
VVTTREF(10 mV/div) 0.9 V offset
VVTTREF(10 mV/div) 0.75 V offset
VVTT
VVTT
(20 mV/div)
0.9 V offset
(20 mV/div)
0.75 V offset
VVDDQSNS
VVDDQSNS
(50 mV/div)
1.8 V offset
(50 mV/div)
1.5 V offset
IVTT
(2 A/div)
IVTT
(2 A/div)
Time (200 ms/div)
Time (200 ms/div)
Figure 14. VTT Load Transient Response (0.75 V)
Figure 13. VTT Load Transient Response (0.9 V)
VVTTREF(10 mV/div) 0.6 V offset
VVTTREF(10 mV/div) 0.675 V offset
VVTT
VVTT
(20 mV/div)
0.675 V offset
(20 mV/div)
0.6 V offset
VVDDQSNS
VVDDQSNS
(50 mV/div)
1.35 V offset
(50 mV/div)
1.2 V offset
IVTT
(2 A/div)
IVTT
(2 A/div)
Time (200 ms/div)
Time (200 ms/div)
80
180
60
135
60
135
40
90
40
90
20
45
20
45
0
0
0
0
−20
−45
−40
−60
−80
1000
Sink: −1 A
VVDD = 5 V
VVDDQSNS = 1.5 V
Gain
Phase
10000
100000
Frequency (Hz)
1000000
−20
−90
−40
−135
−60
−180
10000000
Figure 17. VTT (Sink: -1 A) Bode Plot (0.75 V)
8
Gain (dB)
180
Phase (°)
Gain (dB)
Figure 15. VTT Load Transient Response (0.675 V)
80
−45
Phase (°)
Figure 16. VTT Load Transient Response (0.6 V)
−90
Source: +1 A
VVDD = 5 V
VVDDQSNS = 1.5 V
Gain
Phase
−80
1000
10000
100000
Frequency (Hz)
1000000
−135
−180
10000000
Figure 18. VTT (Source: +1 A) Bode Plot (0.75 V)
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Typical Characteristics (continued)
IVTTREF= 0 A
S5: Low to High
VVTTREF(500 mV/div)
VVTTREF(500 mV/div)
IVTTREF= 0 A
VVTT (500 mV/div)
IVTT = 0 A
S3: Low to High
VVTT (500 mV/div)
VS5 (5 V/div)
VS5 (5 V/div)
VS3 (5 V/div)
VS3 (5 V/div)
Time (40 ms/div)
Time (1 ms/div)
Figure 19. Start-Up Waveforms (S5: Low to High)
Figure 20. Start-Up Waveforms (S3: Low to High)
0.30
IVTTREF= 0 A
IVTT = 0 A
S3/S5: High to Low
VVTT (500 mV/div)
VS5 (5 V/div)
VS3 (5 V/div)
0.25
VTT Dropout Voltage (V)
VVTTREF (500 mV/div)
TA = 25°C
VVDD = 5 V
0.20
0.15
0.10
VOUT = 0.900 V
VOUT = 0.750 V
VOUT = 0.675 V
VOUT = 0.600 V
0.05
0.00
0.0
Time (2 s/div)
Figure 21. Shutdown Waveforms (S3/ S5: High to Low)
0.5
1.0
VTT Current (A)
1.5
Figure 22. VTT Dropout Voltage
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7 Detailed Description
7.1 Overview
The TPS51206 device is a sink or source double date rate (DDR) termination regulator with VTTREF buffered
reference output.
7.2 Functional Block Diagram
VLDOIN
2
VDDQSNS
1
+
6
VTTREF
3
VTT
4
PGND
+
GND
GND
8
VTTREF Disharge
OTP-OK
GND
VTT Disharge
OTP
GND
VDD 10
+
EN-VTTREF
2.9V/2.7 V
S5
+
9
+
EN-VTT
S3
7
VTTSNS
5
+
TPS51206
GND
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7.3 Feature Description
7.3.1 VTT Sink and Source Regulator
The TPS51206 device is a sink or source tracking termination regulator specifically designed for low input
voltage, low cost, and low external component count systems where space is a key application parameter. The
device integrates a high-performance, low-dropout (LDO) linear regulator (VTT) that has ultimate fast response to
track ½ VDDQSNS within 40 mV at all conditions, and its current capability is 2 A for both sink and source
directions. A 10-µF (or greater) ceramic capacitor(s) need to be attached close to the VTT terminal for stable
operation. A grade of X5R or better is recommended. To achieve tight regulation with minimum effect of trace
resistance, the remote sensing terminal, VTTSNS, should be connected to the positive terminal of the output
capacitor(s) as a separate trace from the high current path from the VTT pin.
The device has a dedicated pin, VLDOIN, for VTT power supply to minimize the LDO power dissipation on user
application. The minimum VLDOIN voltage is 0.4 V above the ½ VDDQSNS voltage.
7.3.2 VTTREF
The VTTREF pin includes 10 mA of sink or source current capability, and tracks ½ of VDDQSNS with ±1%
accuracy. The VTTREF pin can not be open. A 0.22-µF ceramic capacitor needs to be attached close to the
VTTREF terminal for stable operation; X5R or better grade is recommended.
10
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Feature Description (continued)
7.3.3 VDD Undervoltage Lockout Protection
The TPS51206 device input voltage (VDD) includes undervoltage lockout protection (UVLO). When the VDD pin
voltage is lower than UVLO threshold voltage, VTT and VTTREF are shut off. This is non-latch protection.
7.3.4 VTT Current Limit
The TPS51206 device has VTT sink and source current limit capability. When the VTT current is higher than 2 A,
the current is limited and VTT voltage is out of regulation. When the current is below 2 A, the VTT voltage is in
regulation. This is non-latch protection.
7.3.5 Overtemperature Protection
This device features internal temperature monitoring. If the temperature exceeds the threshold value, VTT and
VTTREF are shut off. This is a non-latch protection.
7.3.6 Power On and Off Sequence
Figure 23 is the recommended power on and off sequence. During power on, it is allowed to turn on VDD, S3
and S5 first, then turn on VLDOIN and VDDQSNS. During power off, it is allowed to turn off VDD, S3 and S5
first, then turn off VLDOIN and VDDQSNS.
VDD
VLDOIN
VDDQSNS
S5
VTTREF
S3
VTT
UDG-11136
Figure 23. Typical Timing Diagram
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7.4 Device Functional Modes
7.4.1 Power State Control
The TPS51206 device has two input pins, S3 and S5, to provide simple control of the power state. Table 1
describes S3 and S5 terminal logic state and corresponding state of VTTREF and VTT outputs. VTT is turn-off
and placed to high impedance (High-Z) state in S3. The VTT output is floated and does not sink or source
current in this state. When both S5 and S3 pins are LOW, the power state is set to S4 and S5 . In S4 and S5
state, all the outputs are turn-off and discharged to GND.
Table 1. S3 and S5 Control Table
STATE
12
S3
S5
VTTREF
S0
HI
HI
ON
ON
S3
LO
HI
ON
OFF(High-Z)
S4 and S5
LO
LO
OFF(Discharge)
OFF(Discharge)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51206 device is typically used as a sink and source tracking termination regulator which converts a
voltage from VTT+0.4 V to 3.5 V
8.2 Typical Applications
8.2.1 VLDOIN = VDDQ Configuration
Figure 24 shows an application diagram for a configuration where VLDOIN and VDDQ are connected.
TPS51206
VDDQ
1
VDDQSNS
2
VLDOIN
VTT
3
VTTSNS
5
VTT
C1
10 PF
C3
10 PF
S3_SLP
7
S3
S5_SLP
9
S5
PGND
4
VTTREF
6
C4
0.22 PF
10 VDD
5 V or 3.3 V
C2
0.1 PF
VTTREF
GND
8
PowerPad
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 24. VLDOIN = VDDQ Configuration
8.2.1.1 Design Requirements
Table 2. Design Parameters
PARAMETER
EXAMPLE VALUE
Supply Voltage (VDD)
3.3 V or 5 V
VLDOIN = VDDQ
1.5 V
Output Current
±2 A
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8.2.1.2 Detailed Design Procedure
Table 3. VLDOIN = VDDQ Configuration Components
REFERENCE
DESIGNATOR
SPECIFICATION
MANUFACTURER
PART
NUMBER
C1, C3
10 µF, 6.3 V, X5R, 1608 (0603)
Taiyo Yuden
JMK107BJ106MA
C2
0.1 µF, 6.3 V, X5R, 1005 (0402)
Taiyo Yuden
JWK105BJ104MP
C4
0.22 µF, 6.3 V, X5R, 1005 (0402)
Taiyo Yuden
JMK105BJ224KV
8.2.1.2.1 VDD Capacitor
Add a ceramic capacitor, with a value 0.1 µF (or greater) and X5R grade (or better), placed close to the VDD
terminal, to stabilize the bias supply voltage from any parasitic impedance from the power supply rail.
8.2.1.2.2 VLDOIN Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-µF (or greater) and
X5R grade (or better) ceramic capacitor to supply this transient charge.
8.2.1.2.3 VTTREF Capacitor
Add a ceramic capacitor, with a value 0.22 µF and X5R grade (or better), placed close to the VTTREF terminal
for stable operation.
8.2.1.2.4 VTT Capacitor
For stable operation, a 10-µF (or greater) and X5R (or better) grade ceramic capacitor(s) need to be attached
close to the VTT terminal. This capacitor is recommended to minimize any additional equivalent series resistance
(ESR) and/or equivalent series inductance (ESL) of ground trace between the PGND terminal and the VTT
capacitor(s).
8.2.1.2.5 VTTSNS Connection
To achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, the VTTSNS pin
should be connected to the positive terminal of the VTT pin output capacitor(s) as a separate trace from the highcurrent path from VTT. Consider adding a low-pass R-C filter at the VTTSNS pin in case the ESR of the VTT
output capacitor(s) is larger than 2 mΩ. The R-C filter time constant should be approximately the same or slightly
lower than the time constant of the VTT output capacitance and ESR.
TPS51206
VTT
3
VTT
RC
VTTSNS
5
CC
C3
10 mF
PGND
4
UDG-11137
Figure 25. R-C Filter for VTTSNS
8.2.1.2.6 VDDQSNS Connection
VDDQSNS is a reference input of the VTTREF and VTT. Trace should be routed away from noise-generating
lines.
14
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8.2.1.3 Application Curves
VVTTREF(10 mV/div) 0.75 V offset
VVTT
(20 mV/div)
0.75 V offset
VVDDQSNS
(50 mV/div)
1.5 V offset
IVTT
(2 A/div)
Time (200 ms/div)
Figure 26. VTT Load Transient Response (0.75 V)
8.2.2 VLDOIN Separated from VDDQ Configuration
Figure 27 shows an application diagram for a configuration where VLDOIN and VDDQ are separated.
TPS51206
VDDQ Sense
VTT Power
1
VDDQSNS
2
VLDOIN
VTT
3
VTTSNS
5
C1
10 PF
C3
10 PF
S3_SLP
7
S3
S5_SLP
9
S5
5 V or 3.3 V
Supply
PGND
4
VTTREF
6
VTTREF
C4
0.22 PF
10 VDD
C2
0.1 PF
VTT
GND
8
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GND
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Figure 27. VLDOIN Separated from VDDQ Configuration
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8.2.2.1 Design Requirements
Table 4. Design Parameters
PARAMETER
EXAMPLE VALUE
Supply Voltage (VDD)
3.3 V or 5 V
VLDOIN = VDDQ
1.5 V
Output Current
±2 A
8.2.2.2 Detailed Design Procedure
Table 5. VLDOIN Separated from VDDQ Configuration Components
REFERENCE
DESIGNATOR
SPECIFICATION
PART
NUMBER
MANUFACTURER
C1, C3
10 µF, 6.3V, X5R, 1608 (0603)
Taiyo Yuden
JMK107BJ106MA
C2
0.1 µF, 6.3V, X5R, 1005 (0402)
Taiyo Yuden
JWK105BJ104MP
C3
10 µF, 6.3V, X5R, 1608 (0603)
Taiyo Yuden
JMK107BJ106MA
C4
0.22 µF, 6.3V, X5R, 1005 (0402)
Taiyo Yuden
JMK105BJ224KV
8.2.2.3 Application Curves
IVTTREF= 0 A
VVTTREF(500 mV/div)
IVTTREF= 0 A
VVTT (500 mV/div)
IVTT = 0 A
S3: Low to High
IVTT = 0 A
S3/S5: High to Low
VVTTREF (500 mV/div)
VVTT (500 mV/div)
VS5 (5 V/div)
VS5 (5 V/div)
VS3 (5 V/div)
VS3 (5 V/div)
Time (1 ms/div)
Time (2 s/div)
Figure 28. Start-Up Waveforms (S3: Low to High)
16
Figure 29. Shutdown Waveforms (S3 / S5: High to Low)
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9 Power Supply Recommendations
TPS51206 device is designed for a sink / source double date rate (DDR) termination regulator with VTTREF
buffered reference output. Supply input voltage (VDD) supports 3.3-V rail and 5-V rail; VLDOIN input voltage
supports VTT+0.4 V to 3.5 V.
10 Layout
10.1 Layout Guidelines
Consider the following before beginning a TPS51206 device layout design.
• The input bypass capacitor for VLDOIN should be placed as close as possible to the terminal with short and
wide connections.
• The output capacitor for VTT should be placed close to the terminals (VTT and PGND) with short and wide
connection in order to avoid additional ESR and/or ESL trace inductance.
• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high current VTT power trace. In addition, VTTSNS trace should be routed away from high current trace, on
the separate layer is recommended. This configuration is strongly recommended to avoid additional ESR
and/or ESL. If sensing the voltage at the point of the load is required, it is recommended to attach the output
capacitor(s) at that point. In addition, it is recommended to minimize any additional ESR and/or ESL of ground
trace between the GND pin and the VTT capacitor(s).
• The GND pin (and the negative node of the VTTREF output capacitor) and PGND pins (and the negative
node of the VTT output capacitor) should be connected to the internal system ground planes (for better result,
use at least two internal ground planes) with multiple vias. Use as many vias as possible to reduce the
impedance between GND pin or PGND pin and the system ground plane.
• In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the package thermal pad. The wide traces of the component and the side copper connected to the thermal
land pad help to dissipate heat. Numerous vias 0.33 mm in diameter connected from the thermal land to the
internal/solder side ground plane(s) should also be used to help dissipation. Consult the TPS51206-EVM
User's Guide for more detailed layout recommendations.
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VDDQ Sense Input
VTT Power
Supply Input
10.2 Layout Example
0.1 mF
0402
10 mF
0603
VDDQSNS
VDD
VLDOIN
S5
VTT
VTT Output
GND
PGND
10 mF
0603
5-V or 3.3-V Supply Input
0.22 mF
0402
S3
VTTSNS
VTTREF
VTTREF Output
Via to Ground Plane
Via for VTTSNS
Etch Beneath Component
UDG-11135
Figure 30. PCB Layout Guideline
10.3 Thermal Considerations
Because the TPS51206 device is a linear regulator, the VTT current flows in both source and sink directions,
thereby dissipating power from the device. When the device is sourcing current, the voltage difference between
VVLDOIN and VVTT times IVTT (VTT current) current becomes the power dissipation as shown in Equation 1.
PDISS(src) = (VVLDOIN - VVTT )´ IVTT(src)
(1)
In this case, if the VLDOIN pin is connected to an alternative power supply lower than the VDDQ voltage, overall
power loss can be reduced. For the sink phase, VTT voltage is applied across the internal LDO regulator, and
the power dissipation can be calculated by Equation 2.
PDISS(snk) = VVTT ´ IVTT(snk)
(2)
Maximum power dissipation allowed by the package is calculated by Equation 3.
TJ(max) - TA(max)
PPKG =
qJA
where
•
•
•
18
TJ(max) is 125°C
TA(max) is the maximum ambient temperature in the system
θJA is the thermal resistance from junction to ambient
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51206DSQR
ACTIVE
WSON
DSQ
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
1206
TPS51206DSQT
ACTIVE
WSON
DSQ
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
1206
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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