TPS51211
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SLUSAA7B – NOVEMBER 2010 – REVISED MAY 2013
High-Performance, Single Synchronous Step-Down
Controller For Notebook Power Supply
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
2
•
•
•
•
•
•
•
•
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Wide Input Voltage Range: 3 V to 28 V
Output Voltage Range: 0.7 V to 2.6 V
Wide Output Load Range: 0 to 20A+
Built-in 0.5% 0.7 V Reference
290-kHz, Adaptive On-Time D-CAP™ MODE
Control
4700 ppm/°C RDS(on) Current Sensing
Internal 1-ms Voltage Servo Soft-start
Pre-Charged Start-up Capability
Built in Output Discharge
Power Good Output
Integrated Boost Switch
Built-in OVP/UVP/OCP
Thermal Shutdown (Non-latch)
SON-10 (DSC) Package
Notebook Computers
I/O Supplies
System Power Supplies
DESCRIPTION
The TPS51211 is a small-sized single buck controller
with adaptive on-time D-CAP™ mode. The device is
suitable for low output voltage, high current, PC
system power rail and similar point-of-load (POL)
power supply in digital consumer products. A small
package with minimal pin-count saves space on the
PCB, while a dedicated EN pin and pre-set frequency
minimize design effort required for new designs. The
skip-mode at light load condition, strong gate drivers
and low-side FET RDS(on) current sensing supports
low-loss and high efficiency, over a broad load range.
The conversion input voltage which is the high-side
FET drain voltage ranges from 3 V to 28 V and the
output voltage ranges from 0.7 V to 2.6 V. The device
requires an external 5-V supply. The TPS51211 is
available in a 10-pin SON package specified from
–40°C to 85°C.
TYPICAL APPLICATION CIRCUIT
VIN
V5IN
TPS51211
EN
1
PGOOD
VBST 10
2
TRIP
DRVH
9
VOUT
3
EN
SW
8
4
VFB
V5IN
7
5
TST
DRVL
6
GND
VOUT_GND
UDG-10160
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
TPS51211
SLUSAA7B – NOVEMBER 2010 – REVISED MAY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA
PACKAGE
–40°C to 85°C
Plastic SON PowerPAD
ORDERING DEVICE
NUMBER
PINS
OUTPUT
SUPPLY
MINIMUM
QUANTITY
TPS51211DSCR
10
Tape and reel
3000
TPS51211DSCT
10
Mini reel
250
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Input voltage range (2)
Output voltage range (2)
VBST
–0.3 to 37
VBST (3)
–0.3 to 7
SW
–5 to 30
V5IN, EN, TRIP, VFB, TST
–0.3 to 7
DRVH
–5 to 37
DRVH (3)
–0.3 to 7
DRVH (3), pulse width < 20 ns
–2.5 to 7
DRVL
–0.5 to 7
DRVL, pulse width < 20 ns
–2.5 to 7
PGOOD
–0.3 to 7
UNIT
V
V
TJ
Junction temperature range
150
°C
TSTG
Storage temperature range
–55 to 150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
DISSIPATION RATINGS
2-oz. trace and copper pad with solder.
(1)
2
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
10-pin DSC (1)
1.54 W
15 mW/°C
0.62 W
Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information.
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TPS51211
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SLUSAA7B – NOVEMBER 2010 – REVISED MAY 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Input voltage range
4.5
6.5
VBST
–0.1
34.5
SW
–1
28
SW (1)
–4
28
–0.1
6.5
(2)
EN, TRIP, VFB, TST
–0.1
6.5
–1
34.5
DRVH (1)
–4
34.5
DRVH (2)
–0.1
6.5
DRVL
–0.3
6.5
PGOOD
–0.1
6.5
Operating free-air temperature
–40
85
DRVH
TA
(1)
(2)
MAX
V5IN
VBST
Output voltage range
TYP
UNIT
V
V
V
°C
This voltage should be applied for less than 30% of the repetitive period.
Voltage values are with respect to the SW terminal.
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ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VV5IN = 5 V. (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
320
600
μA
1
μA
SUPPLY CURRENT
IV5IN
V5IN supply current
TA = 25°C, No Load,
VEN = 5 V, VVFB = 0.735 V
IV5INSDN
V5IN shutdown current
TA = 25°C, No Load, VEN = 0 V
INTERNAL REFERENCE VOLTAGE
VVFB
VFB regulation voltage
IVFB
VFB input current
TA = 25°C
–10°C ≤ TA ≤ 85°C
0.7005
0.7040
0.7075
0.697
0.704
0.711
0.01
0.2
VVFB = 0.735 V, TA = 25°C
V
μA
OUTPUT DISCHARGE
Output discharge current from
SW pin
IDischg
VEN = 0 V, VSW = 0.5 V
5
13
mA
OUTPUT DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
tD
Dead time
Source, IDRVH = –50 mA
1.5
3.6
Sink, IDRVH = 50 mA
0.7
2.0
Source, IDRVL = –50 mA
1.0
3.0
0.5
1.6
Sink, IDRVL = 50 mA
DRVH-off to DRVL-on
7
17
DRVL-off to DRVH-on
10
22
Ω
ns
BOOT STRAP SWITCH
VFBST
Forward voltage
VV5IN-VBST, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VVBST = 34.5 V, VSW = 28 V, TA = 25°C
0.1
0.2
V
0.01
1.5
μA
260
400
DUTY AND FREQUENCY CONTROL
tOFF(min)
Minimum off-time
TA = 25°C
tON(min)
Minimum on-time
VIN = 28 V, VOUT = 0.7 V, TA = 25°C (1)
Internal SS time
From VEN = high to VOUT = 95%
150
79
ns
SOFTSTART
tss
1
ms
POWERGOOD
PG in from lower
92.5%
95%
97.5%
PG in from higher
107.5%
110%
112.5%
2.5%
5%
7.5%
3
6
0.8
1
VTHPG
PG threshold
IPGMAX
PG sink current
VPGOOD = 0.5 V
tPGDEL
PG delay
Delay for PG in
PG hysteresis
mA
1.2
ms
LOGIC THRESHOLD AND SETTING CONDITIONS
Enable
VEN
EN voltage threshold
IEN
EN input current
VEN = 5V
fSW
Switching frequency
TA = 25°C (2)
(1)
(2)
4
1.8
Disable
0.5
266
290
V
1.0
μA
314
kHz
Ensured by design. Not production tested.
Not production tested. Test condition is VIN= 8 V, VOUT= 1.1 V, IOUT = 10 A using application circuit shown in Figure 19.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VV5IN = 5 V. (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
9
10
11
UNIT
PROTECTION: CURRENT SENSE
ITRIP
TRIP source current
TCITRIP
TRIP current temperature
coeffficient
VTRIP = 1V, TA = 25°C
On the basis of 25°C
VTRIP
Current limit threshold setting
range
VTRIP-GND Voltage
VOCL
Current limit threshold
VAZCADJ
Adaptive zero cross adjustable
range
(3)
4700
0.2
VTRIP = 3.0 V
ppm/°C
3
375
VTRIP = 0.2 V
Positive
μA
V
mV
25
3
Negative
15
–15
–3
120%
125%
mV
PROTECTION: UVP AND OVP
VOVP
OVP trip threshold
OVP detect
tOVPDEL
OVP propagation delay time
50-mV overdrive
VUVP
Output UVP trip threshold
UVP detect
tUVPDEL
Output UVP propagation delay
time
tUVPEN
Output UVP enable delay time
115%
μs
1
65%
70%
75%
0.8
1
1.2
ms
1.0
1.2
1.4
ms
Wake up
4.20
4.38
4.50
Shutdown
3.7
3.93
4.1
From Enable to UVP workable
UVLO
VUVV5IN
V5IN UVLO threshold
V
THERMAL SHUTDOWN
TSDN
(3)
Thermal shutdown threshold
Shutdown temperature (3)
Hysteresis (3)
145
10
°C
Ensured by design. Not production tested.
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DEVICE INFORMATION
DSC PACKAGE
(TOP VIEW)
PGOOD
1
10
VBST
TRIP
2
9
DRVH
EN
3
8
SW
VFB
4
7
V5IN
TST
5
6
DRVL
TPS51211DSC
GND
Thermal pad is used as an active terminal of GND.
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
DRVH
9
O
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is
defined by the voltage across VBST to SW node bootstrap flying capacitor
DRVL
6
O
Synchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined by
V5IN voltage.
EN
3
I
SMPS enable pin. Short to GND to disable the device.
Thermal
Pad
I
Ground
PGOOD
1
O
Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signal
voltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes within
specified limits. Power bad, or the terminal goes low, after a 2- μs delay.
SW
8
I
Switch node. A high-side MOSFET gate drive return. Also used for on time generation and output
discharge.
GND
OCL detection threshold setting pin. 10 μA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
TRIP
2
I
VOCL =
VTRIP
8
(0.2 V ≤ VTRIP ≤ 3 V)
TST
5
I
Used for testing purpose in production line. Pull down to GND with a resistor of 470 kΩ or less.
V5IN
7
I
5-V +30%/–10% power supply input.
VBST
10
I
Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin to
the SW pin. Internally connected to V5IN via bootstrap MOSFET switch.
VFB
4
I
SMPS feedback input. Connect the feedback resistor divider.
6
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FUNCTIONAL BLOCK DIAGRAM
0.7 V –30%
+
UV
+
OV
0.7 V +10/15%
Delay
0.7 V –5/10%
Enable/SS Control
VFB
4
+
+
Ramp Comp
10 mA
TRIP
2
+
+
x(-1/8)
9
DRVH
8
SW
7
V5IN
6
DRVL
XCON
0.7 V
OCP
+
ZC
TST
10 VBST
Control Logic
PWM
+
2
PGOOD
+
0.7 V +20%
EN
1
+
5
tON
OneShot
GND
TPS51211
UDG-10161
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TYPICAL CHARACTERISTICS
V5IN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
V5IN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
800
20
VV5IN = 5 V
VEN = 5 V
VVFB = 0.735 V
No Load
IV5INSDN – V5IN Shutdown Current – mA
IV5IN – V5IN Supply Current – mA
1000
600
400
200
0
–50
0
50
100
18
16
14
12
10
8
6
4
2
0
–50
150
50
100
Figure 1.
Figure 2.
OVP/UVP THRESHOLD
vs
JUNCTION TEMPERATURE
CURRENT SENSE CURRENT (ITRIP)
vs
JUNCTION TEMPERATURE
150
150
20
VV5IN = 5 V
18
OVP
ITRIP – Current Sense Current – mA
VOVP /VUVP – OVP/UVP Trip Threshold – %
0
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
100
UVP
50
VV5IN = 5 V
VTRIP = 1 V
16
14
12
10
8
6
4
2
0
–50
0
50
100
TJ – Junction Temperature – °C
Figure 3.
8
VV5IN = 5 V
VEN = 0 V
No Load
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150
0
–50
0
50
100
150
TJ – Junction Temperature – °C
Figure 4.
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TPS51211
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SLUSAA7B – NOVEMBER 2010 – REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
1000
500
450
fSW – Switching Frequency – kHz
fSW – Switching Frequency – kHz
IOUT = 10 A
400
350
300
250
100
10
1
VIN = 12 V
200
6
8
10
12
14
16
18
20
0.1
0.001
22
0.01
VIN – Input Voltage – V
Figure 5.
0.1
1
100
10
IOUT – Output Current – A
Figure 6.
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.12
1.12
1.11
1.11
VOUT – Output Voltage – V
VOUT – Output Voltage – V
IOUT = 20 A
1.10
1.10
1.09
IOUT = 0 A
1.09
VIN = 12 V
1.08
0.001
1.08
0.01
0.1
1
IOUT – Output Current – A
Figure 7.
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10
100
6
8
10
12
14
16
18
20
22
VIN – Input Voltage – V
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
1.1-V EFFICIENCY
vs
OUTPUT CURRENT
100
90
VIN= 12 V
VOUT = 1.1 V
EN (5 V/div)
IOUT = 20 A
80
h – Efficiency – %
70
VOUT (0.5 V/div)
60
50
40
PGOOD (5 V/div)
30
VIN (V)
20
8
12
20
10
0
0.001
0.01
0.1
1
10
t – Time – 500 µs/div
100
IOUT – Output Current – A
Figure 9.
VIN= 12 V
Figure 10. 1.1-V Start-Up Waveform
X
X
X
EN (5 V/div)
IOUT = 0 A
EN (5 V/div)
VIN= 12 V
IOUT = 0 A
0.5-V pre-biased
VOUT (0.5 V/div)
PGOOD (5 V/div)
VOUT (0.5 V/div)
PGOOD (5 V/div)
DRVL (5 V/div)
t – Time – 500 µs/div
Figure 11. Pre-Biased Start-Up Waveform
X
X
X
10
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t – Time – 10 µs/div
Figure 12. 1.1-V Soft-Stop Waveform
X
X
X
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TPS51211
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TYPICAL CHARACTERISTICS (continued)
IOUT = 1 A to 15 A (3A/µs)
VIN= 20 V
V
OUT
(50 mV/div)
IIND
(10 A/div)
IOUT
(10 A/div)
t – Time – 100 µs/div
Figure 13. 1.1-V Load Transient Response
X
X
X
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The TPS51211 is a high-efficiency, single channel, synchronous buck regulator controller suitable for low output
voltage point-of-load applications in notebook computers and similar digital consumer applications. The device
features proprietary D-CAP™ mode control combined with adaptive on-time architecture. This combination is
ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage
ranges from 0.7 V to 2.6 V. The conversion input voltage range is from 3 V to 28 V. The D-CAP™ mode uses the
ESR of the output capacitor(s) to sense current information. An advantage of this control scheme is that it does
not require an external phase compensation network, helping the designer with ease-of-use and realizing low
external component count configuration. Adaptive on-time control tracks the preset switching frequency over a
wide range of input and output voltages, while it increases the switching frequency at step-up of load.
The strong gate drivers of the TPS51211 allow low RDS(on) FETs for high-current applications.
ENABLE AND SOFT START
When the EN pin voltage rises above the enable threshold, (typically 1.2 V) the controller enters its start-up
sequence. An internal DAC begins to ramp up the reference voltage from 0 V to 0.7 V. This ramping time is
750 μs. Smooth and constant ramp up of the output voltage is maintained during start up regardless of load
current. Connect a 1-kΩ resistor in series with the EN pin to provide protection.
ADAPTIVE ON-TIME D-CAP™ CONTROL
TPS51211 does not have a dedicated oscillator that determines switching frequency. However, the device runs
with pseudo-constant frequency by feed-forwarding the input and output voltages into its on-time one-shot timer.
The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and proportional
to the output voltage (tON ∝ VOUT / VIN ). This makes the switching frequency fairly constant in steady state
conditions over wide input voltage range.
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid point of resistor divider) is
compared to the internal 0.7-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts the set signal to terminate the off-time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal becomes valid if the inductor current level is below OCP threshold, otherwise the offtime is extended until the current level to become below the threshold.
12
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SMALL SIGNAL MODEL
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 14.
Switching Modulator
VIN
DRVH
R1
VFB
Control
Logic
and
Driver
PWM
+
R2
+
L
IIND
DRVL
VOUT
IOUT
IC
0.7 V
ESR
RL
Voltage Divider
VC
CO
Output
Capacitor
UDG-09063
Figure 14. Simplified Modulator Model
The output voltage is compared with internal reference voltage (ramp signal is ignored here for simplicity). The
PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
H(s) =
1
s ´ ESR ´ CO
(1)
For loop stability, the 0-dB frequency, ƒ0, defined in Equation 2 need to be lower than 1/4 of the switching
frequency.
f0 =
f
1
£ SW
2p ´ ESR ´ CO
4
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor's
chemistry. For example, specialty polymer capacitors (SP-CAP) have CO on the order of several 100 μF and
ESR in range of 10 mΩ. These makes f0 on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ0 of more than 700 kHz, which is not suitable for this modulator.
RAMP SIGNAL
The TPS51211 adds a ramp signal to the 0.7-V reference in order to improve its jitter performance. As described
in the previous section, the feedback voltage is compared with the reference information to keep the output
voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with –7 mV at the beginning of ON-cycle and becomes 0 mV at the end of OFF-cycle in
continuous conduction steady state.
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LIGHT LOAD CONDITION IN AUTO-SKIP OPERATION
The TPS51211 automatically reduces switching frequency at light load conditions to maintain high efficiency. As
the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to the point that its rippled valley touches zero level, which is the boundary between continuous
conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor
current is detected. As the load current further decreases, the converter runs in to discontinuous conduction
mode. The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer
time to discharge the output capacitor with smaller load current to the level of the reference voltage. The
transition point to the light load operation IO(LL) (i.e., the threshold between continuous and discontinuous
conduction mode) can be calculated in Equation 3.
IO(LL ) =
(V - VOUT ) ´ VOUT
1
´ IN
2 ´ L ´ fSW
VIN
where
•
fSW is the PWM switching frequency
(3)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportional to the output current from the IO(LL) given in Equation 3. For example, it is 58 kHz
at IO(LL)/5 if the frequency setting is 290 kHz.
ADAPTIVE ZERO CROSSING
The TPS51211 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.
OUTPUT DISCHARGE CONTROL
When EN is low, the TPS51211 discharges the output capacitor using internal MOSFET connected between SW
and GND while high-side and low-side MOSFETs are kept off. The current capability of this MOSFET is limited to
discharge slowly.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which are 1.0Ω for V5IN to DRVL and 0.5Ω for DRVL to GND. A dead time
to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and
low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at Vgs=5V times switching frequency. This gate drive current as well as
the high-side gate drive current times 5V makes the driving power which need to be dissipated from TPS51211
package.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a
floating driver, 5 V of bias voltage is delivered from V5IN supply. The average drive current is also equal to the
gate charge at VGS=5V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBST and SW pins. The drive capability is represented by its internal resistance, which are
1.5 Ω for VBST to DRVH and 0.7 Ω for DRVH to SW.
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POWER-GOOD
The TPS51211 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10%/–5% of
the target value, internal comparators detect power-good state and the power-good signal becomes high after a
1-ms internal delay. If the output voltage goes outside of +15%/–10% of the target value, the powergood signal
becomes low after a 2-μs internal delay. The powergood output is an open-drain output and must be pulled up
externally.
CURRENT SENSE AND OVER CURRENT PROTECTION
TPS51211 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. To
provide both good accuracy and cost effective solution, the TPS51211 supports temperature compensated
MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,
RTRIP. The TRIP terminal sources ITRIP current, which is 10μA typically at room temperature, and the trip level is
set to the OCL trip voltage VTRIP as shown in Equation 4. Note that VTRIP is limited up to approximately 3 V
internally.
VTRIP (mV) = RTRIP (kW) ´ ITRIP (mA)
(4)
The inductor current is monitored by the voltage between GND pad and SW pin so that the SW pin should be
connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700ppm/°C temperature slope to
compensate the temperature dependency of the RDS(on). GND is used as the positive current sensing node so
that GND should be connected to the proper current sensing device, i.e. the source terminal of the low-side
MOSFET.
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load
current at overcurrent threshold, IOCP, can be calculated in Equation 5
æ V
TRIP
IOCP = ç
ç 8 ´ RDS(on)
è
ö IIND(ripple )
(V - VOUT ) ´ VOUT
VTRIP
1
÷+
=
+
´ IN
÷
2
8 ´ RDS(on) 2 ´ L ´ fSW
VIN
ø
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down the
controller.
OVER/UNDER VOLTAGE PROTECTION
TPS51211 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After a 1-ms delay, TPS51211 latches OFF both highside and low-side MOSFETs drivers. This function is enabled after 1.2 ms following EN has become high.
UVLO PROTECTION
TPS51211 has V5IN undervoltage lockout protection (UVLO). When the V5IN voltage is lower than UVLO
threshold voltage, the switch mode power supply shuts off. This is non-latch protection.
THERMAL SHUTDOWN
TPS51211 monitors the die temperature. If the temperature exceeds the threshold value (typically 145°C), the
TPS51211 is shut off. This is non-latch protection.
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EXTERNAL COMPONENTS SELECTION
Selecting external components is simple in D-CAP™ mode.
Step 1. Choose the inductor.
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable
operation.
L=
1
IIND(ripple) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(6)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 7.
IIND(peak ) =
)
(
VIN(max ) - VOUT ´ VOUT
VTRIP
1
+
´
8 ´ RDS(on) L ´ fSW
VIN(max )
(7)
Step 2. Choose the output capacitor(s).
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For loop stability,
capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to
determine ESR.
ESR =
VOUT ´ 10 éëmV ùû ´ (1 - D )
0.7 éë V ùû ´ IIND(ripple)
=
10 éëmV ùû ´ L ´ fSW
0.7 éë V ùû
=
L ´ fSW
éW ù
70 ë û
where
D is the duty ratio
the output ripple down slope rate is 10 mV/tSW in terms of VFB terminal voltage as shown in Figure 15
tSW is the switching period
VVFB – Feedback Voltage – mV
•
•
•
(8)
tSW x (1-D)
10
VRIPPLE(FB)
0
tSW
t – Time
Figure 15. Ripple Voltage Down Slope
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Step 3. Determine the value of R1 and R2.
The output voltage is programmed by the voltage-divider resistor, R1 and R2, shown in Figure 14. R1 is
connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. Typical
designs begin with the selection of an R2 value between 10 kΩ and 20 kΩ. Determine R1 using Equation 9.
IIND(ripple) ´ ESR ö
æ
çç VOUT ÷÷ - 0.7
2
è
ø
´ R2
R1 =
0.7
(9)
Special consideration for high-side drivers.
When an application uses the latest fast-switching type MOSFETs, it is recommended to populate the design
with two resistors before evaluation (without shorting).
In this situation, place R7 in series with the bootstrap capacitor and place R8 in series with the high-side gate
driver as shown in Figure 16. Both resistors can have a value of 0 Ω and they should be placed regardless of the
design in case they are ultimately needed to control switching speed. When a resistance of 0 Ω is confirmed as a
result of the evaluation, the resistor can be shorted in the final design.
V5IN
VIN
C3
U1
TPS51211
R6
R1
R7
0Ÿ
1
PGOOD
VBST 10
2
TRIP
DRVH
C1
R8
Q1
9
L1
0:
R3
EN
3
EN
4
VFB
SW
8
V5IN
7
VOUT
C4
Q2
5
R2
R5
TST
GND
R4
DRVL
6
C2
VOUT_GND
UDG-13107
Figure 16. Special Consideration for High-Side Drivers
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LAYOUT CONSIDERATIONS
VIN
TRIP
TPS51211
2
V5IN
TST
VOUT
6
#1
5
1 mF
#2
DRVL
VFB
4
5
Thermal Pad
GND
#3
UDG-10162
Figure 17. Ground System of DC/DC Converter Using the TPS51211
Certain points must be considered before starting a layout work using the TPS51211.
• Inductor, VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed
on one side of the PCB (solder side). Other small signal components should be placed on another side
(component side). At least one inner plane should be inserted, connected to ground, in order to shield and
isolate the small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP and TST should be placed away
from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal
layer(s) as ground plane(s) and shield feedback trace from power traces and components.
• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and
low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the VIN
capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 of
Figure 17)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitor(s),
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of Figure 17)
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
from gate of the low-side MOSFET through the gate driver and GND pad of the device, and back to
source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the
low-side MOSFET and GND pad of the device at ground as close as possible. (Refer to loop #3 of
Figure 17)
• Since the TPS51211 controls output voltage referring to voltage across VOUT capacitor, the top-side resistor of
the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner both
bottom side resistor and GND pad of the device should be connected to the negative node of VOUT capacitor.
The trace from these resistors to the VFB pin should be short and thin. Place on the component side and
avoid via(s) between these resistors and the device.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
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•
•
•
SLUSAA7B – NOVEMBER 2010 – REVISED MAY 2013
to a high-voltage switching node.
Connect the frequency setting resistor from TST pin to ground, or to the PGOOD pin, and make the
connections as close as possible to the device. The trace from the TST pin to the resistor and from the
resistor to ground should avoid coupling to a high-voltage switching node.
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least
0.5 mm (20 mils) diameter along this trace.
The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
LAYOUT CONSIDERATIONS TO REMOTE SENSING
VIN
TRIP
TPS51211
2
V5IN
TST
6
5
VOUT
1 mF
VFB
DRVL
4
0.1 mF
5
100 W
VTT_SENSE
VSS_SENSE
Thermal Pad
GND
UDG-10163
Figure 18. Remote Sensing of Output Voltage Using the TPS51211
•
•
•
Make a Kelvin connection to the load device.
Run the feedback signals as a differential pair to the device. The distance of these parallel pair should be as
short as possible.
Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.
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TPS51211
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TPS51211 APPLICATION CIRCUITS
V5IN
4.5 V
to
6.5 V
U1
TPS51211
R6
100 kW
R1
5.6 kW
1
PGOOD
C3
10 mF x 4
C1
0.1 mF
VBST 10
Q1
FDMS8680
R7
2
R3
1 kW
9
3.3 W
EN
R2
10 kW
DRVH
TRIP
R5
30 kW
3
EN
SW
8
4
VFB
V5IN
7
5
TST
DRVL
6
GND
R4
470 kW
VIN
8V
to
20 V
Q2
FDMS8670AS
Q3
FDMS8670AS
L1
0.45 mH
VOUT
1.1 V
18 A
C4
330 mF x 4
C2
1 mF
VOUT_GND
UDG-10164
Figure 19. 1.1-V VOUT, 18-A IOUT Application
Table 1. 1.1-V, 18-A, 290-kHz Application List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
C3
1
4 × 10 μF, 25 V
Taiyo Yuden
TMK325BJ106MM
C4
1
4 × 330 μF, 2 V, 12 mΩ
Panasonic
EEFCX0D331XR
L1
1
0.45 μH, 25 A, 1.1 mΩ
Panasonic
ETQP4LR45XFC
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2, Q3
2
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
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SLUSAA7B – NOVEMBER 2010 – REVISED MAY 2013
Changes from Original (NOVEMBER 2010) to Revision A
Page
•
Added DRVH, pulse width < 20 ns rating in ABSOLUTE MAXIMUM RATINGS table ........................................................ 2
•
Added DRVL, pulse width < 20 ns rating in ABSOLUTE MAXIMUM RATINGS table ......................................................... 2
Changes from Revision A (FEBRUARY 2012) to Revision B
•
Page
Added clarity to the EXTERNAL COMPONENTS SELECTION section ............................................................................ 16
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51211DSCR
ACTIVE
WSON
DSC
10
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
S51211
TPS51211DSCT
ACTIVE
WSON
DSC
10
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
S51211
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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