TPS51220
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SLVS785C – OCTOBER 2007 – REVISED JULY 2009
Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller
Check for Samples: TPS51220
FEATURES
1
•
•
•
2
•
•
•
•
•
•
Input Voltage Range: 4.5 V to 28 V
Output Voltage Range: 1 V to 12 V
Selectable Light Load Operation
(Continuous / Auto Skip / Out-Of-Audio™ Skip)
Programmable Droop Compensation
Voltage Servo Adjustable Soft Start
200 kHz to 1 MHz Fixed Frequency PWM
Selectable Current/ D-CAP™ Mode
Architecture
180° Phase Shift Between Channels
Resistor or Inductor DCR Current Sensing
•
•
•
•
•
•
Powergood Output for Each Channel
OCL/OVP/UVP/UVLO Protections
(OVP Disable Option)
Thermal Shutdown (Non-Latch)
Output Discharge Function (Disable Option)
Integrated Boot Strap MOSFET Switch
QFN-32 (RHB)
APPLICATIONS
•
•
Notebook Computer System and I/O Bus
Point of Load in LCD TV, MFP
DESCRIPTION
The TPS51220 is a dual synchronous buck regulator controller with 2 LDOs. It is optimized for 5-V/3.3-V system
controller, enabling designers to cost effectively complete 2-cell to 4-cell notebook system power supply. The
TPS51220 supports high efficiency, fast transient response and 99% duty cycle operation. It supports supply
input voltage ranging from 4.5 V to 28 V, and output voltages from 1 V to 12 V. Two types of control schemes
can be chosen depending on the application. Peak current mode supports stability operation with lower ESR
capacitor and output accuracy. The D-CAP mode supports fast transient response. The high duty (99%)
operation and the wide input/output voltage range supports flexible design for small mobile PCs and a wide
variety of other applications. The fixed frequency can be adjusted from 200 kHz to 1 MHz by a resistor, and each
channel runs 180° out of phase. The TPS51220 can also synchronize to the external clock, and the interleaving
ratio can be adjusted by its duty. The TPS51220 is available in the 32 pin 5x5 QFN package and is specified
from –40°C to 85°C.
Figure 1. TYPICAL APPLICATION CIRCUIT
VBAT
VBAT
C14
PGND
C24
Q12
VO1
2
29
28
27
26
GND
DRVL2
VBST2
DRVH1
30
DRVL1
31
L2
C21
Q22
VREG5
1
32
SW1
PGND
VBST1
C11
C22
PGND
GND
PGND
PGND
PGND
Q21
C01
PGND
DRVH2
PGND
24
VIN 23
V5SW
VBAT
R01
3
RF
4
EN1
VREG3 22
5
PGOOD1
6
SKIPSEL1
C03
GND EN1
PGOOD1
SKIPSEL1
PGOOD2
R24
13
15
VREG5
R21
VO2
R12
R22
C02
R13
GND
16
R23
GND
VO1
14
C23
CSN2 17
VFB2
12
COMP2
11
TRIP
VREF2
10
EN
9
FUNC
GND
GND
SKIPSEL2
CSP2 18
CSN1
COMP1
8
R11
PGOOD2 20
SKIPSEL2 19
CSP1
VFB1
7
C13
VREG3
3.3V/10mA
EN2
PowerPAD
R14
EN
EN2 21
TPS51220RHB
(QFN32)
VO2
3.3 V
25
SW2
L1
VO1
5.0 V
VREG5
5V/100mA
Q11
C12
GND
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Out-Of-Audio, D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TPS51220
SLVS785C – OCTOBER 2007 – REVISED JULY 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
V5SW
+
4.7V/ 4.5V
+
1.25V
+
+
VREG5
4.7V/ 4.5V
VREG3
GND
V5OK
+
4.2V/ 3.8V
Ready
GND
+
THOK
150/ 140
Deg-C
VREF2
1.25V
GND
GND
CLK2
OSC
RF
CLK1
GND
1V +5%/ 10%
+
PGOOD1
Delay
+
1V -30%
1V - 5%/ 10%
+
GND
UVP
CLK1
Ready
+
FUNC
Fault2
OVP
SDN2
1V +15%
Fault1
COMP1
Ramp
Comp
CUR
VFB1
SDN1
+
+ PWM
VREG5
1V
+
Enable/
Soft-start
+
D-CAP
VFB-AMP
EN1
VREF2
VBST1
Ramp
Comp
+
Skip
DRVH1
CS-AMP
CSN1
SW1
+
OCP
+
CSP1
Control
Logic
XCON
VREG5
100mV
DRVL1
TRIP
Discharge
Control
GND
GND
100mV
VREF2
N-OCP
+
GND
OOA
Ctrl
GND
SKIPSEL1
Channel-1 Switcher shown
2
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SLVS785C – OCTOBER 2007 – REVISED JULY 2009
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range
(2)
VALUE
UNIT
VIN
–0.3 to 30
V
VBST1, VBST2
–0.3 to 35
V
VBST1, VBST2 (3)
–0.3 to 7
V
SW1, SW2
–7 to 30
V
CSP1, CSP2, CSN1, CSN2
–1 to 13.5
V
EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2, FUNC
–0.3 to 7
V
V5SW
–0.3 to 7
V
V5SW (to VREG5)
(4)
–7 to 7
V
DRVH1, DRVH2
–7 to 35
V
DRVH1, DRVH2 (3)
–0.3 to 7
V
DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2,
PGOOD1, PGOOD2
–0.3 to 7
V
VO
Output voltage range (2)
–0.3 to 3.6
V
TJ
Operating junction temperature range
–40 to 125
°C
Tstg
Storage temperature
–55 to 150
°C
VREG3
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the corresponding SW terminal.
When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.
DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
32 pin RHB
2.2 W
23 mW/°C
0.9 W
RECOMMENDED OPERATING CONDITIONS
MIN
VSS
Supply
voltage
VIN
TA
I/O voltage
MAX
28
V5SW
–0.8
6
DRVH1, DRVH2
–4.0
33
VBST1, VBST2,
–0.1
33
DRVH1, DRVH2 (wrt SW1, SW2)
–0.1
6
–6
33
–4.0
28
–6
28
CSP1, CSP2, CSN1, CSN2
–0.8
13
EN, EN1, EN2, VFB1, VFB2, TRIP, DRVL1, DRVL2, COMP1, COMP2, VREG5,
RF, VREF2, PGOOD1, PGOOD2, SKIPSEL1, SKIPSEL2, FUNC
–0.1
6
VREG3
–0.1
3.5
–40
85
DRVH1, DRVH2 (negative overshoot -6 V for t< 20% duration of switching period)
VI
VO
TYP
4.5
SW1, SW2
SW1, SW2 (negative overshoot -6 V for t< 20% duration of switching period)
Operating free-air temperature
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UNIT
V
V
°C
3
TPS51220
SLVS785C – OCTOBER 2007 – REVISED JULY 2009
www.ti.com
ORDERING INFORMATION
(1)
4
TA
PACKAGE (1)
-40°C to 85°C
Plastic Quad Flat Pack
(32 Pin QFN)
ORDERABLE PART
NUMBER
TRANSPORT MEDIA
TPS51220RHBT
Tape and Reel
250
TPS51220RHBR
Tape and Reel
3000
QUANTITY
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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SLVS785C – OCTOBER 2007 – REVISED JULY 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
7
15
μA
80
120
μA
SUPPLY CURRENT
I(VINSDN)
VIN shutdown current
VIN shutdown current, TA = 25°C,
No Load, EN = 0V, V5SW = 0 V
I(VINSTBY)
VIN standby current
VIN standby current, TA = 25°C, No Load,
EN1 = EN2 = V5SW = 0 V
I(VBATSTBY)
VBAT standby current
VBAT standby current, TA = 25°C, No Load
SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V (1)
I(V5SW)
V5SW supply current
V5SW current, TA = 25°C, No Load,
ENx = 5V, VFBx = 1.05 V
500
μA
TRIP = 5 V
1.2
mA
TRIP = 0 V
1.4
mA
VREF2 OUTPUT
V(VREF2)
VREF2 output voltage
I(VREF2) < ±10 μA, TA = 25°C
1.98
2.00
2.02
I(VREF2) < ±100 μA, 4.5V < VIN < 25 V
1.97
2.00
2.03
V
VREG3 OUTPUT
V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C
3.279
3.313
3.347
V(VREG3)
VREG3 output voltage
V5SW = 0 V, 0 mA < I(VREG3) < 10 mA,
5.5 V < VIN < 25 V
3.135
3.300
3.400
I(VREG3)
VREG3 output current
VREG3 = 3 V
10
15
20
V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C
4.99
5.04
5.09
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
6 V < VIN < 25 V
4.90
5.03
5.15
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
5.5 V < VIN < 25 V
4.50
5.03
5.15
V5SW = 0 V, VREG5 = 4.5 V
100
150
200
V5SW = 5 V, VREG5 = 4.5 V
200
300
400
Turning on
4.55
4.7
4.8
Hysteresis
0.15
0.20
0.25
V
mA
VREG5 OUTPUT
V(VREG5)
VREG5 output voltage
V
V
I(VREG5)
VREG5 output current
mA
V(THV5SW)
Switchover threshold
td(V5SW)
Switchover delay
Turning on
7.7
ms
R(V5SW)
5V SW on-resistance
I(VREG5) = 100 mA
0.5
Ω
V(VFB)
VF B regulation voltage
tolerance
TA = 25°C, No Load
I(VFB)
VF B input current
VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C
R(Dischg)
CSNx discharge resistance ENx = 0 V, CSNx = 0.5 V, TA = 25°C
V
OUTPUT
TA = –40°C to 85°C , No Load
0.9925
1.000
1.0075
0.990
1.000
1.010
–50
20
V
50
nA
40
Ω
VOLTAGE TRANSCONDUCTANCE AMPLIFIER
Gain
VID
Differential input voltage
range
I(COMPSINK)
COMP maximum sink
current
COMPx = 1.8 V
33
μA
I(COMPSRC)
COMP maximum source
current
COMPx = 1.8 V
–33
μA
(1)
TA = 25°C
μS
Gmv
500
–30
30
mV
Specified by design. Detail external condition follows application circuit of Figure 53.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT AMPLIFIER
GC
Gain
VIC
Common mode input
voltage range
VID
Differential input voltage
range
TRIP = 0V/2V, CSN = 5V, TA = 25°C (2)
3.333
TRIP = 3.3V/5V, CSN = 5V, TA = 25°C (2)
1.667
TA = 25°C
0
13
V
–75
75
mV
POWERGOOD
V(THPG)
PG threshold
PG in from lower
92.5%
PG in from higher
102.5%
PG hysteresis
95%
97.5%
105% 107.5%
5%
I(PG)
PG sink current
PGOOD = 0.5 V
t(PGDLY)
PGOOD delay
Delay for PG in
5
t(SSDYL)
Soft-start delay time
Delay for Soft Start, ENx = Hi to SS-ramp starts
200
μs
t(SS)
Soft-start Time
Internal Soft Start
960
μs
0.8
1
mA
1.2
ms
SOFTSTART
FREQUENCY AND DUTY CONTROL
f(SW)
Switching frequency
Rf = 330 kΩ
273
303
333
Lo to Hi
0.7
1.3
2
V(THRF)
RF threshold
f(SYNC)
Syncronization Input
Frequency Range (2)
tONmin
Minimum On Time
V(DRVH) = 90% to 10%, No Load
tOFFmin
Minimum Off Time
V(DRVH) = 10% to 90%, No Load
tD
Dead time
V(DTH)
DRVH-off threshold
DRVH to GND
V(DTL)
DRVL-off threshold
DRVL to GND (2)
Hysteresis
0.2
200
kHz
V
V
1000
kHz
120
150
ns
290
440
ns
DRVH-off to DRVL-on
10
30
50
ns
DRVL-off to DRVH-on
30
40
70
ns
(2)
1
V
1
V
OUTPUT DRIVERS
R(DRVH)
DRVH resistance
R(DRVL)
DRVL resistance
Source, V(VBST-DRVH) = 0.1 V
1.7
5
1
3
Source, V(VREG5-DRVL) = 0.1 V
1.3
4
Sink, V(DRVL-GND) = 0.1 V
0.7
2
Sink, V(DRVH-SW) = 0.1 V
Ω
Ω
CURRENT SENSE
Current limit threshold
(ultra-low voltage)
TRIP = 0V/2V, TA = 25°C
27
31
35
TRIP = 0V/2V
25
31
37
V(OCL-LV)
Current limit threshold
(low voltage)
TRIP = 3.3V/5V, TA = 25°C
56
60
64
TRIP = 3.3V/5V
54
60
66
V(ZC)
Zero cross detection
comparator Offset
0.95V < CSNx < 12.6V
–4
0
4
Negative current limit
threshold
(ultra-low voltage)
TRIP = 0V/2V, TA = 25°C
–24
–31
–38
V(OCLN-ULV)
TRIP = 0V/2V
–22
–31
–40
TRIP = 3.3V/5V, TA = 25°C
–51
–60
–69
V(OCLN-LV)
Negative current limit
threshold
(low voltage)
TRIP = 3.3V/5V
–49
–60
–71
V(OCL-ULV)
(2)
6
mV
mV
mV
Specified by design.
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SLVS785C – OCTOBER 2007 – REVISED JULY 2009
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
110%
115%
120%
UNIT
UVP, OVP AND UVLO
V(OVP)
OVP Trip Threshold
t(OVPDLY)
OVP Prop Delay
V(UVP)
UVP Trip Threshold
t(UVPDLY)
UVP Delay
V(UVREF2)
VREF2 UVLO Threshold
V(UVREG3)
VREG3 UVLO Threshold
V(UVREG5)
VREG5 UVLO Threshold
OVP detect
μs
1.5
UVP detect
65%
70%
73%
0.8
1
1.2
Wake up
1.7
1.8
1.9
V
Hysteresis
75
100
125
mV
Wake up
Hysteresis
Wake up
Hysteresis
ms
3
3.1
3.2
0.10
0.15
0.20
4.1
4.2
4.3
V
0.35
0.40
0.44
V
V
INTERFACE AND LOGIC THRESHOLD
Wake up
0.8
1
1.2
Hysteresis
0.1
0.2
0.3
0.45
0.50
0.55
0.1
0.2
0.3
V(EN)
EN Threshold
V(EN12)
EN1/EN2 Threshold
V(EN12SS)
EN1/EN2 SS Start
Threshold
SS-ramp start threshold at external soft start
V(EN12SSEND)
EN1/EN2 SS End
Threshold
SS-End threshold at external soft start
I(EN12)
EN1/EN2 Source Current
VEN1/EN2 = 0V
Wake up
Hysteresis
(3)
1.5
SKIPSEL1/SKIPSEL2
Setting Voltage
V
2
V
2
TRIP Setting Voltage
FUNC Setting Voltage
I(TRIP)
TRIP Input Current
I(SKIPSEL)
SKIPSEL Input Current
μA
1.5
1.9
2.1
OOA Skip (min 1/8 Fsw)
3.2
3.4
OOA Skip (min 1/16 Fsw)
3.8
V
1.5
V(OCL-ULV), Discharge OFF
1.9
2.1
V(OCL-LV), Discharge OFF
3.2
3.4
V(OCL-LV), Discharge ON
3.8
Current mode, OVP enable
V(FUNC)
2.6
Auto Skip
V(OCL-ULV), Discharge ON
V(TRIP)
V
1
Continuous
V(SKIPSEL)
V
V
1.5
D-CAP mode, OVP disable
1.9
2.1
D-CAP mode, OVP enable
3.2
3.4
Current mode, OVP disable
3.8
TRIP = 0 V
–1
1
TRIP =5 V
–1
1
SKIPSELx = 0 V
–0.5
0.5
SKIPSELx = 5 V
–0.5
0.5
V
μA
μA
BOOT STRAP SW
V(FBST)
Forward Voltage
VVREG5-VBST, IF = 10 mA, TA = 25°C
0.10
0.20
V
I(BSTLK)
VBST Leakage Current
VBST = 30 V, SW = 25 V
0.01
1.5
μA
Shutdown temperature (3)
150
THERMAL SHUTDOWN
T(SDN)
(3)
Thermal SDN Threshold
Hysteresis (3)
10
°C
Specified by design.
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DEVICE INFORMATION
PINOUT
VBST2
SW2
25
GND
DRVL2
27
26
30
20
19
7
8
18
17
PGOOD2
SKIPSEL2
CSP2
CSN2
VFB1
COMP1
FUNC
15
16
9
10
CSN1
5
6
VREG3
EN2
VREF2
TRIP
COMP2
VFB2
SKIPSEL1
CSP1
DRVH2
VIN
3
4
24
23
22
21
1
2
11
12
13
14
V5SW
RF
EN1
PGOOD1
EN
DRVH1
29
28
32
31
SW1
VBST1
DRVL1
VREG5
RHB PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DRVH1
1
DRVH2
24
SW2
25
SW1
32
VREG3
22
EN1
4
EN2
21
PGOOD1
5
PGOOD2
20
SKIPSEL1
6
SKIPSEL2
19
CSP1
7
CSP2
18
CSN1
8
CSN2
17
VFB1
9
VFB2
16
COMP1
10
COMP2
15
RF
3
8
I/O
DESCRIPTION
O
High-side MOSFET gate driver outputs. Source 1.7Ω, sink 1.0Ω, SW-node referenced floating driver. Drive
voltage corresponds to VBST to SW voltage.
I/O
High-side MOSFET gate driver returns.
O
Always alive 3.3-V, 10-mA low dropout linear regulator output. Bypass to (signal) GND with more than 1-μF
ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
I
Channel 1 and channel 2 SMPS enable Pins. When turning on, apply greater than 0.55 V and less than 6 V,
or be floating. Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
O
Power Good window comparator outputs for channel 1 and channel 2. The applied voltage should be less
than 6 V, and the recommended pull-up resistance value is from 100 kΩ to 1 MΩ.
Skip mode selection pin.
I
GND: Continuous conduction mode
VREF2: Auto skip
VREG3: OOA auto skip, maximum 7 skips (suitable for fsw < 400 kHz)
VREG5: OOA auto skip, maximum 15 skips (suitable for equal to or greater than 400 kHz)
I/O
Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
be used to extract voltage drop across DCR. 0.1 μF is a good value to start the design. See the current
sensing scheme section for more details.
I
Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the
current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal.
I
SMPS voltage feedback inputs. Connect the feedback resistors divider, and should be referred to (signal)
GND.
I
Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin
to VREF2 for proper loop compensation with current mode operation. Ramp compensation adjustable pin for
D-CAP mode, connect R from this pin to VREF2. 10 kΩ is a good value to start the design. 6 kΩ to 20 kΩ
can be chosen. See the D-CAP MODE section for more details.
I/O
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
synchronization.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Control architecture and OVP function selection pin.
FUNC
11
I
VREF2
13
O
GND: Current mode, OVP enable
VREF2: D-CAP mode, OVP disable
VREG3: D-CAP mode, OVP enable
VREG5: Current mode, OVP disable
2-V Reference Output. Bypass to (signal) GND by 0.22μF ceramic capacitor.
Overcurrent trip level and discharge mode selection pin.
GND: V(OCL-ULV) , Discharge on
VREF2: V(OCL-ULV), Discharge off
VREG3: V(OCL-LV), Discharge off
VREG5: V(OCL-LV), Discharge on
TRIP
14
I
EN
12
I
VREF2 and VREG5 Linear Regulators Enable Pin. When turning on, apply greater than 1.2V and less than
6V. Connect to GND to Disable.
VBST1
31
I
Supply inputs for high-side NFET driver (boot strap Terminal). Connect a capacitor (0.1μF or greater is
recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this pin is an
optional.
O
Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, GND referenced driver.
I
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
voltage is higher than 4.8 V, switch-over function will be enabled. (Note) When switch-over is enabled,
VREG5 output voltage will be almost the same as V5SW input voltage.
VBST2
26
DRVL1
30
DRVL2
27
V5SW
2
VREG5
29
O
5-V, 100-mA low-dropout linear regulator output. Bypass to (power) GND using a 10-μF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
when 4.8 V or above is provided. (Note: when switch-over (above V5SW) is enabled, VREG5 output voltage
is approximately the same as V5SW input voltage.)
VIN
23
I
Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
GND
28
–
Ground.
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TYPICAL CHARACTERISTICS
VIN SHUTDOWN CURRENT
vs
INPUT VOLTAGE
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
15
15
I(VINSDN) - Shutdown Current - μA
I(VINSDN) - Shutdown Current - μA
VIN = 12V
12
9
6
3
12
9
6
3
RT
0
-50
0
5
10
15
20
25
30
100
Figure 3.
VIN STANDBY CURRENT
vs
JUNCTION TEMPERATURE
VIN STANDBY CURRENT
vs
INPUT VOLTAGE
120
120
100
100
80
60
40
150
80
60
40
20
20
10
50
Figure 2.
I(VINSTBY) - Standby Current - mA
I(VINSTBY) - Standby Current - mA
VI - VIN Input Voltage - V
0
-50
0
TJ - Junction Temperature - °C
0
0
50
100
TJ - Junction Temperature - °C
Figure 4.
150
5
10
15
20
VI - VIN Input Voltage - V
25
30
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
NO LOAD BATTERY CURRENT
vs
INPUT VOLTAGE
NO LOAD BATTERY CURRENT
vs
INPUT VOLTAGE
1.0
1.0
EN = on, EN1 = on, EN2 = on
0.9
0.9
0.8
0.8
I(VBAT) - Battery Current - mA
I(VBAT) - Battery Current - mA
EN = on, EN1 = off, EN2 = on
0.7
0.6
0.5
0.4
0.3
0.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.1
0.0
5
10
15
20
0.0
25
5
VI - VIN Input Voltage - V
10
15
20
VI - VIN Input Voltage - V
Figure 6.
Figure 7.
BATTERY CURRENT
vs
INPUT VOLTAGE
VREF2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
25
2.02
1.0
EN = on, EN1 = on, EN2 = off
VIN = 12V
0.9
VO(VREF2) - Output Voltage - V
I(VBAT) - Battery Current - mA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
2.01
2.00
1.99
0.1
0.0
5
10
15
20
VI - VIN Input Voltage - V
25
1.98
-100
Figure 8.
-50
0
50
100
IO(VREF2) - Output Current - μA
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
VREG3 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VREG5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
5.10
VIN = 12V
VO(VREG5) - Output Voltage - V
VO(VREG3) - Output Voltage - V
VIN = 12V
3.35
3.30
3.25
5.05
5.00
4.95
4.90
3.20
0
2
4
6
8
0
10
20
40
60
80
100
IO(VREG5) - Output Current - mA
IO(VREG3) - Output Current - mA
Figure 10.
Figure 11.
SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
FORWARD VOLTAGE OF BOOST SW
vs
JUNCTION TEMPERATURE
0.25
330
320
0.20
V(FBST) - Forward Voltage - V
f(SW) - Switching Frequency - kHz
RF = 330kΩ
310
300
290
0.10
0.05
280
270
-50
0.15
0
50
100
150
0.00
-50
TJ - Junction Temperature - °C
Figure 12.
12
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0
50
100
150
TJ - Junction Temperature - °C
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
VBST LEAKAGE CURRENT
vs
JUNCTION TEMPERATURE
150
1.5
130
1.2
Ilkg - VBST Leakage Current - μA
OVP/UVP Threshold - %
OVP/UVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
OVP
110
90
70
0.9
0.6
0.3
UVP
50
-50
0.0
-50
TJ - Junction Temperature - °C
0
50
100
TJ - Junction Temperature - °C
Figure 14.
Figure 15.
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
0
50
100
150
66
V(OCL-LV) - Current Limit Threshold - mV
V(OCL-ULV) - Current Limit Threshold - mV
37
35
CSN = 1V
CSN = 5V
33
31
CSN = 12V
29
27
25
-50
150
0
50
100
150
64
CSN = 1V
CSN = 5V
62
60
CSN = 12V
58
56
54
-50
TJ - Junction Temperature - °C
Figure 16.
0
50
100
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TJ - Junction Temperature - °C
Figure 17.
13
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.3-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.40
5.10
CCM
VO2 - 3.3-V Output Voltage - V
VO1 - 5-V Output Voltage - V
CCM
5.05
IO = 0A
5.00
IO = 3A
4.95
IO = 6A
4.90
5
10
15
20
3.35
IO = 0A
IO = 3A
3.30
IO = 6A
3.25
3.20
25
5
VI - VIN Input Voltage - V
10
15
25
VI - VIN Input Voltage - V
Figure 19.
Figure 18.
5-V EFFICIENCY
vs
OUTPUT CURRENT
5-V EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 7 V
Auto-skip
90
80
OOA
VIN = 12 V
h - Efficiency - %
h - Efficiency - %
20
60
40
80
VIN = 21 V
70
60
20
CCM
Auto-skip
VIN = 12V
0
0.001
14
0.01
0.1
1
IO1 - 5-V Output Current - A
Figure 20.
10
50
0.001
0.01
0.1
1
10
IO1 - 5-V Output Current - A
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 7 V
Auto-skip
90
80
h - Efficiency - %
h - Efficiency - %
VIN = 12 V
OOA
60
40
5-V Switcher ON
(Auto-skip)
20
CCM
80
VIN = 21 V
70
Auto-skip
60
50
5-V Switcher ON
(Auto-skip)
VIN = 12V
0
0.001
0.01
0.1
1
40
0.001
10
0.01
0.1
1
Figure 22.
Figure 23.
5-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
3.3-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
400
400
VIN = 12V
VIN = 12V
350
f(SW) - Swithching Frequency - kHz
350
f(SW) - Swithching Frequency - kHz
10
IO2 - 3.3-V Output Current - A
IO2 - 3.3-V Output Current - A
CCM
300
250
200
OOA
150
100
CCM
300
250
200
OOA
150
100
50
50
Auto-skip
Auto-skip
0
0
0
0.5
1
1.5
IO1 - 5-V Output Current - A
Figure 24.
2
0
0.5
1
1.5
IO2 - 3.3-V Output Current - A
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
5.10
Current Mode
Rgv = 10k
VIN = 12V
OOA
5.05
VO2 - 3.3-V Output Voltage - V
VO1 - 5-V Output Voltage - V
Current Mode
Rgv = 10k
VIN = 12V
Auto-skip
5.00
CCM
4.95
4.90
Auto-skip
3.30
CCM
3.25
3.20
0
1
2
3
4
IO1 - 5-V Output Current - A
Figure 26.
5
OOA
3.35
6
0
1
2
3
4
IO2 - 3.3-V Output Current - A
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
5.10
D-CAP mode
Rgv = 10k
Cout-ESR = 18mW
VIN = 12V
D-CAP mode
Rgv = 10k
Cout-ESR = 40mW
VIN = 12V
OOA
5.05
VO2 - 3.3-V Output Voltage - V
VO1 - 5-V Output Voltage - V
6
Figure 27.
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
Auto-skip
5.00
CCM
4.95
4.90
3.35
OOA
Auto-skip
3.30
CCM
3.25
3.20
0
16
5
1
2
3
4
IO1 - 5-V Output Current - A
Figure 28.
5
6
0
1
2
3
4
IO2 - 3.3-V Output Current - A
5
6
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
5.0-V START-UP WAVEFORMS
3.3-V START-UP WAVEFORMS
EN1 (5V/div)
EN2 (5V/div)
VO1 (2V/div)
VO2 (2V/div)
PGOOD1 (5V/div)
PGOOD2 (5V/div)
VIN=12V
Iout=6A
VIN=12V
Iout=6A
t - Time - 1ms/div
Figure 30.
t - Time - 1ms/div
Figure 31.
5.0-V SOFT-STOP WAVEFORMS
3.3-V SOFT-STOP WAVEFORMS
EN1 (5V/div)
EN2 (5V/div)
VO1 (5V/div)
VO2 (5V/div)
PGOOD1 (5V/div)
PGOOD2 (5V/div)
DRVL1 (5V/div)
DRVL2 (5V/div)
t - Time - 1ms/div
Figure 32.
t - Time - 1ms/div
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
5.0-V LOAD TRANSIENT RESPONSE
3.3-V LOAD TRANSIENT RESPONSE
VO2 (100mV/div)
VO1 (100mV/div)
IIND(5A/div)
IIND(5A/div)
IO1 (5A/div)
t - Time - 100 ms/div
Figure 35.
t - Time - 100 ms/div
Figure 34.
5.0-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
3.3-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
Phase
40
Gain - dB
20
Gain
0
180
80
135
60
90
40
45
20
0
Phase - °
Gain - dB
80
60
180
135
Phase
90
Gain
45
0
0
-20
-45
-20
-45
-40
-90
-40
-90
-135
-60
-180
-80
100
VIN = 12V
Current mode
-60
-80
100
1K
10K
100K
1M
VIN = 12V
Current Mode
f - Frequency - kHz
Figure 36.
18
IO2 (5A/div)
VIN=12V, Auto-skip
Phase - °
VIN=12V, Auto-skip
-135
-180
1K
10K
f - Frequency - kHz
100K
1M
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
5.0-V SWITCH-OVER WAVEFORMS
VREG5 (100mV/div)
VO1 (100mV/div)
t - Time - 2ms/div
Figure 38.
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DETAILED DESCRIPTION
ENABLE AND SOFT START
When EN is Low, the TPS51220 is in the shutdown state. The 3.3-V LDO only stays alive, and consumes 7 μA
(typically). When EN becomes High, the TPS51220 is in the standby state. The 2-V reference and the 5-V LDO
become enabled, and consume approximately 80 μA with no load condition, and are ready to turn on SMPS
channels. Each SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51220
begins softstart, and ramps up the output voltage from zero to the target voltage with 0.96 ms. However, if a
slower soft-start is required, an external capacitor can be tied from the ENx pin to GND. In this case, the
TPS51220 charges the external capacitor with the integrated 2-μA current source. An approximate external softstart time would be tEX-SS = CEX / IEN12, which means the time from ENx = 1V to ENx = 2V. The recommend
capacitance is more than 2.2nF.
1) Internal
Soft-start
EN1
Vout1
200ms
960ms
EN11V
2) External
Soft-start
EN1
External
Soft-start
time
Vout1
Figure 39. Enable and Soft-start Timing
Table 1. Enable Logic States
EN
EN1
EN2
VREG3
VREF2
VREG5
CH1
CH2
GND
Don’t Care
Don’t Care
ON
Off
Off
Off
Off
Hi
Lo
Lo
ON
ON
ON
Off
Off
Hi
Hi
Lo
ON
ON
ON
ON
Off
Hi
Lo
Hi
ON
ON
ON
Off
ON
Hi
Hi
Hi
ON
ON
ON
ON
ON
Pre-Biased Startup
The TPS51220 supports a pre-biased start up by preventing negative inductor current during soft-start in the
condition the output capacitor has some charge. The initial DRVH signal waits until the voltage feedback signal
becomes greater than the internal reference ramping up by soft-start function. After that, the start-up manner is
the same as the way of fully discharged soft start condition. This manner is regardless of the SKIPSELx
selection.
20
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3.3V, 10mA LDO (VREG3)
A 3.3-V, 10mA, linear regulator is integrated in the TPS51220. This LDO services some of the analog supply rail
for the device and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-μF (at least 1-μF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the
device.
2V, 100μA Sink/ Source Reference (VREF2)
This voltage is used for the reference of the loop compensation network. Apply a 0.22-μF (at least 0.1-μF), high
quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND in adjacent to the device.
5.0V, 100mA LDO (VREG5)
A 5.0-V, 100mA, linear regulator is integrated in the TPS51220. This LDO services the main analog supply rail
for the device and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-μF
(at least 4.7-μF), high quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the
device.
VREG5 SWITCHOVER
When EN1 is high, PGOOD1 indicates GOOD and more than 4.7 V is applied to V5SW, the internal 5-V LDO is
shut off and the VREG5 is shorted to V5SW by an internal MOSFET after a 7.7-ms delay. When the V5SW
voltage becomes lower than 4.5 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is turned
off and the internal 5-V LDO resumes immediately
BASIC PWM OPERATIONS
The main control loop of the SMPS is designed as a fixed frequency, pulse width modulation (PWM) controller. It
supports two control schemes; a peak current mode and a proprietary D-CAP mode. Current mode achieves
stable operation in any type of capacitors including low ESR capacitor(s) such as ceramic or specialty polymer
capacitors. D-CAP mode does not require an external compensation circuit, and is suitable for relatively larger
ESR capacitor(s) configuration. These control schemes are selected with FUNC-pin; see Table 4.
CURRENT MODE
The current mode scheme uses the output voltage information and the inductor current information to regulate
the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the
internal 1V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The
inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage goes down, the TPS51220 increases the target inductor current to raise the output voltage, on
the other hand, if the output voltage goes up the TPS51220 decreases the target inductor current to reduce the
output voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The highside MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the controller
regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each OFF state to
keep the conduction loss minimum.
D-CAP™ MODE
With the D-CAP mode operation, the PWM comparator compares VREF2 with the combination value of the
COMP voltage, VFB-AMP output, and the ramp compensation signal. When the both signals are equal at the
peak of the voltage sense signal, the comparator provides the OFF signal to the high-side MOSFET driver.
Because the compensation network is implemented on the part and the output waveform itself is used as the
error signal, external circuit is simplified. Another advantage is its inherent fast transient response. A trade-off is
a sufficient amount of ESR required in the output capacitor. The D-CAP™ mode is suitable for relatively larger
output ripple voltage application. The inductor current information is used for the overcurrent protection and light
load operation.
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PWM FREQUENCY CONTROL
The TPS51220 has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1.
1 × 105
fsw éëkHz ùû =
RF ëékΩ ûù
(1)
TPS51220 can also synchronize to more than 2.5-V amplitude external clock by applying the signal to the RF
pin. The set timing of channel-1 initiates at the raising edge (1.3 V typ) of the clock and channel-2 initiates at the
falling edge (1.1 V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
When the external clock synchronization is selected, the following actions are required.
• Remove RF resistor
• Add clock signal before EN1 or EN2 turning on.
TPS51220 can NOT support switching frequency change on the fly (from f
vice versa).
SW
set by RF-resistor to ex-clock, nor
1000
900
fSW - Frequency - kHz
800
700
600
500
400
300
200
100
0
100
200
300
400
500
RF - Resistance - kW
Figure 40. Switching Frequency vs RF
22
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LIGHT LOAD OPERATION
The TPS51220 automatically reduces switching frequency at light load condition to maintain high efficiency if
Auto Skip or Out-of-Audio mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping
pulses. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its peak touches a predetermined current, ILL(PEAK), which indicates the
boundary between heavy load and light load conditions. Once the top MOSFET is turned on, the TPS51220 does
not allow it to be turned off until it touches ILL(PEAK). This eventually causes an overvoltage condition to the output
and pulse skipping. From the next pulse after zero-crossing is detected, ILL(PEAK) is limited by the ramp down
signal which starts from 25% of the overcurrent limit setting (IOCL(PEAK): see the current protection session) toward
5% of IOCL(PEAK) over one switching cycle to prevent causing large ripple. The transition load point to the light load
operation ILL(DC) can be calculated as shown in Equation 2 and Equation 3.
I LL(DC) + I LL(PEAK) * 0.5 I IND(RIPPLE)
(2)
(V - VOUT ) × VOUT
1
IIND(RIPPLE) =
× IN
L × fSW
VIN
where
•
fSW is the PWM switching frequency which is determined by RF resistor setting or external clock
(3)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportional to the output current from the ILL(DC) given above; however, as the switching is
synchronized with clock. Due to the synchronization, the switching waveform in boundary load condition (close to
ILL(DC)) appears as a sub-harmonic oscillation; however, it is the intended operation.
If SKIPSELx is tied to GND, the TPS51220 works on a constant frequency of fSW regardless its load current.
Inductor
Current
ILL(PEAK)
ILL(DC)
IIND(RIPPLE)
0
Time
Figure 41. Boundary Between Pulse Skipping and CCM
ILL(PEAK)Ramp = (0.25-0.2 ×
VOUT
) × IOCL(PEAK)
VIN
(4)
Inductor
Current
25% of IOCL(PEAK)
ILL(PEAK) Ramp signal
ILL(PEAK)
5% of IOCL(PEAK)
0
Time
ton
1/fSW
Figure 42. Inductor Current Limit at Pulse Skipping
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TPS51220
SLVS785C – OCTOBER 2007 – REVISED JULY 2009
www.ti.com
Table 2. Skip Mode Selection
SKIPSELx
OPERATING MODE
GND
Continuous Conduction
VREF2
VREG3
VREG5
Auto Skip
OOA Skip (max 7 skips,
for
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