TPS51313DRCR

TPS51313 www.ti.com.cn ZHCSAE8 – SEPTEMBER 2012 5V 输入或 3.3V 输入，3A 完全集成转换器 查询样品: TPS51313 特性 应用范围 1 • • • • • • • • 234 输入电压 VIN 范围：3.1V 至 5.5V 偏置电压 VCC 范围：3.1V 至 5.5V 输出电压范围：0.6V 至 3.3V 0.6V， ，1% 电压基准精度 开关频率：1MHz 无需外部补偿 固定电压伺服器软启动功能 过热保护 X • • 说明 FB 1 10 VCC 2 9 PGOOD VIN 3 8 NC PGND 4 7 SW PGND 5 6 SW Thermal Pad 离散图形 PCIe® PEX 轨 低压负载点 (POL) 电源轨 TPS51313 是一款针对低压负载点应用的易于使用 的、完全集成、同步降压转换器。 它被设计成符合 NVIDIA ™ OpenVreg 类型 0 技术规范，其中包括对封 装和封装尺寸的要求。 它在输出电压介于 0.6V 至 3.3V 之间时支持 3A（最大值）直流输出电流。 DCAP2™ 模式适应、恒定接通时间控制（开关频率 1MHz）可在使用全陶瓷输出电容器设计时实现小封装 尺寸并提供一个低外部组件数量。 此器件还在轻负载 条件下特有自动跳跃功能、预偏置启动和内部固定软启 动时间。 当器件被禁用时，输出电容器通过内部电阻 器放电。 TPS51313 采用 3mm × 3mm，10 引脚 DRC 封装（符合 RoHs 环保标准且无铅），额定温度 范围为 -10°C 至 85°C。 EN X 简化的应用 CFF R1 R2 TPS51313 FB EN VCC VIN 3.3 or 5V EN PGOOD VIN NC PGND SW PGND SW C IN PGOOD LOUT VOUT Thermal Pad COUT UDG-12083 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2 is a trademark of Texas Instruments. NVIDIA is a trademark of NVIDIA, Incorporated. PCIe is a registered trademark of PLX Technology, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated English Data Sheet: SLUSB31 TPS51313 ZHCSAE8 – SEPTEMBER 2012 www.ti.com.cn This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) ORDERABLE DEVICE NUMBER TA PACKAGE –10°C to 85°C Plastic SON (DRC) (1) TPS51313DRCR TPS51313DRCT PINS 10 OUTPUT SUPPLY MINIMUM QUANTITY Tape and reel 3000 Mini reel 250 ECO PLAN Green (RoHS and no Pb/Br) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE Input voltage range (2) Output voltage range (2) MIN MAX VIN, VCC –0.3 6.0 SW –2.0 6.0 SW (transient 20nsec) -3.0 8.5 EN –0.3 6.0 FB –1 3.6 PGOOD –0.3 Junction temperature, TJ Storage temperature, Tstg (1) (2) –55 UNIT V 6.0 V 125 °C 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. THERMAL INFORMATION TPS51313 THERMAL METRIC (1) UNITS DRC (10-PIN) θJA Junction-to-ambient thermal resistance 42.4 θJCtop Junction-to-case (top) thermal resistance 53.9 θJB Junction-to-board thermal resistance 18.1 ψJT Junction-to-top characterization parameter 1.1 ψJB Junction-to-board characterization parameter 18.3 θJCbot Junction-to-case (bottom) thermal resistance 6.3 °C/W spacer - so note to thermal table has space between the note and ROC table title (1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。 RECOMMENDED OPERATING CONDITIONS Input voltage range Output voltage range MIN MAX VIN, VCC –0.1 5.5 SW –0.1 5.5 EN –0.1 5.5 FB –0.1 3.5 PGOOD –0.1 5.5 V –10 85 °C Operating free-air temperature, TA 2 UNIT V Copyright © 2012, Texas Instruments Incorporated TPS51313 www.ti.com.cn ZHCSAE8 – SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS Over operating free-air temperature range, VIN = 5 V, VCC = 5 V, VEN = 3.3 V (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY VOLTAGE VIN Supply voltage 3.1 5.5 V VCC Supply voltage 3.1 5.5 V SUPPLY CURRENT IIN Input voltage supply current EN = High 100 μA ISD Input voltage shutdown current EN = Low 12 μA IVCC(in) VCC supply current EN = High IVCC(sd) VCC shutdown current EN = Low, TA = 25°C μA 700 20 μA VFB REFERNCE VOLTAGE VFBREF Reference voltage VFBREFTOL Reference voltage tolerance IFB Feedback pin leakage current 0.6 TA = 25°C V –1% 1% –100 100 nA SMPS FREQUENCY fSW Switching frequency tOFF(min) Minimum off-time tDEAD Deadtime (1) EVM close loop measurement. VIN = 5 V, VOUT = 1.05 V, IOUT = 3 A 1 110 190 SW node high, VIN = 5 V 9 SW node low, VIN = 5 V 10 MHz 270 ns ns LOGIC THRESHOLD VLL EN low-level voltage VLH EN high-level voltage 0.8 ILLK EN input leakage current VIN = VCC = 3.3 V Soft-start time (1) VFB rising from 0 V to 0.6 V 1.5 –3 V V 1 3 μA SOFT START tSS 300 µs PGOOD COMPARATOR VPGTH PGOOD threshold tPGDLY PGOOD high delay time IPGLK PGOOD leakage current PGOOD out to higher w/r/t VFB 130% PGOOD out to lower w/r/t VFB 50% Delay for PGOOD in, after EN = Hi 1.3 –1 0 ms 1 μA CURRENT DETECTION IOCL Current limit threshold Valley current limit, VIN = VCC = 3.3 V, TA = 25°C 4.8 A PROTECTIONS VIN_UVLO VIN UVLO threshold voltage Wake-up 2.85 2.95 3.05 Shutdown 2.6 2.7 2.8 Wake-up 2.85 2.95 3.05 Shutdown 2.6 2.7 2.8 V VCC_UVLO VCC UVLO threshold voltage VOVP OVP threshold voltage OVP detect voltage, overdrive = 100 mV tOVP OVP delay time Overdrive = 100 mV VUVP UVP threshold voltage UVP detect voltage, overdrive = 100 mV tUVPDLY UVP delay time Overdrive = 100 mV 2.4 µs EN = Lo 260 Ω Shutdown temperature 145 130% 1.9 µs 50% SW PULL DOWN RSWPD Switch node pull down resistance THERMAL SHUTDOWN TSDN (1) Thermal shutdown threshold (1) Hysteresis 20 °C Specified by design. Not production tested. Copyright © 2012, Texas Instruments Incorporated 3 TPS51313 ZHCSAE8 – SEPTEMBER 2012 www.ti.com.cn DEVICE INFORMATION Functional Block Diagram TPS51313 VREF – 50% + PGOOD UV VBG Delay VREF VREF + 30% + OV UVP FB Σ + VSW OVP + ENOK EN 1.5 V/ 0.8 V Control Logic PWM + IGAIN + · · · · · On/Off Time Minimum On /Off SKIP Mode OCL/OVP/UVP Discharge + VCCOK VCC UVLO VCC 2.95 V/ 2.7 V + VINOK VIN UVLO 2.95 V/2.7 V VIN VBG OC + + tON One Shot XCON SW + ZC Discharge PGND UDG-12112 4 Copyright © 2012, Texas Instruments Incorporated TPS51313 www.ti.com.cn ZHCSAE8 – SEPTEMBER 2012 DRC PACKAGE 10 PINS (TOP VIEW) FB 1 10 VCC 2 9 PGOOD VIN 3 8 NC PGND 4 7 SW PGND 5 6 SW Thermal Pad EN . . PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION EN 10 I Enable function for the switched-mode power supply (SMPS) (3.3-V logic compatible) FB 1 I Voltage feedback. Also used for OVP, UVP and PGOOD determination. NC 8 I No connect. Make no external connection to this pin. I Device ground O Power good indicator. Requires external pull-up resistor. I Switching node output. Connect to external inductor. Also serve as current sensing negative input for over current protection purpose PGND PGOOD SW 4 5 9 6 7 VCC 2 VIN 3 Thermal Pad I Power supply for analog circuit. Main power conversion input and gate-drive voltage supply for output FETs. Connect to PGND. Copyright © 2012, Texas Instruments Incorporated 5 TPS51313 ZHCSAE8 – SEPTEMBER 2012 www.ti.com.cn TYPICAL CHARACTERISTICS 90 1.070 80 1.065 Output Voltage (V) Efficiency (%) 70 60 50 40 VOUT = 1.05 V VIN = 3.3 V fSW = 1 MHz 30 20 0.001 0.01 0.1 Output Current (A) 1 VIN = 3.3 V fSW = 1 MHz 1.060 1.055 1.050 1.045 1.040 0.0 3 0.5 1.0 1.5 2.0 Output Current (A) G000 Figure 1. Efficiency vs. Output Current 2.5 3.0 G001 Figure 2. DC Load Regulation 400 60 VIN =3.3 V ILOAD = 3 A VVOUT = 1.05 V fSW = 1 MHz 40 350 300 200 150 0 Phase (°) Gain (dB) 250 20 100 50 −20 Magnitude −40 100 1000 0 Phase 10000 100000 Frequency (Hz) 1000000 −50 10000000 G001 Figure 3. Bode Plot Figure 4. Fast 0-A to 3-A Transient Response 6 Figure 5. Slow 0-A to 3-A Transient Response Copyright © 2012, Texas Instruments Incorporated TPS51313 www.ti.com.cn ZHCSAE8 – SEPTEMBER 2012 APPLICATION INFORMATION Functional Overview TPS51313 is a D-CAP2 mode adaptive on time converter with internal integrator. Monolithically integrate high side and low side FET supports output current to a maximum of 3-ADC. The converter automatically runs in discontinuous conduction mode to optimize light load efficiency. A switching frequency of 1-MHz enables optimization of the power train for the cost, size and efficiency performance of the design. PWM Operation The PWM operation is comprised of three separate loops, A, B and C as shown in Figure 6. L OUT VIN C OUT + – R LOAD Integrator VCS PWM Comparator Q S Q R Σ VC + + R1 + gM VFB R2 VREF + – tON OneShot + – B C RA R 11 CSN K1 + CA RB CSP R12 CB A UDG-12113 Figure 6. PWM Operation Internal Current Loop (A) Loop A is the internal current loop. The current information is sampled, divided and averaged at the SW node. The RC time constant and the gain of the current sense amplifier is chosen to cover the wide range of power stage design intended for this application. Internal Voltage Loop (B) Loop B is the internal voltage loop. The feedback voltage information is compared to the voltage reference at the input of the gM amplifier, the internal integrator is designed to provide a zero at the double pole location to boost phase margin at the desired crossover frequency. Copyright © 2012, Texas Instruments Incorporated 7 TPS51313 ZHCSAE8 – SEPTEMBER 2012 www.ti.com.cn Fast Feedforward Loop (C) Loop C is the additional loop that acts a direct fast feedforward loop to enhance the transient response. In steady state operation as shown in Figure 7, the on time is initiated by the interaction of the three loops mentioned above. When the (VC– VCS) is rising above threshold defined by (VFB – VREF), the PWM comparator issues the on time pulse after the propagation delay. The demand of on time occurs when the artificial current has reached the valley point. The load regulation is maintained by the integrator provided by the gM amplifier and internal integrator. In transient operation as shown in Figure 8, the benefit of this topology is becoming evident. In an all MLCC output configuration, especially when the output capacitance is low, when the load step is applied, the output voltage is immediately discharged to try to keep the load demand. The immediate reflection of the load demand is instantly reflected in the FB voltage. The (VFB – VREF) is thus served as a termination voltage level for the (VC – VCS), thus modulating the initiation of the on time. The transient response can be improved further by amplifying the difference between VFB and the VREF reference. VFB–VREF ILOAD VC – VCS IL tON PWM PWM delay ~100 ns PWM IL VFB –VREF VOUT VC – VCS UDG-12114 Figure 7. Steady-State Operation UDG-12115 Figure 8. Transient Operation PWM Frequency The TPS51313 operates at a switching frequency of 1 MHz. Light Load Power Saving Features The TPS51313 offers an automatic pulse-skipping feature to provide excellent efficiency over the entire load range. The converter senses the current when the low-side FET is on and prevents negative current flow by turning off the low side FET. This saves power by eliminating re-circulation of the inductor current. When the bottom FET is turned off, the converter enters discontinuous mode, and the switching frequency decreases, reducing switching loss. Power Sequences TPS51313 initiates the soft-start process when the EN, VIN and VCC pins are ready. The soft-start time 300 µs when the reference voltage is between 0 V and 0.6 VREF. The actual output ramp-up time is the same as that of the VREF start-up time, which is 300 µs. Power Good Signal The TPS51313 has one open-drain power good (PGOOD) pin. During initial startup, there is a 1.3-ms power good high propagation delay after EN goes high. The PGOOD de-asserts when the EN is pulled low or an undervoltage condition on VCC or VIN or any other faults (such as VOUT, UVP, OCP, OVP) that require latch off action is detected. Protection Features The TPS51313 offers many features to protect the converter power chain as well as the system electronics. 8 Copyright © 2012, Texas Instruments Incorporated TPS51313 www.ti.com.cn ZHCSAE8 – SEPTEMBER 2012 Input Undervoltage Protection on VCC and VIN (UVLO) The TPS51313 continuously monitor the voltage on the VCC and VIN to ensure the voltage level is high enough to bias the converter properly and to provide sufficient gate drive potential to maintain high efficiency for the converter. The converter starts with VCC and VIN approximately 2.95 V and has a nominal of 250 mV of hysteresis, assuming EN is above the logic threshold level. If the UVLO level is reached for either VCC or VIN, the converter transitions the SW node into a tri-state and remains off until the device is reset by both VCC and VIN reaches 2.95 V (nominal). The PGOOD is deasserted when UVLO is detected and remains low until the device is reset. The device resumes operation when VIN recoveres to 2.95 V (nominal). Output Overvoltage Protection (OVP) The TPS51313 has OVP protection circuit. An OVP event is detected when the FB voltage is approximately 130% x 0.6VREF. In this case, the converter de-asserts the PGOOD signal and performs the overvoltage protection function. The converter latches off both high-side and low-side FET (after a typical delay of 1.9 µs) and remains in this state until the device is reset by EN, or VCC or VIN. Output Undervoltage Protection (UVP) Output undervoltage protection works in conjunction wit the current protection described in the Overcurrent and Current Limit Protection section. If the FB voltage drops below 50% x 0.6 VREF, after a delay of 2.4 µs, the converter latches off. Undervoltage protection can be reset by EN, VCC or VIN. Overcurrent and Current Limit Protection The TPS51313 provides an overcurrent protection function. The minimum OCP level is 4.8-A DC. When the current limit is exceeded for consecutive 9 cycles, the converter latches off and remains latched off until it is reset by EN, VCC or VIN. The TPS51313 also provides current limit protection function. If the sense current is above the OCL setting, the converter delays the next on pulse until the current level drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. During a fast or very fast overcurrent event, the output voltage tends to droop until the UVP limit is reached. Then the converter de-asserts the PGOOD signal, and latches off after a delay between 1 µs and 2 µs . The converter remains in this state until the device is reset by EN, VCC or VIN. Thermal Protection The TPS51313 has an internal temperature sensor. When the die temperature reaches a nominal of 145°C, the device shuts down until the temperature cools by approximately 20°C. Then the converter restarts. The thermal shutdown is an non-latched behavior. Copyright © 2012, Texas Instruments Incorporated 9 TPS51313 ZHCSAE8 – SEPTEMBER 2012 www.ti.com.cn REFERENCE DESIGN Application Schematic This section describes a simplified design procedure for a discrete graphics processor PEX rail application using the TPS51313 converter. Figure 9 shows the application schematic.. CFF R1 R2 TPS51313 FB EN VCC VIN 3.3 or 5V EN PGOOD VIN NC PGND SW PGND SW C IN PGOOD LOUT VOUT COUT Thermal Pad UDG-12083 Figure 9. Reference Design Schematic Table 1. Reference Design List of Materials FUNCTION MANUFACTURER PART NUMBER Output Inductor Vishay IHLP-1212AB-11 Ceramic Output Capacitors Panasonic ECJ2FB0J226M Murata GRM21BR60J226ME39L Design Procedure Step One. Determine the specifications. . The PEX rail requirement provides the following key paramaters. • VOUT = 1.05 V • ICC(max) = 3 A • ΔI = 2A (transient load step and release) • di/dt = 2.5A/µs Step Two. Determine the system parameters. The input voltage range and operating frequency are of primary interest. For example, • VIN = VCC = 3.3 V • fSW = 1 MHz. • Maximum height of power chain components = 1.2 mm 10 Copyright © 2012, Texas Instruments Incorporated TPS51313 www.ti.com.cn ZHCSAE8 – SEPTEMBER 2012 Step Three. Set the output voltage. Use Equation 1 to determine the output voltage. VOUT = VREF ´ (R1 + R2 ) R2 (1) The output voltage is determined by 0.6-V votlage reference and the resistor dividers (R1 and R2). The output voltage is regulated to the FB pin. For this VOUT = 1.05 V, reference design, select R1 = 30 kΩ and R2 = 40 kΩ. (see Figure 9) To improve signal-to-noise performance of the converter, add a small feedforward capacitor (typically approximately 27 pF or less) in parallel with the upper resistor (R1). Step Four. Determine inductor value and choose inductor. Smaller inductance yields better transient performance but the consequence is higher ripple and lower efficiency. Higher values have the opposite characteristics. It is common practice to limit the ripple current to 25% to 50% of the maximum current. In this case, use 40%: IP-P = 3 A ´ 0.4 = 1.2 A where • • • L= fSW = 1 MHz VIN = 3.3 V VOUT = 1.05 V (2) ö V ´ dT æ (VIN - VOUT ) ö æ VOUT =ç ÷´ç ÷ = 0.596 mH ç ÷ ç (fSW ´ VIN ) ÷ IP-P IP-P è ø è ø (3) For this application, a 0.56-µH, 18.7-mΩ inductor from Vishay with part number IHLP-1212AB-11 is chosen. Maximum height for this inductor is 1.2 mm. Step Five. Determine the output capacitance. To determine COUT based on transient and stability requirement, first calculate the minimum output capacitance for a given transient. Equation 4 and Equation 5 calculate the minimum output capacitance for meeting the transient requirement, which is 33.8-µF assuming a ±3% voltage allowance for load step and release. æV ö ´t L ´ DILOAD(max )2 ´ ç VOUT SW + tMIN(off ) ÷ ç VIN(min ) ÷ è ø COUT(min_ under ) = ææ V ö ö IN(min ) - VVOUT ÷ ÷ ´ tSW - t 2 ´ DVLOAD(insert ) ´ ç ç MIN(off ) ÷ ´ VVOUT çç ÷ VIN(min ) ø èè ø COUT(min_ over ) = ( LOUT ´ DILOAD(max ) (4) 2 ) 2 ´ DVLOAD(release ) ´ VVOUT (5) This design uses 3 22-µF capacitors with consideration of the MLCC derating effect (60% derating for both AC and DC effect). Step Six. Establishing the internal compensation loop. The TPS51313 is designed with an internal compensation loop. The internal integrator zero location is approximately 60 kHz. When the power stage double pole frequency contributed by the LOUT and COUT is less than or equal to that of the zero frequency location, the converter is stable with sufficient margin. Step Seven. Select decoupling and peripheral components. For TPS51313 peripheral capacitors use the following minimum value of ceramic capacitance, X5R or better temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always appropriate. Copyright © 2012, Texas Instruments Incorporated 11 TPS51313 ZHCSAE8 – SEPTEMBER 2012 www.ti.com.cn VCC and VIN decoupling ≥ 2 × 10 µF, 6.3 V Pull up resistor on PGOOD = 100 kΩ Step Eight. (Optional) Snubber design for optimizing maximum switch node ringing. For TPS51313 layout design, if the maximum switch node voltage is above 8.5 V for 20 ns, snubber circuit is recommended to limit the maximum voltage to be within the absolute maximum voltage rating (see Absolute maximum rating table on page 2). A series combination of R and C (where the value of R is approximately 2.2 Ω, and the value of C is approximately 470 pF) from SW node to PGND can be added to achieve effective snubbing for SW node. Layout Considerations Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout. • Widen the PGND connection area as much as possible. • Place VIN, VCC decoupling capacitors as close to the device as possible. • Use wide traces for the VIN, SW and PGND pins. These nodes carry high current and also serve as heat sinks. • Place FB and voltage setting dividers as close to the device as possible. 12 Copyright © 2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 7-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS51313DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -10 to 85 S51313 Samples TPS51313DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -10 to 85 S51313 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of