TPS51362RVER

TPS51362 www.ti.com SLUSBB6A – FEBRUARY 2013 – REVISED JUNE 2013 22-V Input, 10-A Integrated FET Converter With Ultra-Low Quiescent ( ULQ™) Check for Samples: TPS51362 FEATURES APPLICATIONS • • • • • • • 1 2 • • • • • • • • • Input Voltage Range: 3 V to 22 V Output Voltage Range: 0.6 V to 2 V 10-A Integrated FET Converter Fewest External Components ULQ™-100 Mode of Operation to Enable Long Battery Life During System Standby Soft-Start Time Programmable by External Capacitor Switching Frequency: 800 kHz D-CAP2™ Architecture to Enable POSCAP and All MLCC Output Capacitor Usage Integrated and Temperature Compensated Low-Side On-Resistance Sensing for Accurate OCL Protection Powergood Output OCL, OVP, UVP and UVLO Protections Thermal Shutdown (non-latch) Output Discharge Function Integrated Boost MOSFET Switch 28-Pin, 3.5-mm × 4.5-mm, RVE, QFN Package with 0.4-mm Pitch and 1-mm Height Notebook Computers (VCCIO) Memory Rails (DDR VDDQ) DESCRIPTION The TPS51362 is a high-voltage input, synchronous converter with integrated FET, based on DCAP-2™ control topology, which enables fast transient response and supports both POSCAP and all MLCC output capacitors. TI proprietary FET technology combined with TI leading-edge package technology provides the highest density solution for single-output power rail such as VCCIO and VDDQ for DDR notebook memory, or any point-of-load (POL) in wide application. The key feature of the TPS51362 is its ULQ™ Mode to enable low-bias current (100 µA in low power mode, enabled by LP#). This feature is extremely beneficial for long battery life in system standby mode. The feature set includes switching frequency of 800 kHz. Programmable soft-start time with an external capacitor. auto skip, pre-bias startup, integrated bootstrap switch, power good, enable and a full suite of fault protection schemes, including OCL, UVP, OVP, 5-V UVLO and thermal shutdown. It is packaged in 3.5 mm × 4.5 mm, 0.4-mm pitch, 28pin QFN (RVE), and specified from -10°C to 85°C. SIMPLIFIED APPLICATION VSNS GSNS 23 22 21 GSNS VSNS SLEW 20 19 TRIP GND 18 17 16 15 V5 VIN VIN VIN 24 REFIN2 PGND 14 25 REFIN PGND 13 26 VREF TPS51362 PGND 12 27 NU PGND 11 28 EN PGND 10 PGOOD LP# MODE NC 1 EN PGOOD LP# VIN 7.4 V to 20 V 2 3 4 BST SW SW SW SW 5 6 7 8 9 VOUT 1.05 V UDG-13052 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ULQ, DCAP-2 are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS51362 SLUSBB6A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) TA PACKAGE –10°C to 85°C Plastic Quad Flat Pack (QFN) ORDERABLE DEVICE NUMBER TPS51362RVET TPS51362RVER (2) PINS 28 TRANSPORT MEDIA MINIMUM ORDER QUANTITY Small tape-and-reel 250 Large tape-and-reel 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE VIN UNIT MIN MAX –0.3 30 36 BST transient