TPS51396A
ZHCSNW0C – FEBRUARY 2019 – REVISED APRIL 2021
TPS51396A 具有 ULQ™ 模式、可延长电池寿命的 4.5V 至 24V、8A 同步降压稳
压器
1 特性
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输入电压范围：4.5V 至 24V
D-CAP3™ 架构控制，可实现快速瞬态响应
输出电压范围：0.6V 至 7V
1% 反馈电压精度 (25°C)
持续输出电流：8A
集成 19.5mΩ 和 9.5mΩ RDS(on) 内部电源开关
ULQ™ 运行，能够在系统待机期间延长电池寿命
Eco-Mode™ 和 OOA 模式，适用于轻负载运行（通
过 MODE 引脚选择）
600kHz、800kHz 和 1MHz 可选开关频率（通过
MODE 引脚选择）
Out-of-Audio (OOA) 轻负载运行，开关频率超过
25kHz
支持大负荷运行
可调节软启动时间（通过 SS 引脚调节）
电源正常指示器
内置输出放电功能
逐周期过流保护
锁存输出，可提供 OV 和 UV 保护
非锁存，可提供 OT 和 UVLO 保护
20 引脚 3.0mm × 3.0mm HotRod™ VQFN 封装
TPS51396A 的主要特性是其 ULQ（超低静态电流），
可实现低偏置电流和大负荷运行。该 ULQ 特性非常有
益于在低功耗运行时延长电池寿命。TPS51396A 的电
源输入电压范围为 4.5V 至 24V。该器件使用 DCAP3
控制模式来提供快速瞬态响应、良好的线路和负载调
节，无需外部补偿，并支持低等效串联电阻 (ESR) 输
出电容器，如专用聚合物和超低 ESR 陶瓷电容器。
TPS51396A 提供 OVP、UVP、OCP、OTP 和 UVLO
的全面保护。它结合了电源正常信号和输出放电功能。
可使用 TPS51396A 中的 MODE 引脚来设置 EcoMode 或 OOA 模 式 ， 从 而 实 现 轻 负 载 运 行 。 EcoMode 在轻负载运行期间可保持高效率，OOA 模式工
作时的开关频率大于 25kHz（即使没有负载也是如
此）。
TPS51396A 同时支持内部和外部软启动时间选项。它
具有 1.3ms 的内部固定软启动时间。如果应用需要更
长的软启动时间，则可以使用外部 SS 引脚，通过连接
外部电容器来实现。
TPS51396A 可采用 20 引脚 3.0mm × 3.0mm HotRod
封装，额定结温范围为 –40°C 至 125°C。
器件信息
2 应用
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封装(1)
器件型号
TPS51396A
笔记本电脑、DTV 和 STB
电信和网络、负载点 (POL)
IPC、工厂自动化
分布式电源系统
(1)
封装尺寸（标称值）
VQFN (20)
3.00mm × 3.00mm
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3 说明
TPS51396A 是一款具有集成式 FET 且具有成本效益
的高电压输入、高效率同步降压转换器。
100
L
TPS51396A
VIN
VOUT
VIN
SW
EN
VBST
95
VCC
CIN
CBST
COUT
MODE
FB
PGOOD
R2
PGOOD
VCC
90
R1
Efficiency (%)
RM_H
RM_L
85
80
75
70
VVIN=6V, VOUT=5V,FSW=600kHz
VVIN=8.4V,VOUT=5V,FSW=600kHz
VVIN=12V, VOUT=5V,FSW=600kHz
VVIN=19V, VOUT=5V,FSW=600kHz
SS
R5
C1
AGND
PGND
Could be floating
Css
65
60
0.001
典型应用
0.01
0.1
I-Load (A)
1
10
D034
效率与输出电流 ECO 模式
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEY3
TPS51396A
www.ti.com.cn
ZHCSNW0C – FEBRUARY 2019 – REVISED APRIL 2021
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 17
8.1 Application Information............................................. 17
8.2 1V Output Typical Application................................... 17
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Device Support........................................................24
11.2 接收文档更新通知................................................... 24
11.3 支持资源..................................................................24
11.4 Trademarks............................................................. 24
11.5 Electrostatic Discharge Caution.............................. 24
11.6 Glossary.................................................................. 24
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (April 2020) to Revision C (April 2021)
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首次公开发布...................................................................................................................................................... 1
更新了整个文档中的表格、图和交叉参考的编号格式......................................................................................... 1
更新了标题..........................................................................................................................................................1
Added table note to the Recommended Operating Conditions ......................................................................... 4
Changes from Revision A (April 2020) to Revision B (April 2020)
Page
• 将销售状态从“保密协议限制”更改为“选择性披露”..................................................................................... 1
Changes from Revision * (February 2019) to Revision A (April 2020)
Page
• 将销售状态从“预告信息”更改为“量产版本”................................................................................................ 1
2
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5 Pin Configuration and Functions
GND
VCC
NC
20
19
7
18
176
16
3
SW
4
SW
15
6
FB
13
AGND
7
4
3
7
VIN
14
4
3
2
3
VIN
MODE
6
1
BST
GND
VIN
4
12
EN
VIN
5
11
SS
7
8
6
9
10
SW
GND
GND
PGOOD
NC
3
7
4
6
图 5-1. RJE Package 20-Pin VQFN (Top View)
表 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BST
1
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1 μF is recommended.
VIN
2,3,4,5
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
GND.
SW
6,19,20
O
Switch node terminal. Connect the output inductor to this pin.
7,8,18,Pad
G
Power GND terminal for the controller circuit and the internal circuitry.
PGOOD
9
O
Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over
voltage or if the device is under thermal shutdown, EN shutdown or during soft start.
SS
11
I
Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.3 ms.
NC
10,16
EN
12
I
Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal pull
down current to disable converter if leave this pin open.
AGND
13
G
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
FB
14
I
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
AGND.
MODE
15
I
Llight load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND, the
different MODE options are shown in 表 7-1
VCC
17
O
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
this pin with a 1-μF capacitor.
GND
Not connect. Can be connected to GND plane for better thermal achieved.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
UNIT
VIN
–0.3
26
V
VBST
–0.3
31
V
VBST-SW
–0.3
6
V
EN, MODE, FB, SS
–0.3
6
V
PGND, AGND
–0.3
0.3
V
SW
–2
26
V
SW (10-ns transient)
–3
28
V
–0.3
6
V
PGOOD
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22- V C101(2)
VALUE
UNIT
±2000
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
Output voltage
MIN
MAX
VIN(1)
4.5
24
V
VBST
–0.3
29
V
VBST-SW
–0.3
5.5
V
EN, MODE, FB, SS
–0.3
5.5
V
PGND, AGND
–0.3
0.3
V
SW
–2
24
V
SW (10-ns transient)
–3
26
V
–0.3
5.5
V
8
A
125
°C
PGOOD
IOUT
Output current
TJ
Operating junction temperature
(1)
4
UNIT
–40
Max DC input (inlcude tolerance) should be not over 24 V.
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6.4 Thermal Information
TPS51396A
THERMAL
METRIC(1)
RJE (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
44.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.3
°C/W
RθJB
Junction-to-board thermal resistance
13.3
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
13.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
16.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
VIN
IVIN
VIN supply current
No load, VEN = 3.3 V, Switching
IVINSDN
Shutdown supply current
No load, VEN = 0 V
4.5
24
V
90
uA
2
uA
VCC OUTPUT
VCC
VCC output voltage
ICC
VCC current limit
VVIN > 5.0 V
4.85
VVIN = 4.5 V
5
5.15
4.5
V
V
20
mA
FEEDBACK VOLTAGE
VFB
FB voltage
TJ = 25°C
594
600
606
mV
TJ = -40°C to 125°C
592
600
611
mV
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching frequency
TJ = 25°C , FSW = 600 kHz,Vo = 1 V
TON(MIN)
SW minumum on time
TJ = 25°C
TOFF(MIN)
SW minimum off time
TJ = 25°C, VFB = 0.5 V
600
kHz
60
ns
190
ns
MOSFET and DRIVERS
RDS(ON)H
High side switch resistance
TJ = 25°C
19.5
mΩ
RDS(ON)L
Low side switch resistance
TJ = 25°C
9.5
mΩ
28
us
OOA FUNCTION
TOOA
OOA mode operation period
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
TJ = 25°C, VEN = 0 V
420
Ω
TSS
Soft start time
Internal soft-start time, SS floating
1.3
ms
ISS
Soft start charge current
5
uA
POWER GOOD
TPGDLY
PG start-up delay
PG from low to high
1
ms
85
%
VFB rising (good)
90
%
VFB rising (fault)
115
%
VFB falling (good)
110
VFB falling (fault)
VPGTH
PG threshold
VPG_L
PG sink current capability
IOL = 4 mA
IPGLK
PG leak current
VPGOOD = 5.5 V
%
0.4
V
1
uA
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TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
8.1
9.8
12
UNIT
CURRENT LIMIT
IOCL
Over current threshold
INOCL
Negative over current threshold
Valley current set point
3.9
A
A
LOGIC THRESHOLD
VENH
EN high-level input voltage
VENL
EN low-level input voltage
IEN
Enable internal pull down
current
1.2
0.8
VEN = 0.8 V
1.4
V
1.05
V
2
µA
125
%
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
tOVPDLY
OVP prop deglitch
20
us
VUVP
UVP trip threshold
60
%
tUVPDLY
UVP prop deglitch
256
us
TJ = 25°C
UVLO
Wake up
VUVLOVIN
VIN UVLO threshold
Shutdown
4.2
3.6
4.4
V
3.8
V
Hysteresis
0.4
V
150
°C
20
°C
OVER TEMPERATURE PROTECTION
TOTP
OTP trip threshold(1)
Shutdown temperature
TOTPHSY
OTP hysteresis(1)
Hysteresis
(1)
6
Not production tested
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6.6 Typical Characteristics
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
480
3.25
3
Shutdown Current (uA)
Supply Current (uA)
470
460
450
440
430
-50
2.75
2.5
2.25
2
1.75
-20
10
40
70
Junction Temperature ( OC)
100
1.5
-50
130
100
130
D002
图 6-2. Shutdown Current vs Temperature
图 6-1. Supply Current vs Junction Temperature
615
1.36
610
1.34
EN On Voltage (V)
VFB Feedback Voltage (mV)
10
40
70
Junction Temperature (OC)
VEN = 0 V
VEN = 5 V
605
600
1.32
1.3
1.28
595
590
-50
-20
D001
-20
10
40
70
Junction Temperature ( OC)
100
1.26
-50
130
-20
D003
10
40
70
Junction Temperature (OC)
100
130
D004
1.13
27.5
1.12
25
High-Side RDS(on) (m:)
EN Off Voltage (V)
图 6-3. Feedback Voltage vs Junction Temperature 图 6-4. Enable On Voltage vs Junction Temperature
1.11
1.1
1.09
1.08
-50
22.5
20
17.5
-20
10
40
70
Junction Temperature (OC)
100
130
15
-50
D005
-20
10
40
70
Junction Temperature (OC)
100
130
D011
图 6-5. Enable Off Voltage vs Junction Temperature 图 6-6. High-Side RDS(on) vs Junction Temperature
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16
130
14
128
OVP Threshold (%)
Low-side RDS(on) (m:)
ZHCSNW0C – FEBRUARY 2019 – REVISED APRIL 2021
12
10
6
-50
-20
10
40
70
Junction Temperature (OC)
100
-20
D012
64
440
63
435
62
61
10
40
70
Juncition Temperature (OC)
100
130
D006
图 6-8. OVP Threshold vs Junction Temperature
Discharge Resistor (:)
UVP Threshold (%)
120
-50
130
图 6-7. Low-Side RDS(on) vs Junction Temperature
430
425
420
60
59
-50
-20
10
40
70
Junction Temperature (OC)
100
415
-50
130
10.6
1.33
Soft-start Time (ms)
1.35
10.2
9.8
9.4
10
40
70
Junction Temperature ( OC)
100
130
D008
图 6-10. Discharge Resistor vs Junction
Temperature
11
9
-50
-20
D007
图 6-9. UVP Threshold vs Junction Temperature
Valley Current Limit (A)
124
122
8
1.31
1.29
1.27
-20
10
40
70
Junction Temperature (OC)
100
130
1.25
-50
D009
图 6-11. Valley Current Limit vs Junction
Temperature
8
126
-20
10
40
70
Junction Temperature (OC)
100
130
D010
图 6-12. Soft-Start Time vs Junction Temperature
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100
100
95
90
80
90
Efficiency (%)
Efficiency (%)
70
85
80
75
60
50
40
30
70
60
0.001
20
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
65
0.01
0.1
I-Load (A)
1
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
0
0.001
10
0.01
D027
图 6-13. Efficiency, Eco-mode, FSW = 600 kHz
0.1
I-Load (A)
1
10
D028
图 6-14. Efficiency, OOA-mode, FSW = 600 kHz
100
100
90
80
70
80
Efficiency (%)
Efficiency (%)
90
70
60
0.01
0.1
I-Load (A)
1
0
0.001
10
0.1
I-Load (A)
1
10
D031
图 6-16. Efficiency, OOA-mode, FSW = 1 MHz
700
VVIN=5V,VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
600
Switching Frequency (kHz)
Switching Frequency (kHz)
0.01
D030
400
300
200
500
VVIN=5V,VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
400
300
200
100
100
0
0.001
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
700
500
40
20
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
图 6-15. Efficiency, Eco-mode, FSW = 1 MHz
600
50
30
50
40
0.001
60
0.01
0.1
I-Load (A)
1
10
0
0.001
D023
图 6-17. FSW Load Regulation, Eco-mode, FSW =
600 kHz
0.01
0.1
I-Load (A)
1
10
D036
图 6-18. FSW Load Regulation, OOA-mode, FSW =
600 kHz
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900
700
900
VVIN=5V,VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
800
Switching Frequency (kHz)
Switching Frequency (kHz)
800
600
500
400
300
200
100
0
0.001
0.01
0.1
I-Load (A)
1
200
0.01
0.1
I-Load (A)
1
10
D039
图 6-20. FSW Load Regulation, OOA-mode, FSW =
800 kHz
1000
Switching Frequency (kHz)
Switching Frequency (kHz)
300
1100
VVIN=12V, VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
700
600
500
400
300
200
100
900
VVIN=12V, VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
800
700
600
500
400
300
200
100
0.01
0.1
I-Load (A)
1
10
0
0.001
D052
图 6-21. FSW Load Regulation, Eco-mode, FSW = 1
MHz
10
400
D038
800
0
0.001
500
0
0.001
10
1100
900
600
100
图 6-19. FSW Load Regulation, Eco-mode, FSW =
800 kHz
1000
700
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
0.01
0.1
I-Load (A)
1
10
D053
图 6-22. FSW Load Regulation, OOA-mode, FSW = 1
MHz
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7 Detailed Description
7.1 Overview
The TPS51396A is 8-A integrated FET synchronous buck converter which operates from 4.5-V to 24-V input
voltage (VIN), and the output is from 0.6 V to 7 V. The proprietary D-CAP3 mode enables low external
component count, ease of design, optimization of the power design for cost, size, and efficiency. The key feature
of the TPS51396A is ultra-low quiescent current (ULQ) mode. This feature is beneficial for long battery life in
system standby mode. The device employs D-CAP3 mode control that provides fast transient response with no
external compensation components and an accurate feedback voltage. The control topology provides seamless
transition between CCM operating mode at higher load condition and DCM operation at lighter load condition.
Eco-mode allows the TPS51396A to maintain high efficiency at light load. OOA (out of audio) mode makes
switching frequency above audible frequency larger than 25 kHz, even there is no loading at output side. The
TPS51396A is able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP
or SP-CAP, and ultra-low ESR ceramic capacitors.
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7.2 Functional Block Diagram
PG high
threshold
UV threshold
+
PGOOD
+
UV
Delay
+
+
PG low
threshold
OV
OV threshold
VIN
FB
+
0.6 V
+
VREGOK
LDO
VCC
4.2 V /
3.8 V
+
+PWM
+
Control Logic
VBST
SS
VIN
Ripple injection
SW
Internal SS
x
x
x
x
x
x
x
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
OOA/SKIP
Soft-Start
PGOOD
SW
XCON
SS
PGND
One shot
+
OCL
EN threshold
EN
+
ZC
+
+
NOCL
150°C /20°C
+
THOK
AGND
Light load operation set /
Switching frequency set
Discharge control
MODE
12
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary DCAP3 mode control. The DCAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both lowESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS51396A also
includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS51396A is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in 方程式 1.
fp
1
2 u S u LOUT u COUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS51396A. The low-frequency L-C double pole has a 180 degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS51396A has an internal 1.3-ms soft start, and also an external SS pin is provided for setting higher softstart time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a larger soft start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 方程式 2:
Tss
Css(nF) u VREF(V)
Iss(PA)
(2)
where
• VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS51396A can support large duty operations by its internal TON extension function. When the VIN/VOUT
15 mil width trace
is recommended to reduce line parasitic inductance.
• Feedback could be 20 mil and must be routed away from the switching node, BST node or other high
efficiency signal.
• VIN trace must be wide to reduce the trace impedance and provide enough current capability.
• Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
图 10-1 shows the recommended top-side layout. Component reference designators are the same as the circuit
shown in 图 8-1. Resistor divider for EN is not used in the circuit of 图 8-1, but are shown in the layout for
reference.
VIN
VOUT
SW
GND
GND
AGND
图 10-1. Top-Layer Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
Eco-mode™, D-CAP3™, ULQ™, Eco-Mode™, HotRod™, DCAP3™, and TI E2E™ are trademarks of Texas
Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
24
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器 (TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS51396ARJER
ACTIVE
VQFN-HR
RJE
20
3000
RoHS & Green
Call TI | SN | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
51396A
Samples
TPS51396ARJET
ACTIVE
VQFN-HR
RJE
20
250
RoHS & Green
Call TI | SN | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
51396A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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