TPS51397A
ZHCSLU8A – SEPTEMBER 2020 – REVISED OCTOBER 2020
ULQ™ 运行的 TPS51397A 4.5V 至 24V、10A 同步降压转换器
1 特性
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输入电压范围：4.5V 至 24V
输出电压范围：0.6V 至 5.5V
支持 10A 的连续输出电流
D-CAP3™ 架构控制，可实现快速瞬态响应
0.6V ± 1% 反馈电压精度 (25°C)
集成 17mΩ 和 5.9mΩ FET
ULQ™ 运行 (110μA)，能够在系统待机期间延长电
池寿命
可通过 MODE 引脚选择 Eco-mode™ 和无声™
500kHz 和 800kHz 可选开关频率
可调内部软启动时间，默认为 1.2ms
大占空比运行
集成式电源正常状态指示器
内置输出放电功能
逐周期过流保护
锁存输出 OV 和 UV 保护
非锁存 UVLO 和 OT 保护
-40°C 至 125°C 的工作结温范围
20 引脚 3.0mm × 3.0mm HotRod™ VQFN 封装
与 12A TPS56C230 引脚对引脚兼容
利用 TPS51397A 并借助 WEBENCH® Power
Designer 创建定制设计方案
2 应用
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该 器 件 是 单 片 10A 同 步 降 压 转 换 器 ， 集 成 了
MOSFET，简单易用且高效，只需极少的外部组件，
适合空间受限的电源系统。
TPS51397A 采用了 D-CAP3™ 控制，此控制方式只需
内部补偿即可实现快速瞬态响应以及出色的线路和负载
调整。ULQ™（超低静态电流）特性则非常有益于在低
功耗运行时延长电池寿命。输入电压较低时，大负荷运
行可显著改善负载瞬态性能。
可 使 用 MODE 引 脚 来 设 置 Eco-mode ™ 或 无 声 ™
(OOA) 模 式 ， 以 实 现 轻 负 载 运 行 以 及 500kHz 或
800kHz 的开关频率。Eco-mode™ 可在轻负载运行期
间维持高效率。OOA 模式可将开关频率保持在可闻频
率以上，同时将对效率的影响降至最低。
此器件同时支持内部和外部软启动选项。它具有 1.2ms
的内部固定软启动时间。如果应用需要更长的软启动时
间，可将外部 SS 引脚连接至外部电容器。
TPS51397A 集成了电源正常状态指示器并具备输出放
电功能。它提供包括 OVP、UVP、OCP、OTP 和
UVLO 在内的全面保护。该器件可采用 20 引脚 3.0mm
× 3.0mm HotRod™ 封装，额定结温范围为 –40°C 至
125°C。
器件信息
笔记本电脑和台式机
超极本、手持平板电脑
工业 PC、单板计算机
非军用无人机
分布式电源系统
TPS51397A
(1)
95
90
CIN
EN
EN
CBST
RM_H
BST
COUT
R1
TPS51397A
MODE
FB
PGOOD
PGOOD
RM_L
R2
VCC
3.00mm × 3.00mm
100
VOUT
SW
VIN
封装尺寸（标称值）
VQFN (20)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
L
VIN
VCC
封装(1)
器件型号
SS
VCC
Css
AGND
PGND
85
Efficiency (%)
•
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3 说明
80
75
70
65
60
50
0.01
简化版原理图
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
55
0.1
1
I-Load (A)
10
Eff5
效率与输出电流，500kHz，Eco-mode
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDX7
TPS51397A
www.ti.com.cn
ZHCSLU8A – SEPTEMBER 2020 – REVISED OCTOBER 2020
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 16
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Receiving Notification of Documentation Updates.. 24
11.2 支持资源..................................................................24
11.3 Trademarks............................................................. 24
11.4 静电放电警告...........................................................24
11.5 术语表..................................................................... 24
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2020) to Revision A (September 2020)
Page
• 将器件状态从“预告信息”更改为“量产数据”。.............................................................................................1
2
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5 Pin Configuration and Functions
NC
20
19
7
18
176
16
3
VCC
4
PGND
15
6
6
13
AGND
7
14
7
4
3
FB
4
3
2
PGND
MODE
3
VIN
SW
1
BST
VIN
SW
VIN
4
12
EN
VIN
5
11
SS
7
SW
PGND
6
9
3
7
8
4
6
PGND PGOOD
10
NC
图 5-1. 20-Pin VQFN RJE Package (Top View)
表 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BST
1
O
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor
between BST and SW. 0.1 μF is recommended.
VIN
2,3,4,5
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN
and PGND.
SW
6,19,20
O
Switching node connection to the inductor and bootstrap capacitor for buck. This pin voltage swings
from a diode voltage below the ground up to input voltage of buck.
7,8,18,
Thermal Pad
G
Power GND terminal for the controller circuit and the internal circuitry
PGOOD
9
O
Open-drain power-good indicator. It is asserted low if output voltage is out of PG threshold, over
voltage, or if the device is under thermal shutdown, EN shutdown, or during soft start.
SS
11
O
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.2 ms.
NC
10,16
EN
12
I
Enable input of buck converter
AGND
13
G
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
FB
14
I
Feedback sensing pin for Buck output voltage. Connect this pin to the resistor divider between output
voltage and AGND.
MODE
15
I
Switching frequency and light load operation mode selection pin. Connect this pin to a resistor divider
from VCC and AGND for different MODE options shown in 表 7-1.
VCC
17
O
The driver and control circuits are powered from this voltage. Decouple with a minimum 1-μF ceramic
capacitor as close to VCC as possible.
PGND
Not connect. Can be connected to GND plane for better thermal achieved.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
UNIT
VIN
–0.3
26
V
VBST
–0.3
31
V
VBST-SW
–0.3
6
V
EN, MODE, FB, SS, VCC
–0.3
6
V
PGND, AGND
–0.3
0.3
V
SW
–1
26
V
SW (10-ns transient)
–3
29
V
–0.3
6
V
PGOOD
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22- V C101(2)
VALUE
UNIT
±2000
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
4.5
24
V
VBST
–0.3
29.5
V
VBST-SW
–0.3
5.5
V
EN, MODE, FB, SS, VCC
–0.3
5.5
V
PGND, AGND
–0.3
0.3
V
–1
24
V
–0.3
5.5
V
10
A
–40
125
°C
VIN
Input voltage
Output voltage
SW
PGOOD
IOUT
Output current
TJ
Operating junction temperature
6.4 Thermal Information
TPS51397A
THERMAL METRIC(1)
RJE (VQFN)
UNIT
20 PINS
RθJA
4
Junction-to-ambient thermal resistance
board)(2)
49.7
°C/W
RθJA_effective
Junction-to-ambient thermal resistance (4-layer custom
39.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.2
°C/W
RθJB
Junction-to-board thermal resistance
14.4
°C/W
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TPS51397A
THERMAL METRIC(1)
RJE (VQFN)
UNIT
20 PINS
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
14.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
13.0
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
70 mm x 70 mm, 4 layers, thickness: 1.5 mm. 2 oz. copper traces located on the top and bottom of the PCB. 4 thermal vias in the
PowerPAD area under the device package.
6.5 Electrical Characteristics
TJ = -40°C to 125°C, VIN = 12 V, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
24
V
IVIN
Non-switching supply current
No load, VEN = 5V
4.5
90
110
150
μA
IVINSDN
Shutdown supply current
No load, VEN = 0V
1
2
4
μA
5
5.15
V
VCC OUTPUT
VCC
VCC output voltage
ICC
VCC current limit
VIN > 5.0V
4.85
VIN = 4.5V
4.5
20
mA
FEEDBACK VOLTAGE
VFB
FB voltage
TJ = 25°C
594
600
606
mV
TJ = -40°C to 125°C
591
600
609
mV
VOUT = 2.5V
450
500
550
kHz
30
60
100
ns
130
180
ns
30
42
us
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching frequency
tON(MIN)
SW minumum on time
tOFF(MIN)
SW minimum off time
VFB = 0.5V
OOA Function
TOOA
Mode Operation Period
22
MOSFET and DRIVERS
RDS(ON)H
High side switch resistance
TJ = 25°C
17
mΩ
RDS(ON)L
Low side switch resistance
TJ = 25°C
5.9
mΩ
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
VEN = 0V
300
350
400
Ω
tSS
Soft start time
Internal soft-start time, SS pin
floating
0.5
1.2
2.5
ms
ISS
Soft start charge current
5
μA
PG from low to high
1
ms
VFB falling (fault)
85
%
VFB rising (good)
90
%
VFB rising (fault)
115
%
VFB falling (good)
110
POWER GOOD
tPGDLY
VPGTH
PG start-up delay
PG threshold
VPG_L
PG sink current capability
IOL = 4mA
IPGLK
PG leak current
VPGOOD = 5.5V
%
0.4
V
1
μA
CURRENT LIMIT
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TJ = -40°C to 125°C, VIN = 12 V, unless otherwise noted.
PARAMETER
IOCL
Over current threshold
(valley)
INOCL
Negative over current
threshold
TEST CONDITION
TJ = 25°C
TJ = -40°C to 125°C
MIN
TYP
MAX
UNIT
11
12
13
A
10.5
12
14
A
3.2
A
LOGIC THRESHOLD
VENH
EN high-level input voltage
1.2
1.3
1.4
V
VENL
EN low-level input voltage
0.9
1.1
1.2
V
IEN
Enable internal pull down
current
VEN = 0.8V
2
µA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
125
%
tOVPDLY
OVP prop deglitch
120
us
VUVP
UVP trip threshold
60
%
tUVPDLY
UVP prop deglitch
256
us
UVLO
VUVLO
VIN UVLO threshold
Wake up
4.1
4.2
4.4
V
Shutdown
3.6
3.7
3.9
V
Hysteresis
0.5
V
Shutdown temperature
150
°C
Hysteresis
20
°C
OVER TEMPERATURE PROTECTION
OTP trip threshold(1)
TOTP
TOTPHSY
(1)
6
OTP
hysteresis(1)
Not production tested.
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6.6 Typical Characteristics
130
4
125
3.5
Shutdown Current (PA)
Supply Current (PA)
TJ = -40°C to 125°C, VIN = 12 V, unless otherwise noted.
120
115
110
105
100
-50
2.5
2
1.5
-20
10
40
70
Junction Temperature (°C)
100
1
-50
130
610
1.4
EN On Voltage (V)
1.45
605
600
595
10
40
70
Junction Temperature (°C)
100
130
Ishu
图 6-2. Shutdown Current vs Junction Temperature
615
1.35
1.3
1.25
1.2
590
585
-50
-20
IQ
图 6-1. Supply Current vs Junction Temperature
VFB Feedback Voltage (mV)
3
-20
10
40
70
Junction Temperature (°C)
100
1.15
-50
130
-20
VFB
10
40
70
Junction Temperature (°C)
100
130
ENon
1.24
32
1.2
28
High-Side RDS(on) (m:)
EN Off Voltage (V)
图 6-3. Feedback Voltage vs Junction Temperature 图 6-4. Enable On Voltage vs Junction Temperature
1.16
1.12
1.08
1.04
1
-50
24
20
16
12
-20
10
40
70
Junction Temperature (°C)
100
130
8
-50
-20
ENof
图 6-5. Enable Off Voltage vs Junction Temperature
10
40
70
Junction Temperature (°C)
100
130
Rdsh
图 6-6. High-Side RDS(on) vs Junction Temperature
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12
128
10
127
OVP Threshold ( )
Low-Side RDS(on) (m:)
ZHCSLU8A – SEPTEMBER 2020 – REVISED OCTOBER 2020
8
6
4
2
125
124
123
0
-50
-20
10
40
70
Junction Temperature (°C)
100
122
-50
130
380
63
370
Discharge Resistor (:)
64
62
61
60
100
130
OVPt
360
350
340
330
58
-50
-20
10
40
70
Junction Temperature (°C)
100
320
-50
130
-20
UVPt
图 6-9. UVP Threshold vs Junction Temperature
15
4.5
14
4
13
12
11
10
10
40
70
Junction Temperature (°C)
100
130
Rdis
图 6-10. Discharge Resistor vs Junction
Temperature
Negative Current Limit (A)
Valley Current Limit (A)
10
40
70
Junction Temperature (°C)
图 6-8. OVP Threshold vs Junction Temperature
59
3.5
3
2.5
2
9
-50
-20
10
40
70
Junction Temperature (°C)
100
130
1.5
-50
OCli
图 6-11. Valley Current Limit vs Junction
Temperature
8
-20
Rdsl
图 6-7. Low-Side RDS(on) vs Junction Temperature
UVP Threshold ( )
126
-20
10
40
70
Junction Temperature (°C)
100
130
NOC
图 6-12. Negative Current Limit vs Junction
Temperature
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1.5
45
1.4
40
OOA Period (Ps)
Soft-Start Time (ms)
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1.3
1.2
1.1
1
30
25
20
0.9
-50
-20
10
40
70
Junction Temperature (°C)
100
15
-50
130
100
95
95
90
90
85
85
Efficiency (%)
100
80
75
70
10
40
70
Junction Temperature (°C)
100
130
TOOA
图 6-14. OOA Period vs Junction Temperature
65
80
75
70
65
60
60
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
55
50
0.01
0.1
1
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
55
50
0.01
10
I-Load (A)
0.1
1
10
I-Load (A)
Eff5
图 6-15. Efficiency vs Load Current,
FSW = 500 kHz, Eco-mode
Eff8
图 6-16. Efficiency vs Load Current,
FSW = 800 kHz, Eco-mode
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
-20
Tss
图 6-13. Soft-Start Time vs Junction Temperature
Efficiency (%)
35
60
50
40
30
60
50
40
30
20
20
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
10
0
0.01
0.1
1
10
I-Load (A)
0
0.01
0.1
1
10
I-Load (A)
Eff5
图 6-17. Efficiency vs Load Current,
FSW = 500 kHz, OOA
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
10
Eff8
图 6-18. Efficiency vs Load Current, FSW = 800 kHz,
OOA
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1000
700
Switching Frequency (kHz)
Switching Frequency (kHz)
600
500
400
300
200
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
100
0
800
600
400
200
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
0
0
1
2
3
4
5
6
I-Load (A)
7
8
9
10
0
1
2
3
4
Fsw5
图 6-19. Switching Frequency vs Load Current,
FSW = 500 kHz, Eco-mode
5
6
I-Load (A)
7
8
9
10
Fsw8
图 6-20. Switching Frequency vs Load Current, FSW
= 800 kHz, Eco-mode
1000
700
Switching Frequency (kHz)
Switching Frequency (kHz)
600
500
400
300
200
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
100
0
800
600
400
200
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
0
0
1
2
3
4
5
6
I-Load (A)
7
8
9
10
0
1
Fsw5
2
3
4
5
6
I-Load (A)
7
8
9
10
Fsw8
图 6-21. Switching Frequency vs Load Current, FSW 图 6-22. Switching Frequency vs Load Current, FSW
= 500 kHz, OOA
= 800k Hz, OOA
10
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7 Detailed Description
7.1 Overview
TheTPS51397A is a high density synchronous buck converter that operates from 4.5-V to 24-V input voltage,
and 0.6-V to 5.5-V output voltage range. It has 17-mΩ and 5.9-mΩ integrated MOSFETs that enable high
efficiency up to 10 A. The ULQ™ (Ultra Low Quiescent) feature is extremely beneficial for long battery life in low
power operation. The large duty operation greatly improves the load transient performance when input voltage is
low. The device employs DCAP3 ™ mode control that enables low external component count, ease of design,
optimization of the power design for cost, size, and efficiency, and provides fast transient response with no
external compensation components and an accurate feedback voltage. The control topology supports seamless
transition between CCM mode at heavy load conditions and DCM operation at light load conditions. Eco-mode™
allows the TPS51397A to maintain high efficiency at light load and OOA mode makes switching frequency above
audible frequency (20 kHz), even there is no loading at output side. The TPS51397A is able to adapt to both low
equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors.
7.2 Functional Block Diagram
UV threshold
PG high
threshold
+
PGOOD
+
UV
Delay
+
+
PG low
threshold
OV
OV threshold
VIN
FB
+
0.6 V
+
LDO
VREGOK
VCC
4.2 V /
3.7 V
+
+PWM
+
Control Logic
BST
SS
VIN
Ripple injection
SW
VCC
Internal SS
x
x
x
x
x
x
x
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
Eco-mode/OOA
Soft-Start
PGOOD
SW
XCON
SS
PGND
One shot
+
OCL
EN threshold
EN
+
+
ZC
+
NOCL
150°C / 20°C
+
THOK
AGND
Light load operation
/Switching frequency selection
Discharge control
MODE
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7.3 Feature Description
7.3.1 PWM Operation and DCAP3™ Control
The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports
a proprietary DCAP3 ™ mode control. The DCAP3 ™ mode control combines adaptive on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS51397A also includes an error amplifier that makes the output voltage high accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal
one-shot timer expires. This one-shot duration is set proportional to the converter input voltage, VIN, and is
inversely proportional to the output voltage, VOUT, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to the reference voltage to emulate the output ripple. This enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3™ control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS51397A is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in 方程式 1.
¦P =
1
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the external output set-point resistor divider network and the
internal gain of the TPS51397A. The low-frequency L-C double pole has a 180 degree lag in-phase. At the
output filter frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal
ripple generation network introduces a mid-frequency zero that reduces the gain roll off from –40 dB to –20 dB
per decade and increases the phase to 90 degree one decade above the zero frequency. The inductor and
capacitor selected for the output filter must be such that the double pole is placed close enough to the midfrequency zero so that the phase boost provided by this mid-frequency zero provides adequate phase margin for
the stability requirement. The crossover frequency of the overall system should usually be targeted to be less
than one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS51397A has an internal 1.2-ms soft start. An external SS pin is provided for setting higher soft-start time
if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference voltage to the
PWM comparator.
If the application needs a higher soft-start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 方程式 2:
6OO (IO) =
%OO (J() × 84'( (8)
+OO :Q#;
(2)
where
• VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS51397A can support large duty operation by its internal TON extension function. When VIN/VOUT < 1.6
and the VFB keeps lower than internal VREF, TON is extended to implement the large duty operation which greatly
improves the load transient performance.
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7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. A pullup resistor of 100 kΩ is recommended to pull the
voltage up to VCC. Once VFB is between 90% and 110% of the target output voltage, the PGOOD is pulled high
after a 1-ms de-glitch time. The PGOOD pin is pulled low when:
• FB pin voltage is lower than 85% or greater than 115% of the target output voltage,
• In OVP, UVP, or thermal shutdown event, or
• During the soft-start period.
7.3.5 Overcurrent Protection and Undervoltage Protection
The TPS51397A has overcurrent protection and undervoltage protection. The output overcurrent limit (OCL) is
implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF
state by measuring the low-side FET drain-to-source voltage. This voltage is proportional to the switch current.
To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new pulse, even the
voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching
cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the output current is being limited, the output voltage tends to drop because the load demand is higher than what
the converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, and the device is shut off after a wait time of 256 μs. This protection is a latched function. The fault
latching can be reset by EN going low or VCC power cycling.
The TPS51397A also implements negative overcurrent protection, which can prevent inductor current runaway
when IC works in OOA mode. When the inductor valley current hits the negative overcurrent threshold (NOCL =
–3.2 A typical), the low-side FET turns off, then high-side FET turns on.
7.3.6 Overvoltage Protection
The TPS51397A has an overvoltage protection feature, which has the same implementation. When the output
voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high, and the output
will be discharged and latched after a wait time of 120 µs. This function is a latching operation, so it needs to
reset by EN going low or VCC power cycling.
7.3.7 UVLO Protection
The VIN undervoltage lockout (UVLO) protection monitors the VCC pin voltage to protect the internal circuitry
from low input voltage. When the VCC voltage is lower than the UVLO threshold voltage, the device shuts off
and outputs are discharged to prevent mis-operation of the device. The converter begins operation again when
the input voltage exceeds the threshold by a hysteresis of 500 mV (typical). This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS51397A has a discharge function by using internal MOSFET about 350 Ω, which is connected to the
output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.9 Thermal Shutdown
The TPS51397A monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output is discharged. This is a non-latch protection. The device restarts
operation when the temperature goes below the thermal shutdown threshold.
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7.4 Device Functional Modes
7.4.1 Light Load Operation
The TPS51397A has a MODE pin that can control two different states of operation at light load. The light load
operation includes advanced Eco-mode and OOA mode.
7.4.2 Advanced Eco-mode Control
The advanced Eco-mode control schemes to maintain high light load efficiency. As the output current decreases
from heavy load conditions, the inductor current is also reduced and eventually comes to a point where the
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost
the same as it was in continuous conduction mode so that it takes longer to discharge the output capacitor with
smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional
to the load current, and keeps the light load efficiency high. The light load current where the transition to Ecomode operation happens (IOUT(LL)) can be calculated from 方程式 3.
IOUT(LL) =
(V -V
) × VOUT
1
× IN OUT
2 × LOUT × FSW
VIN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 40% of IOUT(ma×) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Out-of-Audio
Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above
audible frequency with minimum reduction in efficiency. It prevents audio noise generation from the output
capacitors and inductor. During Out-of-Audio operation, the OOA control circuit monitors the states of both highside and low-side MOSFETs and forces them to switch. When both high-side and low-side MOSFETs are off for
more than 30 μs during a light-load condition, the low-side FET will discharge until output voltage drops to
trigger the high-side FET on or inductor current hits negative OC limit.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 20 kHz which avoids the audible noise in the system. When the device works in
OOA mode, TI recommends setting the peak value of inductor current above –1 A by choosing appropriate
inductor.
7.4.4 Mode Selection
The device detects the voltage on the MODE pin during start-up and latches onto one of the MODE options
listed in 表 7-1. The voltage on the MODE pin is recommended to be set by connecting this pin to the center tap
of a resistor divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom
resistor (RM_L) as 1% resistors is shown in 表 7-1. It is recommended to choose the resistor to set the voltage at
around the middle value of each range. It is important that the voltage for the MODE pin is derived from the VCC
rail only since internally this voltage is referenced to detect the MODE option, and not to leave the mode pin
floating. The MODE pin setting can be reset only by a VIN power cycling or EN toggle.
表 7-1. MODE Pin Resistor Settings
14
VOLTAGE ON MODE
RM_H(kΩ)
RM_L (kΩ)
LIGHT LOAD OPERATION
FREQUENCY (kHz)
(0~10%)*VCC
330
15
Eco-mode
500
(10%~20%)*VCC
180
33
OOA
500
(20%~30%)*VCC
160
51
Eco-mode
800
(30%~50%)*VCC
75
51
OOA
800
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图 7-1 shows the typical start-up sequence of the device once the enable signal crosses the EN turnon
threshold. After the voltage on VCC crosses the rising UVLO threshold, it takes about 500 μs to finish the
working mode and frequency selection. The output voltage starts ramping after about 0.2*TSS delay time.
EN threshold
1.3V
EN
VCC UVLO
4.2V
VCC
500us
MODE
MODE/FSW
Selection
VOUT
0.2*TSS
TSS
1ms
PGOOD
图 7-1. Power-Up Sequence
7.4.5 Standby Operation
The TPS51397A can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally. When floating, the part is disabled by
default.
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8 Application and Implementation
Note
以下应用部分的信息不属于 TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The schematic in 图 8-1 shows a typical application for TPS51397A with 5-V output. This design converts an
input voltage range of 5.5 V to 24 V down to 5 V with a maximum output current of 10 A.
8.2 Typical Application
C1
U1
1uF
VIN = 5.5V t 24V
VIN
VCC 17
VCC
BST
1
2
3
4
5
VIN
VIN
VIN
VIN
SW
SW
SW
6
19
20
FB
14
GND
C3
22uF
C4
22uF
C5
0.1uF
GND
SS
11
SS
EN
12
EN
MODE 15
R6
VCC
R7
330k
9
MODE
PGOOD
100k
R8
NC
NC
10
16
AGND
PGND
PGND
PGND
PGND
13
7
8
18
21
C2
0.1uF
R1
0
L1
VOUT = 5V/10A
VOUT
SW
1.8uH
R2
51.1
TP6
R3
0
C11
100pF
C6
0.1uF
C7
47µF
C8
47µF
C9
47µF
R4
110k
C10
47µF
GND
R5
15.0k
TPS51397A
15k
GND
GND
GND
图 8-1. 5-V, 10-A Reference Design
8.2.1 Design Requirements
表 8-1 lists the design parameters for this example.
表 8-1. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOUT
Output voltage
IOUT
Output current
ΔVOUT
VIN
Transient response
5.5
VOUT(ripple)
Output voltage ripple
FSW
Switching frequency
0-A — 10-A loading
10
A
12
24
V
2% x VOUT
500
Light load operating mode
TA
V
±5% x VOUT
1-A — 9-A load step, 2.5 A/μs
Input voltage
5
kHz
Eco-mode
Ambient temperature
25
°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor, you can change the output voltage above 0.6 V. See 方程式 4.
8176 = 0.6 × (1 +
16
4722'4
)
4.19'4
(4)
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8.2.2.1.2 MODE Selection
The light load operation mode (Eco-mode or OOA) and switching frequency are set by a voltage divider from
VCC to GND connected to the MODE pin. See 表 7-1 for possible MODE pin configurations. For this design
example, the switching frequency is about 500 KHz, the light load operation mode is Eco-mode, and the output
current is 10 A.
8.2.2.1.3 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表 8-2 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 方程式 5 and 方程式 6. It is important
that the inductor is rated to handle these currents.
2ö
æ
1 æ VOUT × (VIN(max) - VOUT )ö ÷
ç
2
ç
÷
IL(rms)= ç I OUT + ×
12 ç VIN(max) × LOUT × FSW ÷ ÷÷
ç
è
ø ø
è
IL(peak) = IOUT +
(5)
IOUT(ripple)
(6)
2
Under transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device, so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.1.4 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. In D-CAP3, the regulator reacts within
one cycle to the change in the duty cycle, so good transient performance can be achieved without needing large
amounts of output capacitance. The recommended output capacitance range is given in 表 8-2. Ceramic
capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than VOUT(ripple)/
IOUT(ripple).
表 8-2. Recommended Component Values
VOUT (V)
RLOWER (kΩ) RUPPER (kΩ)
0.6
10
0
1.2
10
10
2.5
15
47.5
3.3
20
90
5.0
15
110
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
500
0.33
66
330
-
800
0.22
66
330
-
500
0.68
66
330
-
800
0.47
66
330
-
500
1.2
66
330
-
800
1.0
66
330
-
500
1.5
66
330
22-110
800
1.2
66
330
22-110
500
1.8
66
330
22-110
800
1.5
66
330
22-110
8.2.2.1.5 Input Capacitor Selection
The TPS51397A requires input decoupling capacitors on power supply input pin VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in 方程式 7.
CIN(min) =
IOUT ×VOUT
VINripple ×VIN ×FSW
(7)
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TI recommends using a high-quality X5R or X7R input decoupling capacitors of nominal 44 µF/35 V on the input
voltage pin VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the application.
The input ripple current is calculated by 方程式 8:
ICIN(rms) = IOUT ×
18
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
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8.2.3 Application Curves
100
1
90
0.6
Load Regulation (%)
Efficiency (%)
图 8-2 through 图 8-17 apply to the circuit of 图 8-1. VIN = 12 V, TA = 25°C, unless otherwise specified.
80
70
VIN=7.4V, VOUT=5V
VIN=12V, VOUT=5V
VIN=18V, VOUT=5V
VIN=24V, VOUT=5V
60
50
0.01
0.1
1
-0.2
VIN=7.4V, VOUT=5V
VIN=12V, VOUT=5V
VIN=18V, VOUT=5V
VIN=24V, VOUT=5V
-0.6
-1
0.001
10
I-Load (A)
0.2
0.01
1
10
load
图 8-3. Load Regulation
800
700
700
600
Switching Frequency (kHz)
Switching Frequency (kHz)
图 8-2. Efficiency Curve
600
500
400
300
500
400
300
200
VIN=7.4V, VOUT=5V
VIN=12V, VOUT=5V
VIN=18V, VOUT=5V
VIN=24V, VOUT=5V
100
200
0
6
8
10
12
14
16
VIN (V)
18
20
22
24
0
1
2
3
4
Fswv
图 8-4. Switching Frequency vs Input Voltage, IOUT
=5A
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0
-0.05
7
8
9
10
Fswl
0.05
0
-0.05
-0.1
-0.1
-0.15
-0.15
-0.2
5
6
I-Load (A)
图 8-5. Switching Frequency vs Output Load
Line Regulation (%)
Line Regulation (%)
0.1
I-Load (A)
EffV
-0.2
6
8
10
12
14
16
VIN (V)
18
20
22
24
6
8
line
图 8-6. Line Regulation, IOUT = 0.1 A
10
12
14
16
VIN (V)
18
20
22
24
line
图 8-7. Line Regulation, IOUT = 5 A
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EN = 5V/div
EN = 5V/div
Vout = 5V/div
Vout = 5V/div
IL = 5A/div
IL = 5A/div
1ms/div
1ms/div
图 8-8. Start-Up Through EN, IOUT = 5 A
图 8-9. Shut-down Through EN, IOUT = 5 A
Vin = 10V/div
Vin = 10V/div
Vout = 5V/div
Vout = 5V/div
IL = 5A/div
IL = 5A/div
20
1ms/div
1ms/div
图 8-10. Start-up Relative to VIN Rising,
IOUT = 5 A
图 8-11. Shut Down Relative to VIN Falling,
IOUT = 5 A
Vout = 50mV/div (AC coupled)
Vout = 50mV/div (AC coupled)
SW = 10V/div
SW = 10V/div
20us/div
2us/div
图 8-12. Output Voltage Ripple, IOUT = 0.1 A
图 8-13. Output Voltage Ripple, IOUT = 5 A
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Vout = 200mV/div (AC coupled)
Vout = 50mV/div (AC coupled)
SW = 10V/div
Iout = 10A/div
2us/div
400us/div
图 8-14. Output Voltage Ripple, IOUT = 10 A
图 8-15. Transient Response, 1 A to 9 A,
Slew Rate = 2.5 A/μs
Vout = 200mV/div (AC coupled)
Vout = 5V/div
SW = 10V/div
Iout = 10A/div
IL = 10A/div
400us/div
80us/div
图 8-16. Transient Response, 0 A to 10 A,
Slew Rate = 2.5 A/μs
图 8-17. Normal Operation to Output Hard Short
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9 Power Supply Recommendations
The TPS51397A is intended to be powered by a well-regulated DC voltage. The input voltage range is 4.5 V to
24 V. The TPS51397A is a buck converter. The input supply voltage must be greater than the desired output
voltage for proper operation. Input supply current must be appropriate for the desired output current. If the input
voltage supply is located far away from the TPS51397A circuit, some additional input bulk capacitance is
recommended. Typical values are 100 μF to 470 μF.
22
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10 Layout
10.1 Layout Guidelines
• A four-layer PCB is recommended for good thermal performance and with maximum ground plane. 3-inch ×
2.75-inch, top and bottom layer PCB with 2-oz copper is used as example.
• Place the decoupling capacitors right across VIN and VCC as close as possible.
• Place output inductors and capacitors with IC at the same layer. SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the PGND
connection of output capacitors and also as close to the output pin as possible.
• Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane. >10-mil width trace
is recommended to reduce line parasitic inductance.
• Feedback can be 10 mil and must be routed away from the switching node, BST node, or other high speed
digital signal.
• VIN trace must be wide to reduce the trace impedance and provide enough current capability.
• Place multiple vias under the device near VIN and PGND and near input capacitors to reduce parasitic
inductance and improve thermal performance.
10.2 Layout Example
图 10-1 shows the recommended top-side layout. Component reference designators are the same as the circuit
shown in 图 8-1.
Trace on the top layer
C
VIN
C
Trace on the bottom layer
Close to VIN pin
R
3
4
VIN
BST
6
VIN
VIN
VIN
7
C
Vias to GND plane
SW
SW
Trace on the bottom layer
PGND
4
4
VCC3
6
PGOOD
3
6
C
Vias to GND plane
NC
NC
3
FB
MODE
AGND
EN
SS
6
4
R
L
PGND
7
7
PGND
PGND
SW
SW
PGND
R
R
R
R
VOUT
Vias to
GND plane
C
Vias to GND plane
Vias to GND plane
0Ÿ
AGND
PGND
图 10-1. Top-Side Layout
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Product Folder Links: TPS51397A
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TPS51397A
ZHCSLU8A – SEPTEMBER 2020 – REVISED OCTOBER 2020
www.ti.com.cn
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
ULQ™, DCAP3™, D-CAP3™, Eco-mode™, 无声™, HotRod™, TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
24
本术语表列出并解释了术语、首字母缩略词和定义。
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TPS51397A
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ZHCSLU8A – SEPTEMBER 2020 – REVISED OCTOBER 2020
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
TPS51397ARJER
Active
Production
VQFN-HR (RJE) | 20
3000 | LARGE T&R
Yes
Call TI | Sn | Nipdau
Level-2-260C-1 YEAR
-40 to 125
51397A
TPS51397ARJER.A
Active
Production
VQFN-HR (RJE) | 20
3000 | LARGE T&R
Yes
Call TI
Level-2-260C-1 YEAR
-40 to 125
51397A
TPS51397ARJER.B
Active
Production
VQFN-HR (RJE) | 20
3000 | LARGE T&R
Yes
Call TI
Level-2-260C-1 YEAR
-40 to 125
51397A
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RJE 20
VQFN-HR - 1 mm max height
QUAD FLATPACK- NO LEAD
3 x 3, 0.45 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224683/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
3.1
2.9
B
A
(45°X0.08) TYP
(0.25)
DETAIL A
3.1
2.9
PIN 1 INDEX AREA
CHAMFERS ARE OPTIONAL
TYPICAL
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 1.8
PKG
SEE TERMINAL
DETAIL A
10
6
16X 0.45
(0.1) TYP
11
5
(0.007)
2X
1.8
PKG
0.975±0.1
21
20X 0.25
0.15
1
PIN 1 ID
DETAIL B
0.1
0.05
15
20
16
(0.123)
C B A
C
20X 0.5
0.3
0.926±0.1
4224338 / B 10/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
(0.926)
(0.123)
16
20
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
21
PKG
(2.8)
(0.975)
11
5
(R0.05) TYP
6
PKG
10
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224338 / B 07/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
(0.926)
(0.123)
16
20
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
21
PKG
(0.975) (2.8)
5
11
(R0.05) TYP
6
PKG
10
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4224338 / B 07/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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