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Table of Contents
User’s Guide
TPS51511 Buck Controller Evaluation Module User's
Guide
ABSTRACT
This user's guide contains information pertaining to the TPS51511 operating specification, the EVM schematic,
the bill of materials, and the printed-circuit board layout.
Table of Contents
1 Hardware................................................................................................................................................................................. 2
1.1 Operating Specification, TPS51511................................................................................................................................... 2
1.2 Schematic.......................................................................................................................................................................... 3
1.3 Bill of Materials...................................................................................................................................................................4
1.4 Board Layout Using TPS51511RHL (QFN 20)...................................................................................................................5
1.5 Test Setup and Procedures................................................................................................................................................9
2 Revision History................................................................................................................................................................... 10
Trademarks
All trademarks are the property of their respective owners.
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Hardware
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1 Hardware
1.1 Operating Specification, TPS51511
Table 1-1. Common Parameters
CH1: Switcher
PARAMETER
TEST CONDITIONS
Input voltage range (VIN)
MIN
Input voltage range (V5IN)
MAX
25
4.75
Operating frequency
Output voltage
TYP
3
5.25
350
High performance
1.2
Low performance
1.1
Adjustable
0.75
UNIT
V
V
kHz
400 k
V
3.3
Output current
15
A
Current limit
18
A
CH2: LDO
PARAMETER
TEST CONDITIONS
Input voltage range
Output voltage
MIN
TYP
1.5
VGA I/O power
Adjustable
5
1.2
0.75
3.3
Output current
2
Current limit
2
MAX
2.5
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UNIT
V
V
A
A
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Hardware
Optional R1 is connected to a pad located near Q3 for possible resistor current sense. (CS_Option)
+
+
1.2 Schematic
Figure 1-1. TPS51511RHL EVM Schematic Diagram (Switcher 1.2 V at 15 A, LDO 1.2 V at 2 A)
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1.3 Bill of Materials
Table 1-2 presents The TPS51511EVM bill of materials.
Table 1-2. TPS51511EVM Bill of Materials
RefDes
Pattern Name
Value
MFR
Part Number
C1, C2
D2E
330 μF/2.5 V
Sanyo
2R5TPE330MC
C3, C4, C5
1210
10 μF/25 V
TDK
C3225X5R1E106M
C6, C8, C9, C16
0805
10 μF/6.3 V
TDK
C2012X5R0J106K
C7
0603
4.7 μF/6.3 V
TDK
C1608X5R0J475M
C10, C11, C19
0603
0.01 μF/50 V
TDK
C1608X7R1H103M
C13
0603
0.1 μF/50 V
TDK
C1608X7R1H104K
C14
0603
1000 pF/50 V
TDK
C1608X7R1H102K
C17
0805
1 μF/ 25 V
TDK
C2012X7R1E105K
C18
0603
Not Installed
TDK
C1608JB1H102M (1 nF/50 V)
C12, C15
0805
Not Installed
TDK
C1608X5R0JxxxM
Q1
SO-8
IRF7821
IR
IRF7821
Q2
SO-8
IRF7832
IR
IRF7832
Q3
SO-8
Not Installed
IR
IRF7832
Q4
SOT-23
Not Installed
Vishay
2N7002
D2
SOD-123
Not Installed
On Semi
MBR0530
L1
IND_IHLP- 5050
1.0 μH
Vishay
IHLP5050CEER1R0M01
DAC1
ON-OFF-ON
G-13AP
NKK
G13AP
DAC2, LDO, SW
ON-ON
G-12AP
NKK
G12AP
R3
0603
0
Vishay
Std
R11
0805
0
Vishay
Std
R2, R17, R20, R21
0603
1K
Vishay
Std
R6
0603
6.34 K
Vishay
Std
R10, R12
0603
10 K
Vishay
Std
R5
0603
14 K
Vishay
Std
R16
0603
18.2 K
Vishay
Std
R9, R15
0603
30.1 K
Vishay
Std
R7
0603
100 K
Vishay
Std
R13
0603
105 K
Vishay
Std
R1, R14
0603
Not Installed
Vishay
0
R18
0603
Not Installed
Vishay
100K
R19
0603
Not Installed
Vishay
Depends on 2bit DAC Vout set
R4
0603
Not Installed
Vishay
Std
R8
0805
Not Installed
Vishay
Std
U1
QFN 20
TPS51511
TI
TPS51511RHL
TP1
TP-Probe
131-4244-00
Tektronix
131-4244-00
TP2–TP15
TP loop
5002
Keystone Elect.
50021
1582-2
Keystone Elect.
1582-2
Bumpon 0.44 × 0.20 Black
(4 Corners bottom)
3M
SJ5003 (Black)
V5IN, V5IN_GND, VIN,
Turret Dbl
VIN_GND, VO, VO_GND, LDOIN,
LDO_GND, LDO_OUT
HARDWARE
Standoff
4
SJ5003
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1.4 Board Layout Using TPS51511RHL (QFN 20)
Figure 1-2. Top Layer Copper
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Figure 1-3. Layer 2 (Internal 1) Copper
6
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Figure 1-4. Layer 3 (Internal 2) Copper
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Figure 1-5. Bottom Layer Copper
8
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Hardware
1.5 Test Setup and Procedures
DAC2 External
Additional DAC
DAC1 Internal DAC
Switch Gate
PGOOD2:
Configure to LDO
LDO Enable
Switch
Switcher Enable
Figure 1-6. Switches and Jumpers
Table 1-3. Various Switch Settings
Switch
Function
On
Off
Floating
Components to Add for Specific Configuration
DAC2
Low
High
N/A
R19, Q4
DAC1
High
Low
LDO Power Good
R14, R18 (LDO Power Good)
LDO Switch
High
Low
N/A
N/A
Sw (Switcher Enable)
High
Low
N/A
N/A
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Revision History
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LDOIN External Supply Voltage
Range 1.5 V to 3.4 V @ 3.5 A
(-)
(+)
5 V DC Supply Voltage
Current Limited @ 1 A
LDO Load 2 A
(-)
(+)
(+)
(-)
VIN DC Supply Voltage
Current Limit @ 5 A
Range 3 V to 25 V
(-)
(+)
(-)
VOSW Load
0 - 15 A
(+)
Figure 1-7. Test Setup
•
Standard Test Procedures
– Required Equipment:
• 3 × Bench power supplies (V5in supply 4.75 V to 5.25 V at 1 A), (Vin supply 3 V to 25 V at 5 A),
(LDO_IN 1.5 V to 3.4 V at 3.5 A).
• 2 x Electronic loads one capable of sinking 19 A at 1.2 V and the other capable of sinking 4 A at 1.2 V.
– Switch Settings:
• DAC1 = ON, Switcher operates in the high-performance range (1.2-V output).
• LDO (ON/OFF) = Enables or disables the LDO output (1.2 V at 2 A).
• SW (ON/OFF) = Enables or disables the Switcher output. (1.2 V at 15 A) (Low-current skip mode
current > 2 A operates in PWM mode.
– Bootstrap Diode:
• Bootstrap diode D1 is not populated on the current evaluation module because the TPS51511 has a
built-in bootstrap diode. In order to further improve the efficiency, D1 can be added.
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2007) to Revision A (February 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
10
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•
Revision History
Updated the user's guide title............................................................................................................................. 2
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