TPS51916RUKR

Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design TPS51916 SLUSAE1F – DECEMBER 2010 – REVISED DECEMBER 2018 TPS51916 Complete DDR2, DDR3, DDR3L and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference 1 Features • 1 • • • • Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 V to 28 V – Output Voltage Range: 0.7 V to 1.8 V – 0.8% VREF Accuracy – Selectable Control Architecture – D-CAP™ Mode for Fast Transient Response – D-CAP2™ Mode for Ceramic Output Capacitors – Selectable 300 kHz, 400 kHz, 500 kHz, or 670 kHz Switching Frequencies – Optimized Efficiency at Light and Heavy Loads with Auto-skip Function – Supports Soft-Off in S4 and S5 States – OCL/OVP/UVP/UVLO Protections – Powergood Output 2-A LDO(VTT), Buffered Reference(VTTREF) – 2-A (Peak) Sink and Source Current – Buffered, Low Noise, 10-mA VTTREF Output – 0.8% VTTREF, 20-mV VTT Accuracy – Supports High-Z (S3) and Soft-Off (S4, S5) Thermal Shutdown 20-Pin, 3 mm × 3 mm, QFN Package Create a WEBENCH Design The device employs D-CAP™ mode coupled with 300 kHz or 400 kHz frequencies for ease-of-use and fast transient response or D-CAP2™ mode coupled with higher 500 kHz or 670 kHz frequencies to support ceramic output capacitor without an external compensation circuit. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2-A sink and 2-A source peak current capabilities, requires only 10-μF of ceramic capacitance. A dedicated LDO supply input is available. The device also provides excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4 or S5 state. Programmable OCL with low-side MOSFET RDS(on) sensing, OVP, UVP, UVLO and thermal shutdown protections are also available. Device Information(1) PART NUMBER TPS51916 Simplified Application VIN 5VIN 2 Applications • BODY SIZE (NOM) 3 mm × 3 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. PGND • PACKAGE QFN (20) Memory Power Supplies: DDR2, DDR3, DDR3L, DDR4 Termination: SSTL_18, SSTL_15, SSTL_135, HSTL PGND 12 V5IN VBST 15 S3 17 S3 DRVH 14 S5 16 S5 VDDQ SW 13 DRVL 11 6 VREF PGND 10 PGOOD 20 8 3 Description The TPS51916 device provides a complete power supply for DDR2, DDR3, DDR3L, and DDR4 memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink and 2-A source tracking LDO (VTT) and buffered low noise reference (VTTREF). 7 AGND PGND REFIN GND VDDQSNS 9 VLDOIN 2 VTT 3 19 MODE VTTSNS 1 18 TRIP VTTGND 4 VTTREF 5 Powergood VTT VTTREF AGND PGND . 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS51916 SLUSAE1F – DECEMBER 2010 – REVISED DECEMBER 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 5 5 6 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 15 7.1 Overview ................................................................. 15 7.2 Functional Block Diagram ....................................... 15 7.3 Feature Description................................................. 16 7.4 Device Functional Modes........................................ 20 7.5 D-CAP2™ Mode Operation .................................... 22 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 9 Power Supply Recommendations...................... 28 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 31 11 Device and Documentation Support ................. 32 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History Changes from Revision E (August 2016) to Revision F • Page Changed VLDOIN discharge current test condition from "Non-tracking" to "Tracking" in Electrical Characteristics table .... 6 Changes from Revision D (June 2012) to Revision E Page • Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, Receiving Notification of Documentation Updates section, Community Resources section, and Mechanical, Packaging, and Orderable Information section, and Mechanical, Packaging, and Orderable Information section ........................................................................................................................................ 1 • Changed Minimum S3 or S5 high-level voltage from "1.8 V" to "1.5 V" in Electrical Characteristics table ........................... 7 Changes from Revision C (March 2012) to Revision D Page • Added clarity to .................................................................................................................................................................... 15 • Added more information to VTT and VTTREF section. ....................................................................................................... 18 • Added clarity to Figure 38..................................................................................................................................................... 22 2 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS51916 TPS51916 www.ti.com SLUSAE1F – DECEMBER 2010 – REVISED DECEMBER 2018 5 Pin Configuration and Functions PGOOD MODE TRIP S3 S5 RUK Package 20-Pin QFN Top View 20 19 18 17 16 VTTSNS 1 15 VBST VLDOIN 2 14 DRVH VTT 3 13 SW VTTGND 4 12 V5IN VTTREF 5 11 DRVL 8 GND REFIN 9 10 PGND 7 VDDQSNS 6 VREF Thermal Pad Pin Functions PIN I/O DESCRIPTION NAME NO. DRVH 14 O High-side MOSFET gate driver output. DRVL 11 O Low-side MOSFET gate driver output. GND 7 – Signal ground. MODE 19 I Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2) PGND 10 – Gate driver power ground. RDS(on) current sensing input(+). PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range. REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation. SW 13 S3 17 I S3 signal input. (See Table 1) S5 16 I S5 signal input. (See Table 1) TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC = 4700 ppm/°C. VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin. VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF. VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application. VREF 6 O 1.8-V reference output. VTT 3 O VTT 2-A LDO output. Need to connect at least 10 μF of capacitance for stability. VTTGND 4 – Power ground for VTT LDO. VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability. VTTSNS 1 I VTT output voltage feedback. V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers. – Thermal pad. Connect directly to system GND plane with multiple vias. Thermal pad I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–). Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS51916 3 TPS51916 SLUSAE1F – DECEMBER 2010 – REVISED DECEMBER 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VBST –0.3 36 VBST (3) –0.3 6 –5 30 VLDOIN, VDDQSNS, REFIN –0.3 3.6 VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN, S3, S5, TRIP, MODE –0.3 6 –5 36 SW Input voltage (2) DRVH Output voltage (2) DRVH (3) –0.3 6 VTTREF, VREF –0.3 3.6 VTT –0.3 3.6 DRVL –0.3 6 PGOOD –0.3 (1) (2) (3) V V 6 Junction temperature, TJ Storage temperature, TSTG UNIT –55 125 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS51916 TPS51916 www.ti.com SLUSAE1F – DECEMBER 2010 – REVISED DECEMBER 2018 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage Input voltage TA MAX V5IN 4.5 5.5 VBST –0.1 33.5 VBST –0.1 5.5 SW -3 28 SW –4.5 28 VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3, S5, TRIP, MODE –0.1 5.5 –3 33.5 DRVH Output voltage NOM DRVH-SW –0.1 5.5 DRVH (less than 30% of repetitive period) –4.5 33.5 VTTREF, VREF –0.1 3.5 VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 Ambient temperature –40 85 UNIT V V V °C 6.4 Thermal Information TPS51916 THERMAL METRIC (1) RUK (QFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 94.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.1 °C/W RθJB Junction-to-board thermal resistance 64.3 °C/W ψJT Junction-to-top characterization parameter 31.8 °C/W ψJB Junction-to-board characterization parameter 58.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: TPS51916 5 TPS51916 SLUSAE1F – DECEMBER 2010 – REVISED DECEMBER 2018 www.ti.com 6.5 Electrical Characteristics over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5IN(S0) V5IN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 590 IV5IN(S3) V5IN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 IV5INSDN V5IN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 1 μA IVLDOIN(S0) VLDOIN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 5 μA IVLDOIN(S3) VLDOIN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 μA IVLDOINSDN VLDOIN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 5 μA V μA μA VREF OUTPUT IVREF = 30 μA, TA = 25°C VVREF Output voltage IVREFOCL Current limit 1.8000 0 μA ≤ IVREF