TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
D
D
D
D
D
D
D
D
D
D
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D
700 KHz Operation
1.25 MHz Operation With External Driver
1.5% Reference Over Full Operating
Temperature Range
Synchronous Rectifier Driver for Greater
Than 90% Efficiency
Programmable Reference Voltage Range of
1.3 V to 3.5 V
User–Selectable Hysteretic Type Control
Droop Compensation for Improved Load
Transient Regulation
Adjustable Overcurrent Protection
Programmable Softstart
Overvoltage Protection
Active Deadtime Control
Power Good Output
Internal Bootstrap Schottky Diode
Low Supply Current . . . 3-mA Typ
Reduced System Component Count and
Size
PWP PACKAGE
(TOP VIEW)
IOUT
DROOP
OCP
VHYST
VREFB
VSENSE
ANAGND
SLOWST
BIAS
LODRV
LOHIB
DRVGND
LOWDR
DRV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PWRGD
VID0
VID1
VID2
VID3
VID4
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
VCC
description
The TPS5211 is a hysteretic regulator controller which provides an accurate, programmable supply voltage to
microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range of 1.3 V to
3.5 V. The output voltage can be set to equal the reference voltage or some multiple of the reference voltage.
A hysteretic controller with user-selectable hysteresis and programmable droop compensation is used to
dramatically reduce overshoot and undershoot caused by load transients. Propagation delay from the
comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for
the output drivers combine to eliminate destructive faults in the output FETs. The softstart current source is
proportional to the reference voltage, thereby eliminating variation of the softstart timing when changes are
made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector output low when
the output drops 7% below the nominal output voltage. An overvoltage circuit disables the output drivers if the
output voltage rises 15% above the nominal value. The inhibit pin can be used to control power sequencing.
Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage (5 V or 3.3 V) is
within proper operating limits before the controller starts. Single-supply (12 V) operation is easily accomplished
using a low-current divider for the required 5-V signals. The output driver circuits include 2-A drivers with internal
8-V gate-voltage regulators. The high-side driver can be configured either as a ground-referenced driver or as
a floating bootstrap driver. The TPS5211 is available in a 28-pin TSSOP PowerPAD package. It operates over
a junction temperature range of 0°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TJ
0°C to 125°C
TSSOP
(PWP)
TPS5211PWPR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
LOSENSE
20
21
19
NOCPU
2V
22
+
–
UVLO
Shutdown
S
VCC
3
1
Fault
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
R
Rising
Edge
Delay
Deglitch
HIGHDR
Deglitch
VPGD
0.93 Vref
VOVP
1.15 Vref
HIGHIN
VCC
VSENSE
8
PREREG
Analog Bias
+
–
Bandgap
Analog
Bias
9
IVREFB
5
–
+
Slowstart
Comp
14
DRV REG
Shutdown
16
CM Filters
VID
MUX
and
Decoder
17
+
VREF
Σ
+
–
–
+ –
Hysteresis
Comp
Shutdown
200 kΩ
Hysteresis
Setting
IVREFB
26
25
24 23
5
2
4
13
6
VID0 VID1 VID2 VID3 VID4 VREFB DROOP VHYST VSENSE
11
10
LOHIB
LODRV
BIAS
DRV
BOOT
HIGHDR
200 kΩ
18
BOOTLO
12
27
IOUT
2x
Q
+
100 mV
SLOWST
IOUTLO HISENSE
LOWDR
DRVGND
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
28
11111
Decode
10 V
OCP
PWRGD
7
SLVS243 – SEPTEMBER 1999
INHIBIT
ANAGND
15
functional block diagram
2
VCC
VID0
VID1
VID2
VID3
VID4
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ANAGND
7
BIAS
9
O
Analog ground
Analog BIAS pin. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND.
BOOT
16
I
Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO.
BOOTLO
18
O
Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
DROOP
2
I
Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND.
DRV
14
O
Drive regulator for the FET drivers. A 1-µF ceramic capacitor should be connected from DRV to DRVGND.
DRVGND
12
HIGHDR
17
O
High drive. Output drive to high-side power switching FETs
HISENSE
19
I
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
22
I
Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V
or 5 V).
IOUT
1
O
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FETs. The voltage on this pin equals 2×Rds(on)×IOUT. In applications requiring very accurate
current sensing, a sense resistor should be connected between the input supply and the drain of the high-side
FETs.
IOUTLO
21
O
Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
are off. Capacitance range should be between 0.033 µF and 0.1 µF.
LODRV
10
I
Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
LOHIB
11
I
Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
I
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
LOWDR
13
O
Low drive. Output drive to synchronous rectifier FETs
OCP
3
I
Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD
28
O
Power good. Power good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST
8
O
Slowstart (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Slowstart current = IVREFB/5
VCC
15
VHYST
4
I
HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND.
The hysteresis window = 2 × (VREFB – VHYST)
VID0
27
I
Voltage identification input 0
VID1
26
I
Voltage identification input 1
VID2
25
I
Voltage identification input 2
VID3
24
I
Voltage identification input 3
VID4
23
I
Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
setting the output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from VCC.
VREFB
5
O
Buffered reference voltage from VID network
VSENSE
6
I
Voltage sense input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended an RC low pass filter be connected at this pin to filter noise.
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
12-V supply. A 1-µF ceramic capacitor should be connected from VCC to DRVGND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
detailed description
VREF
The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to VCC. The VID codes conform
to the Intel VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.5 V, and they are
decremented by 50 mV, down to 1.3 V, for the lower VID settings. Voltages higher than VREF can be implemented
using an external divider. Refer to Table 1 for the VID code settings. The output voltage of the VID network, VREF,
is within ±1.5% of the nominal setting over the VID range of 1.3 V to 2.5 V, including a junction temperature range
of 5°C to +125°C, and a VCC supply voltage range of 11.4 V to 12.6 V. The output of the reference/VID network
is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 5mV of VREF.
It is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator,
because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the
slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be
equal to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the
comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or VCC.
The rms current through the drivers output should not exceed 110 mA. Refer to the application information
section to determine how to calculate an operating frequency to meet this requirement.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
detailed description (continued)
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
droop compensation
The droop compensation network reduces the load transient overshoot/undershoot on VO, relative to VREF . VO
is programmed to a voltage greater than VREF by an external resistor divider from VO to VSENSE to reduce the
undershoot on VO during a low-to-high load transient. The overshoot during a high-to-low load transient is
reduced by subtracting the voltage on DROOP from VREF. The voltage on IOUT is divided with an external
resistor divider, and connected to DROOP.
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
VCC undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the VCC supply is below the 10-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of CSLOWST is proportional to the reference voltage. By making the charging
current proportional to VREF, the power-up time for VO will be independent of VREF. Thus, CSLOWST can remain
the same value for all VID settings. The slowstart charging current is determined by the following equation:
Islowstart = I(VREFB) / 5 (amps)
Where I(VREFB) is the current flowing out of VREFB.
It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting
the hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500 µA. The equation
for setting the slowstart time is:
tSLOWST = 5 × CSLOWST × RVREFB
(seconds)
Where RVREFB is the total external resistance from VREFB to ANAGND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
detailed description (continued)
power good
The power-good circuit monitors for an undervoltage condition on VO. If VO is 7% below VREF, then the PWRGD
pin is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors VO for an overvoltage condition. If VO is 15% above VREF,
then a fault latch is set and both output drivers are turned off. The latch will remain set until VCC goes below the
undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section
for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
high-side power FET.
overcurrent protection
The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage
connected to the OCP pin. If the voltage on OCP exceeds 100 mV, then a fault latch is set and the output drivers
are turned off. The latch will remain set until VCC goes below the undervoltage lockout value. A 3-µs deglitch
timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against
a short-to-ground fault on the terminal common to both power FETs.
drive regulator
The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum
short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.
LODRV
The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur if the high-side
power FETs become shorted. External components to sense an overvoltage condition are required to use this
feature. When an overvoltage fault occurs, the low-side FETs are used as a crowbar. LODRV is pulled low and
the low-side FET will be turned on, overriding all control signals inside the TPS5211 controller. The crowbar
action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
in series with Vin should be added to disconnect the short-circuit.
Table 1. Voltage Identification Codes
VID TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
6
VREF
VID4
VID3
VID2
VID1
VID0
(Vdc)
0
1
1
1
1
1.30
0
1
1
1
0
1.35
0
1
1
0
1
1.40
0
1
1
0
0
1.45
0
1
0
1
1
1.50
0
1
0
1
0
1.55
0
1
0
0
1
1.60
0
1
0
0
0
1.65
0
0
1
1
1
1.70
0
0
1
1
0
1.75
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
Table 1. Voltage Identification Codes (Continued)
VID TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
VREF
VID4
VID3
VID2
VID1
VID0
(Vdc)
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
No CPU
1
1
1
1
0
2.10
1
1
1
0
1
2.20
1
1
1
0
0
2.30
1
1
0
1
1
2.40
1
1
0
1
0
2.50
1
1
0
0
1
2.60
1
1
0
0
0
2.70
1
0
1
1
1
2.80
1
0
1
1
0
2.90
1
0
1
0
1
3.00
1
0
1
0
0
3.10
1
0
0
1
1
3.20
1
0
0
1
0
3.30
1
0
0
0
1
3.40
1
0
0
0
0
3.50
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
Input voltage range: BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
INHIBIT, VIDx, LODRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7.3 V
PWRGD, OCP, DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
LOHIB, LOSENSE, IOUTLO, HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Output current, VREFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA
Short circuit duration, DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PWP
1150 mW
11.5 mW/°C
630 mW
460 mW
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
recommended operating conditions
MIN
MAX
11.4
13
V
Input voltage, BOOT to DRVGND
0
28
V
Input voltage, BOOT to BOOTLO
0
13
V
Input voltage, INHIBIT, VIDx, LODRV, PWRGD, OCP, DROOP
0
6
V
Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE
0
13
V
Input voltage, VSENSE
0
4.5
V
Voltage difference between ANAGND and DRVGND
Output current, VREFB†
0
±0.2
V
0
0.4
mA
Supply voltage, VCC
UNIT
† Not recommended to load VREFB other than to set hystersis since IVREFB sets slowstart time.
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, IDRV = 0 A (unless otherwise noted)
reference/voltage identification
PARAMETER
TEST CONDITIONS
VREF
Cumulative reference accuracy
(see Note 2)
VIDx
High-level input voltage
VIDx
Low-level input voltage
VREFB
VIDx
MIN
VCC = 11.4 to 12.6 V, 1.3 V ≤ VREF ≤ 3.5 V
TYP
MAX
–0.015
0.015
2.25
IVREFB = 50 µA
Output regulation
10 µA ≤ IO ≤ 500 µA
Input resistance
VIDx = 0 V
VREF–5mV
VREF VREF+5mV
2
Input pull-up voltage divider
V/V
V
1
Output voltage
UNIT
V
V
mV
36
73
95
kΩ
4.8
4.9
5
V
NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.
3. This parameter is ensured by design and is not production tested.
power good
PARAMETER
TEST CONDITIONS
Undervoltage trip threshold
VOL
IOH
Low-level output voltage
Vhys
Hysteresis voltage
MIN
TYP
90
93
IO = 5 mA
VPWRGD = 6 V
High-level input current
0.5
MAX
UNIT
95 %VREF
0.75
V
µA
1
1.3
2.9
4.5 %VREF
MIN
TYP
MAX
UNIT
10.4
13
15.6
µA
slowstart
PARAMETER
TEST CONDITIONS
Charge current
VSLOWST = 0.5 V,
IVREFB = 65 µA
Discharge current
VSLOWST = 1 V
VVREFB = 1.3 V,
3
Comparator input offset voltage
Comparator input bias current
See Note 3
Comparator hysteresis
–7.5
NOTE 3: This parameter is ensured by design and is not production tested.
8
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mA
10
mV
100
nA
7.5
mV
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
hysteretic comparator
PARAMETER
Input offset voltage
Input bias current
Hysteresis accuracy
TEST CONDITIONS
MIN
VDROOP = 0 V (see Note 3)
See Note 3
–2.5
VREFB – VHYST = 15 mV
(Hysteresis window = 30 mV)
–3.5
Maximum hysteresis setting
VREFB – VHYST = 30 mV
NOTE 3: This parameter is ensured by design and is not production tested.
TYP
MAX
2.5
UNIT
mV
500
nA
3.5
mV
60
mV
high-side VDS sensing
PARAMETER
TEST CONDITIONS
MIN
Gain
VHISENSE = 12 V,
VLOSENSE = 11.9 V,
Differential input to Vds sensing amp = 100 mV
Sink current
5 V ≤ VIOUTLO ≤ 13 V
IOUT
Source current
VIOUT = 0.5 V,
VIOUTLO = 11.5 V
IOUT
Sink current
VIOUT = 0.05 V, VHISENSE = 12 V,
VIOUTLO = 12 V
Output voltage swing
LOSENSE
MAX
2
Initial accuracy
IOUTLO
TYP
High-level input voltage
Low-level input voltage
VHISENSE = 12 V,
194
206
mV
250
nA
µA
50
µA
0
VHISENSE = 3 V, RIOUT = 10 kΩ
11.4 V ≤ VHISENSE ≤ 12.6 V,
LOSENSE connected to HISENSE,
VHISENSE – VIOUTLO = 0.15 V
V/V
500
VHISENSE = 11 V, RIOUT = 10 kΩ
VHISENSE = 4.5 V, RIOUT = 10 kΩ
VHISENSE = 4
4.5
5 V (see Note 3)
UNIT
2
V
0
1.5
V
0
0.75
V
2.85
V
2.4
V
50
60
80
62
85
123
67
95
144
69
75
MIN
TYP
MAX
UNIT
1.9
2.1
2.35
V
Hysteresis
0.08
0.1
0.12
V
Stop threshold
1.85
Sample/hold resistance
4.5 V ≤ VHISENSE ≤ 5.5 V,
LOSENSE connected to HISENSE,
VHISENSE – VIOUTLO = 0.15 V
3 V ≤ VHISENSE ≤ 3.6 V,
LOSENSE connected to HISENSE,
VHISENSE – VIOUTLO = 0.15 V
VHISENSE = 12.6 V to 3 V,
VHISENSE – VOUTLO = 100 mV
NOTE 3. This parameter is ensured by design and is not production tested.
CMRR
Ω
dB
inhibit
PARAMETER
TEST CONDITIONS
Start threshold
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V
9
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
overvoltage protection
PARAMETER
TEST CONDITIONS
Overvoltage trip threshold
Hysteresis
MIN
TYP
112
115
See Note 3
10
MAX
UNIT
120 %VREF
mV
NOTE 3: This parameter is ensured by design and is not production tested.
overcurrent protection
PARAMETER
TEST CONDITIONS
OCP trip threshold
MIN
TYP
90
100
Input bias current
MAX
UNIT
110
mV
100
nA
MAX
UNIT
deadtime
PARAMETER
LOHIB
LOWDR
TEST CONDITIONS
High-level input voltage
MIN
TYP
2.4
Low-level input voltage
1.4
High-level input voltage
See Note 3
Low-level input voltage
See Note 3
3
1.7
V
V
NOTE 3: This parameter is ensured by design and is not production tested.
LODRV
PARAMETER
LODRV
TEST CONDITIONS
High-level input voltage
MIN
TYP
MAX
1.85
Low-level input voltage
0.95
UNIT
V
droop compensation
PARAMETER
TEST CONDITIONS
Initial accuracy
VDROOP = 50 mV
MIN
TYP
46
MAX
54
UNIT
mV
drive regulator
PARAMETER
TEST CONDITIONS
Output voltage
11.4 V ≤ VCC ≤ 12.6 V,
Output regulation
1 mA ≤ IDRV ≤ 50 mA
IDRV = 120 mA
Short-circuit current
MIN
TYP
7
MAX
9
100
UNIT
V
mV
120
mA
bias regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
11.4 V ≤ VCC ≤ 12.6 V,
See Note 4
6
V
NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5211 controller. External loads should not be driven by the bias
regulator.
input undervoltage lockout
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
9.25
10
10.75
V
Hysteresis
1.9
2
2.2
V
Stop threshold
7.5
Start threshold
10
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V
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
output drivers
PARAMETER
Peak output
current
(see Note 5)
tpw < 100 µs,
VBOOT – VBOOTLO = 6.5 V,
High-side sink
Duty cycle < 2%,
TJ = 125°C,
High-side source
VHIGHDR = 1.5 V (source) or 6 V (sink),
See Note 3
Low-side sink
Duty Cycle < 2%,
TJ = 125°C,
Low-side source
VLOWDR = 1.5 V (source) or 5 V (sink),
See Note 3
High-side sink
Output
resistance
(see Note 5)
TEST CONDITIONS
High-side source
Low-side sink
Low-side source
tpw < 100 µs,
VDRV = 6.5 V,
MIN
TYP
MAX
UNIT
2
2
A
2
2
3
TJ = 125°C,,
VBOOT – VBOOTLO = 6.5 V,,
VHIGHDR = 6 V (source) or 0.5 V (sink)
45
5.7
TJ = 125°C,
VDRV = 6.5 V,
VLOWDR = 6 V (source) or 0.5 V (sink)
Ω
45
NOTES: 3. This parameter is ensured by design and is not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
supply current
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
range
VINHIBIT = 5 V,
VCC > 10.75 V at startup,
VCC
Quiescent
current
High-side
driver
quiescent
current
VID code ≠ 11111,
VBOOTLO = 0 V
VINHIBIT = 5 V,
VID code ≠ 11111,
VCC > 10.75 V at startup,
VBOOTLO = 0 V,
CHIGHDR = 50 pF,
CLOWDR = 50 pF,
fSWX = 200 kHz,
See Note 3
VINHIBIT = 0 V or VID code = 11111 or VCC < 9.25 V at startup,
VBOOT = 13 V,
VBOOTLO = 0 V
VINHIBIT = 5 V,
VID code ≠ 11111, VCC > 10.75 V at startup,
VBOOT = 13 V,
VBOOTLO = 0 V,
CHIGHDR = 50 pF,
fSWX = 200 kHz (see Note 3)
MIN
TYP
MAX
11.4
12
13
3
10
UNIT
V
mA
5
80
2
µA
mA
NOTE 3: This parameter is ensured by design and is not production tested.
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11
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
switching characteristics over recommended operating virtual-junction temperature range,
VCC = 12 V, IDRV = 0 A (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSENSE to HIGHDR or
LOWDR ((excluding
g deadtime)
MIN
1.3 V ≤ VVREF ≤ 3.5 V, 10 mV overdrive
(see Note 3)
150
250
1.3 V ≤ VVREF ≤ 3.5 V, 20 mV overdrive
200
1.3 V ≤ VVREF ≤ 3.5 V, 30 mV overdrive
190
OVP comparator
See Note 3
Rise time
LOWDR output
Overdrive = 10 mV (see Note 3)
560
VBOOTLO = 0 V
CL = 50 pF
8
TBD
35
CL = 50 pF
TBD
CL = 3 nF
OCP
OVP
2
5
2
5
VHISENSE = 12 V,
VIOUTLO pulsed from 12 V to 11.9 V,
100 ns rise/fall times
(see Note 3)
2
VHISENSE = 4.5 V,
VIOUTLO pulsed from 4.5 V to 4.4 V,
100 ns rise/fall times (see Note 3)
3
VHISENSE = 3 V,
VIOUTLO pulsed from 3 V to 2.9 V,
100 ns rise/fall times (see Note 3)
3
Short-circuit protection
rising-edge delay
SCP
LOSENSE = 0 V (see Note 3)
Turnon/turnoff delay
VDS sensing sample/hold
switch
Crossover delay time
ns
40
See Note 3
High-side VDS sensing
ns
40
VBOOTLO = 0 V
CL = 3 nF
LOWDR output
ns
8
35
CL = 50 pF,
HIGHDR output
900
CL = 3 nF
CL = 3 nF
Fall time
µs
1
1
CL = 50 pF,
HIGHDR output
ns
1
PWRGD comparator
SLOWST comparator
UNIT
180
OCP comparator
Response time
MAX
1.3 V ≤ VVREF ≤ 3.5 V, 40 mV overdrive
Propagation
g
delay
y
Deglitch time (Includes
comparator propagation
delay)
TYP
µs
µs
300
500
ns
3 V ≤ VHISENSE ≤ 11 V,
VLOSENSE = VHISENSE (see Note 3)
30
100
ns
LOWDR to HIGHDRV, and
LOHIB to LOWDR
See Note 3
30
100
ns
Prefilter pole frequency
Hysteretic comparator
See Note 3
Propagation delay
LODRV
See Note 3
NOTE 3: This parameter is ensured by design and is not production tested.
12
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5
MHz
400
ns
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SLOWSTART TIME
vs
SLOWSTART CAPACITANCE
SLOWSTART TIME
vs
SUPPLY CURRENT (VREFB)
100
1000
V(VREFB) = 2 V
I(VREFB) = 100 µA
TJ = 25°C
V(VREFB) = 2 V
CS = 0.1 µF
TJ = 25°C
Slowstart Time – ms
Slowstart Time – ms
10
1
100
10
0.1
0
0.0001
0.0010
0.0100
0.1000
1
1
1
10
Slowstart Capacitance – µF
Figure 1
DRIVER
DRIVER
OUTPUT RISE TIME
vs
LOAD CAPACITANCE
OUTPUT FALL TIME
vs
LOAD CAPACITANCE
1000
Tj = 27 °C
Tj = 27 °C
100
t r – Rise Time – ns
t r – Rise Time – ns
1000
Figure 2
1000
High Side
10
100
High Side
10
Low Side
1
0.01
100
ICC – Supply Current (VREFB) – µA
Low Side
0.10
1.00
10.00
CL – Load Capacitance – nF
100.0
1
0.01
Figure 3
0.10
1.00
10.00
CL – Load Capacitance – nF
100.0
Figure 4
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13
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OVP THRESHOLD
vs
JUNCTION TEMPERATURE
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
118
105
OCP Threshold Voltage – mV
OVP Threshold – %
117
116
115
114
113
112
0
25
50
75
100
103
101
99
97
95
125
0
25
TJ – Junction Temperature – °C
Figure 5
100
125
INHIBIT HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
2.1
150
Inhibit Hysteresis Voltage – mV
Inhibit Start Threshold Voltage – V
75
Figure 6
INHIBIT START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.05
2
1.95
1.9
0
25
50
75
100
125
125
100
75
50
0
TJ – Junction Temperature – °C
25
50
Figure 8
POST OFFICE BOX 655303
75
100
TJ – Junction Temperature – °C
Figure 7
14
50
TJ – Junction Temperature – °C
• DALLAS, TEXAS 75265
125
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
UVLO START THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
10.5
2.5
VI = 12 V
2.3
UVLO Hysteresis – V
UVLO Start Threshold Voltage – V
VI = 12 V
10
9.5
2.1
1.9
1.7
9
0
25
50
75
100
1.5
125
0
TJ – Junction Temperature – °C
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 9
Figure 10
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
POWERGOOD THRESHOLD
vs
JUNCTION TEMPERATURE
6
95
VI = 12 V
Powergood Threshold – %
Quiescent Current – mA
94
4
2
93
92
91
0
0
25
50
75
100
125
90
0
TJ – Junction Temperature – °C
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 11
Figure 12
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15
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
DRIVER
SLOWSTART CHARGE CURRENT
vs
JUNCTION TEMPERATURE
REGULATOR VOLTAGE
vs
JUNCTION TEMPERATURE
15
8.5
14
8.25
Regulator Voltage – V
Slow Start Charge Current – µ A
V(VREFB) = 1.3 V
R(VREFB) = 20 kΩ
13
12
8
7.75
11
10
0
25
50
75
100
7.5
125
0
TJ – Junction Temperature – °C
25
Figure 13
100
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
125
6
RO – Low-Side Output Resistance – Ω
RO – High-Side Output Resistance – Ω
75
Figure 14
5
4
3
2
1
0
4
2
0
0
25
50
75
100
125
0
TJ – Junction Temperature – °C
25
50
Figure 16
POST OFFICE BOX 655303
75
100
TJ – Junction Temperature – °C
Figure 15
16
50
TJ – Junction Temperature – °C
• DALLAS, TEXAS 75265
125
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SENSING SAMPLE/HOLD RESISTANCE
vs
JUNCTION TEMPERATURE
100
RO – Sensing Sample/Hold Resistance – Ω
V(HISENSE) = 12 V
75
50
25
0
0
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 17
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17
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
The following figure is a typical application schematic. The circuit can be divided into the power-stage section
and the control-circuit section. The power stage must be tailored to the input/output requirements of the
application. The control circuit is basically the same for all applications with some minor tweaking of specific
values. Table 2 shows the values of the power stage components for various output-current options.
L101
L102
Q101
12V
Vo
R103
Q102
+
C101
C103
C102
R101
R102
C104
GND
RTN
VCC
15
1 uF 16
17
R1
3.40 k
1%
18
19
C6
20
0.033 uF
21
(see Note A) 22
ENABLE
23
R4
2.55 k
1%
24
C8
2200 pF
25
26
27
DRV
BOOT
LOWDR
HIGHDR
DRVGND
BOOTLO
LOHIB
HISENSE
LODRV
LOSENSE
BIAS
IOUTLO
SLOWST
INHIBIT
ANAGND
VID4
VSENSE
VID3
VREFB
VID2
VHYST
VID1
OCP
VID0
DROOP
PWRGD
IOUT
14
13
R11
10.0 k
11
C5
0.1 uF
C7
1000pF
R3 10.0 k
10
9
8
7
6
R5
5
100
4
R7
3.92 k
R8
1.00 k
R9
4.32 k
R10
1.00 k
3
R6
20.0 k
2
TPS5211
U1
NOTE A: VID0 – VID4 User – selected to set output voltage.
Figure 18. Standard Application Schematic
POST OFFICE BOX 655303
C4
1 uF
12
1
28
18
RTN
R2
150
C1
1 uF
C3
VSENSE
C2
1 uF
VSENSE_HF
LOHIB
LODRV
DRVGND
BOOTLO
LOSENSE
HIGHDRV
12V
Control Section
HISENSE
Power Stage
• DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
Table 2. Power Stage Components
Reference Designation
12-V–Input Power Stage Components
F nction
Function
4–A Out
8–A Out
12–A Out
20–A Out
C101
Input capacitor
muRata,
GRM235Y106Z016A,
2 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
4 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
6 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
10 x 10–uF, 16–V, Y5V
C102
Snubber capacitor
muRata,
GRM39X7R102K050A,
1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
2 x 1000–pF, 50–V, X7R
muRata,
GRM39X7R102K050A,
3 x 1000–pF, 50–V, X7R
C103
Output bulk
capacitor
Sanyo,
4TPC150M,
150–uF, 4–V, 20%
Sanyo,
4TPC150M,
2 x 150–uF, 4–V, 20%
Sanyo,
4TPC150M,
3 x 150–uF, 4–V, 20%
Sanyo,
4TPC150M,
4 x 150–uF, 4–V, 20%
C104
Output hi–freq
bypass capacitor
muRata,
GRM235Y106Z016A,
2 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
4 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
6 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
8 x 10–uF, 16–V, Y5V
L101
Input filter
inductor
CoilCraft,
DO1607C–152,
1.5–uH, 2.1–A
CoilCraft,
DO1813HC–122,
1.2–uH, 4.4–A
CoilCraft,
DO1813HC–122,
1.2–uH, 4.4–A
CoilCraft,
DO3316P–152HC,
1.5–uH, 9.0–A
L102
Output filter
inductor
CoilCraft,
DO1813HCP–561,
0.56–uH, 6–A
CoilCraft,
DO3316P–681HC,
0.68–uH, 12–A
Vishay–Dale,
IHLP–5050CE–XX,
0.82–uH, 16–A,
New product
Vishay–Dale,
IHLP–5050CE–XX,
0.5–uH, 25–A,
New product
R101
High–side gate
resistor
10.0–Ohm,
1/16–W, 5%
10.0–Ohm,
1/16–W, 5%
2 x 10.0–Ohm,
1/16–W, 5%
2 x 10.0–Ohm,
1/16–W, 5%
R102
Lo–side gate
resistor
3.3–Ohm,
1/16–W, 5%
3.3–Ohm,
1/16–W, 5%
2 x 3.3–Ohm,
1/16–W, 5%
3 x 3.3–Ohm,
1/16–W, 5%
R103
Snubber resistor
2.7–Ohm,
1/10–W, 5%
2.7–Ohm,
1/10–W, 5%
2 x 2.7–Ohm,
1/10–W, 5%
3 x 2.7–Ohm,
1/10–W, 5%
Q101
Power switch
IR, IRF7811,
NMOS, 11–mOhm
IR, IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
Q102
Synchronous switch
IR, IRF7811,
NMOS, 11–mOhm
IR, IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
Nominal frequency†
700 KHz
Hysteresis window
20 mV
† Nominal frequency measured with Vo set to 2 V.
The values listed above are recommendations based on actual test circuits. Many variations of the above are
possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not
more, dependent upon the layout than on the specific components, as long as the device parameters are not
exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the
operating frequencies of typical power supplies are relatively low compared to today’s microprocessor circuits,
the power levels and edge rates can cause severe problems both in the supply and the load. The power stage,
having the highest current levels and greatest dv/dt rates, should be given the greatest attention.
POST OFFICE BOX 655303
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TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
frequency calculation
The simplified equation shown below can be used for a preliminary frequency calculation:
fs ≅
V
VI
R11
*
x (V I V
)
REF
x 0.85
C7 x Hysteresis Window
REF
(1)
High frequency operations require special attention not to exceed maxium current through the controller
(120mA), and the maximum total power dissipation.
1400
1300
1200
1100
1000
Fmax( D)
900
kHz
800
Fm ( D)
kHz
Fmax With
External Driver
700
600
500
400
Fmax With
Internal Driver
300
200
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
D
Figure 19
Another restriction relates to the maximum rms current through the output of the highside driver, (110mA.) The
maximum allowable operating frequency can be defined by the following equation:
60ohm)
+ (110mA)
Qg x ǒV I ) VdrvǓ
2
Fmax
(2)
Where Qg = Total gate charge of the upper FETs in the hysteretic converter (in nanocoulombs)
Vdrv = 8 V and is the drive regulator voltage of the TPS5211 controller
VI = Input voltage
Fmax = Maximum switching frequency in kHz
Figure 19 and equation (2) should be used to determine the maximum operating frequency of a converter. The
operating frequency should not exceed the lower of the two values determined by Figure 19 and equation (2).
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
Control Section
Below are the equations needed to select the various components within the control section.
output voltage selection
The most important function of the power supply is to regulate the output voltage to a specific value. Values
between 1.3 V and 3.5 V can be easily set by shorting the correct VID inputs to ground. Values above the
maximum reference voltage (3.5 V) can be set by setting the reference voltage to any convenient voltage within
its range and selecting values for R2 and R3 to give the correct output. Select R3:
R3
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