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TPS53014
SLVSBF1A – MAY 2012 – REVISED FEBRUARY 2019
TPS53014 4.5-V to 28-V Input, D-CAP2™ synchronous buck controller
1 Features
3 Description
•
The TPS53014 is a single, adaptive on-time DCAP2™ mode synchronous buck controller. The
TPS53014 enables system designers to complete the
suite of various end equipment's power bus
regulators with cost effective low external component
count and low standby current solution. The main
control loop for the TPS53014 uses the D-CAP2
mode control which provides a very fast transient
response
with
no
external
compensation
components. The Adaptive on-time control supports
seamless transition between PWM mode at higher
load condition and Eco-mode™ operation at light
load. Eco-mode allows the TPS53014 to maintain
high efficiency during lighter load conditions. The
TPS53014 is also able to adapt to both low
equivalent series resistance (ESR) output capacitors
such as POSCAP or SP-CAP and ultra-low ESR
ceramic capacitors. The device provides convenient
and efficient operation with input voltages from 4.5 V
to 28 V and output voltage from 0.77 V to 7 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ mode control
– Fast transient response
– No external parts required for loop
compensation
– Compatible with ceramic output capacitors
High initial reference accuracy (±1%)
Wide input voltage range: 4.5 V to 28 V
Output voltage range: 0.77 V to 7.0 V
Low-side RDS(on) loss-less current sensing
Adjustable soft start
Non-sinking pre-biased soft start
500-kHz Switching frequency
Cycle-by-cycle overcurrent limiting control
Auto-Skip Eco-ModeTM for High Efficiency at Light
load
OCL/OVP/UVP/UVLO/TSD Protections
Adaptive Gate Drivers with Integrated Boost
PMOS Switch
Thermally Compensated OCP, 4000 ppm/°C
10 pin VSSOP
The TPS53014 is available in the 3-mm × 3-mm 10pin VSSOP (DGS) package and is specified for an
ambient temperature range of –40°C to +85°C.
Device Information(1)
PART NUMBER
2 Applications
•
TPS53014
Point-of-load regulation in low power systems for
wide range of applications
– Digital TV power supply
– Networking home terminal
– Digital set-top box (STB)
– DVD player / recorder
– Gaming consoles and other
PACKAGE
DGS (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VIN
TPS53014
VBST
10
DRVH
9
SW
8
EN
DRVL
7
VIN
PGND
6
1
VFB
2
SS
3
VREG5
EN
4
VIN
5
VOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53014
SLVSBF1A – MAY 2012 – REVISED FEBRUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
5
7
Absolute Maximum Ratings .....................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics .............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
Application and Implementation ........................ 15
8.1 Typical Application ................................................. 15
9
Layout ................................................................... 17
9.1 Layout Guidelines ................................................... 17
10 Device and Documentation Support ................. 18
10.1
10.2
10.3
10.4
10.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2012) to Revision A
•
2
Page
Editorial changes only; no technical changes; update to current TI data sheet standards for current content ..................... 1
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5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
TPS53014
VBST
10
DRVH
9
SW
8
EN
DRVL
7
VIN
PGND
6
1
VFB
2
SS
3
VREG5
4
5
Pin Functions
PIN
NAME
VSSOP-10
I/O
DESCRIPTION
VFB
1
I
D-CAP2 feedback input. Connect to output voltage with resistor divider.
SS
2
O
Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time.
VREG5
3
O
Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-μF high
quality ceramic capacitor. VREG5 is active when EN is asserted high.
EN
4
I
Enable. Pull High to enable converter.
VIN
5
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-μF high quality ceramic capacitor.
PGND
6
I
System ground.
DRVL
7
O
Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF)
and VREG5(ON).
SW
8
I/O
Switch node connections for both the high-side driver and over current comparator.
DRVH
9
O
High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and
VBST(ON).
VBST
10
I
High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal
diode is connected between VREG5 and VBST
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6 Specifications
6.1
Absolute Maximum Ratings
Operating under free-air temperature range (unless otherwise noted)
(1)
VALUE
Input voltage range
Output voltage range
VIN, EN
–0.3 to 30
VBST
–0.3 to 36
VBST - SW
–0.3 to 6
VFB
–0.3 to 6
SW
–0.3 to 30
SW (10 nsec transient)
–3.0 to 30
DRVH
–2 to 36
DRVH - SW
–0.3 to 6
DRVL, VREG5, SS
–0.3 to 6
PGND
UNIT
V
V
–0.3 to 0.3
TA
Operating ambient temperature range
–40 to 85
°C
TSTG
Storage temperature range
–55 to 150
°C
TJ
Junction temperature range
–40 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Recommended Operating Conditions
Supply input voltage range
MIN
MAX
4.5
28
VBST
–0.1
33.5
VBST - SW
–0.1
5.5
VFB
–0.1
5.5
EN
–0.1
28
SW
–1.0
28
DRVH
–1.0
33.5
DRVH - SW
–0.1
5.5
DRVL, VREG5, SS
–0.1
5.5
PGND
–0.1
0.1
VIN
Input voltage range
Output Voltage range
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
6.3 Thermal Information
THERMAL METRIC (1)
TPS53014
DGS (10 PINS)
UNITS
θJA
Junction-to-ambient thermal resistance
172.2
°C/W
θJCtop
Junction-to-case (top) thermal resistance
44.0
°C/W
θJB
Junction-to-board thermal resistance
93.0
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
91.4
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.4 Electrical Characteristics
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
VIN Supply current
IVINSDN
VIN Shutdown current
VIN current, TA = 25°C, EN = 5V, VVFB = 0.8V,
VSW = 0 V
660
VIN current, TA = 25°C, No Load , VEN = 0V,
VREG5 = OFF
6.0
μA
μA
VFB VOLTAGE and DISCHARGE RESISTANCE
VVFBTHL
VFB Threshold voltage
TA = 25°C , VOUT = 1.05 V
(1)
TCVFB
VFB Temperature coefficient
Relative to TA = 25°C
IVFB
VFB Input current
VFB = 0.8V, TA = 25°C
765.3
773.0
-140
-150
-10
780.7
mV
140
ppm/°C
100
nA
VREG5 OUTPUT
VVREG5
VREG5 Output voltage
TA=25°C, 6 V < VIN < 28 V, IVREG5 = 5 mA
5.1
V
IVREG5
Output current
VIN = 5.5V, VVREG5 = 4.0V, TA = 25°C
120
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
TD
Dead time
Source, IDRVH = –50mA, TA = 25°C
3.2
4.7
Sink, IDRVH = 50mA, TA = 25°C
1.4
2.4
Source, IDRVL = –50mA, TA = 25°C
6.9
8.2
Sink, IDRVL = 50mA, TA = 25°C
0.8
1.7
DRVH-low to DRVL-on (1)
15
DRVL-low to DRVH-on (1)
20
VVREG5-VBST, IF = 10mA, TA = 25°C
0.1
0.2
-7.36
-6.4
-5.44
4.5
5.0
Ω
Ω
ns
INTERNAL BOOST DIODE
VFBST
Forward voltage
V
SOFT START
Issc
SS Charge current
VSS = 0V , TA = 25°C
Issd
SS Discharge current
VSS = 0.5V , TA = 25°C
TCISSC
ISSC Temperature coefficient
Relative to TA = 25°C
-4.5
μA
mA
4.5
nA/°C
UVLO
VUVVREG5
VREG5 UVLO threshold
VREG5 Rising
4.0
Hysteresis
0.3
V
LOGIC THRESHOLD
VENH
EN H-level threshold voltage
VENL
EN L-level threshold voltage
REN
EN pin resistance to GND
1.6
V
0.5
V
VEN = 12 V
225
450
900
kΩ
14.3
15
15.8
μA
CURRENT SENSE
ITRIP
TRIP Source current
VDRVL = 0.1V, TA = 25°C
TCVTRIP
VTRIP Temperature coefficient
Relative to TA = 25°C
VOCL
Current limit threshold
4000
ppm/°C
RTRIP = 75kΩ, TA = 25°C
234
336
424
RTRIP = 27kΩ, TA = 25°C
121
174
220
RTRIP = 6.8kΩ, TA = 25°C
35
50
63
mV
ON-TIME TIMER CONTROL
TON
On time
VOUT = 1.05 V (1)
250
ns
TOFF(MIN)
Minimum off time
VIN = 4.5 V, VVFB = 0.7 V, TA = 25°C
230
ns
(1)
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
115%
120%
125%
UNIT
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
TOVPDEL
Output OVP propagation delay
VUVP
Output UVP trip threshold
TUVPDEL
Output UVP delay
TUVPEN
Output UVP enable delay
OVP detect voltage
10
UVP detect voltage
63%
68%
73%
1
UVP enable delay / soft start time
X1.4
X1.7
μs
ms
X2.0
THERMAL SHUTDOWN
TSDN
6
Thermal shutdown threshold
Shutdown temperature (1)
Hysteresis (1)
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150
°C
25
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6.5 Typical Characteristics
1200
12
1000
10
Supply Current−Shutdown Current (µA)
Supply Current (µA)
VIN = 12 V, TA= 25°C (unless otherwise noted)
800
600
400
200
8
6
4
2
VIN = 12 V
0
−50
0
50
100
Junction Temperature (°C)
VIN = 12 V
0
−50
150
0
50
100
Junction Temperature (°C)
150
G001
G002
Figure 1. VIN Supply Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs Junction Temperature
600
80
70
500
Switching Frequency (kHz)
EN Input Current (µA)
60
50
40
30
400
300
200
20
100
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
10
IOUT = 3 A
VIN = 12 V
0
0
5
10
15
20
EN Input Voltage (V)
25
30
0
−50
0
50
100
Junction Temperature (°C)
G003
Figure 3. En Input Current Vs En Input Voltage
150
G004
Figure 4. Switching Frequency vs Junction Temperature
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
600
0.800
0.795
0.790
0.785
400
VFB Voltage (V)
Switching Frequency (kHz)
500
300
200
0.775
0.770
0.765
0.760
100
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
IOUT = 3 A
0
0.780
0
5
10
15
20
Input Voltage (V)
25
0.755
0.750
30
IOUT = 50 mA
IOUT = 2 A
0
5
10
15
20
Input Voltage (V)
25
30
G005
G006
Figure 6. Vfb Voltage vs Input Voltage
0.800
1.10
0.795
1.09
0.790
1.08
0.785
1.07
Output Voltage (V)
VFB Voltage (V)
Figure 5. Switching Frequency vs Input Voltage
0.780
0.775
0.770
1.06
1.05
1.04
0.765
1.03
0.760
1.02
0.755
0.750
−50
0
50
100
Ambient Temperature (°C)
VIN = 5 V
VIN = 12 V
VIN = 28 V
1.01
IOUT = 50 mA
IOUT = 2 A
150
1.00
0.0
1.0
2.0
3.0
4.0
5.0
Output Current (A)
6.0
G007
Figure 7. Vfb Voltage vs Ambient Temperature
8
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7.0
8.0
G008
Figure 8. Load Regulation
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
1.10
1.09
VO (50 mV/div ac coupled)
1.08
Output Voltage (V)
1.07
1.06
1.05
IOUT (5 A/div)
1.04
1.03
1.02
1.01
1.00
Slew Rate (0.3 A/µsec)
IOUT = 50 mA
IOUT = 2 A
0
5
10
15
20
Input Voltage (V)
25
Time Scale (100 µsec/div)
30
G009
Figure 10. Transient Response
Figure 9. Line Regulation
100
EN (10 V/div)
90
80
VREG5 (5 V/div)
70
Efficiency (%)
VO (500 mV/div)
SS (2 V/div)
60
50
40
30
20
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
10
Time (1 msec/div)
VIN = 12 V
0
0.0
1.0
2.0
3.0
4.0
5.0
Output Current (A)
6.0
7.0
8.0
G012
Figure 11. Start Up Waveforms
Figure 12. Efficiency
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
100
90
VO = 1.05 V
VO (20 mV/div ac coupled)
80
Efficiency (%)
70
60
50
SW (5 V/div)
40
30
20
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
10
VIN = 12 V
0
0.001
0.01
0.1
Output Current (A)
1
Time (1 µsec/div)
10
G013
Figure 13. Light Load Efficiency
VO = 1.05 V
VO (20 mV/div ac coupled)
SW (5 V/div)
Figure 14. Output Voltage Ripple, IOUT = 8 A
VO = 1.05 V
SW (5 V/div)
Time (1 µsec/div)
Time (10 µsec/div)
Figure 15. Output Voltage Ripple, IOUT = 50 mA
10
VIN (50 mV/div ac coupled)
Figure 16. Input Voltage Ripple, IOUT = 8 A
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
VO = 1.05 V
VIN (10 mV/div ac coupled)
SW (5 V/div)
Time (10 µsec/div)
Figure 17. Input Voltage Ripple, IOUT = 50 mA
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7 Detailed Description
7.1 Overview
The TPS53014 is single synchronous step-down (buck) controller. It operates using D-CAP2™ mode control.
The fast transient response of D-CAP2™ control reduces the required amount of output capacitance to meet a
specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including
ceramic and special polymer types.
7.2 Functional Block Diagram
VREG5
TPS53014
-32%
+
+
VFB
+20%
-
REF
SS
+
+
-
1
VBST
VIN
10
UV
DRVH
CONTROL
LOGIC
OV
9
SW
XCON
VOUT
8
VREG5
DRVL
7
1
SHOT
PGND
6
10µA
PGND
6.4µA
SGND
OCL
SS
2
+
ADC
SW
VIN
5
SGND
EN
EN
4
EN
LOGIC
UV
OV
UVLO
TSD
VIN
VREG5
SS LOGIC
3
VREG5
REF
REF
UVLO
PGND
PROTECTION
LOGIC
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS53014 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the
beginning of each cycle, the high-side MOSFET is turned on. this MOSFET is turned off when the internal timer
expires. This timer is set by the converter input voltage VIN, and the output voltage VO, to maintain a pseudofixed frequency over the input voltage range, hence it is called adaptive on-time control. The timer is reset and
the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An
internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced
output ripple from D-CAP2™ mode control.
12
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Feature Description (continued)
7.3.2 Auto-Skip Eco-Mode™ Control
The TPS53014 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point where
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost half
as is was in the continuous conduction mode because it takes longer time to discharge the output capacitor with
smaller load current to the level of the reference voltage. The transition point to the light load operation IOX(LL)
current can be calculated in Equation 1 with 500kHz used as fsw.
(V -V )×VOUT
1
IOUT(LL) =
× IN OUT
2×L×fSW
VIN
(1)
7.3.3 Drivers
TPS53014 contains two high-current resistive MOSFET gate drivers. The low-side driver is a PGND referenced,
VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET whose
source is connected to PGND. The high-side driver is a floating SW referenced, VBST powered driver designed
to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage during the
high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to
Gate Charge (Qg @ Vgs = 5V) times Switching frequency (fsw). To prevent cross-conduction, there is a narrow
dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the
inductor current is carried by one of the MOSFETs body diodes.
7.3.4 5-Volt Regulator
The TPS53014 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all both
drivers and the ICs internal logic. A high-quality 4.7µF or greater ceramic capacitor from VREG5 to GND is
required to stabilize the internal regulator.
7.3.5 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6.4-µA current begins charging the
capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during
start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.773 V and SS pin source
current is 6.4-µA.
t
SS
(ms) =
CSS (nF) x VFB(V)
I (mA)
SS
=
CSS (nF) x 0.773 V
6.4mA
(2)
The TPS53014 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VO) starts
and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
7.3.6 Overcurrent Protection
TPS53014 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53014 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, a resister should
be connected between DRVL and PGND. The recommended values are given inTable 1.
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Table 1. OCL Resistor Values
RESISTER VALUE ( kΩ)
Vtrip (V)
6.8
0.050
11
0.087
18
0.125
27
0.174
39
0.224
56
0.274
75
0.336
IOCL is determined by Equation 3.
æ (V -V
) V ö V
IOCL = ç IN OUT × OUT ÷ + TRIP
ç 2×L×f
VIN ÷ø RDS(ON)
SW
è
(3)
The trip voltage is set between 0.05 V to 0.336 V over all operational temperature, including the 4000ppm/°C
temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the
overcurrent limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall
below the under voltage protection threshold and the TPS53014 will shut down.
7.3.7 Over/Undervoltage Protection
TPS53014 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 120% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 68% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 1ms, TPS53014 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 × Tss after power-on. The OVP and UVP latch off is
reset when EN goes low.
7.3.8 UVLO Protection
TPS53014 has under voltage lock out protection (UVLO) that monitors the voltage of VREG5 pin. When the
VREG5 voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF. The
UVLO is non-latch protection.
7.3.9 Thermal Shutdown
TPS53014 monitors its temperature. If the temperature exceeds the threshold value (typically 150°C), the device
shuts off. When the temperature falls below the threshold, the IC starts again. When VIN starts up and VREG5
output voltage is below its nominal value, the thermal shutdown threshold is kept lower than 150°C. As long as
VIN rises, TJ must be kept less than 110°C.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Typical Application
A typical application schematic is shown in Figure 18.
VIN
R1
3.96k
R2
10.0k
C1
0.01µF
C2
4.7µF
SGND
VIN
EN
1
TPS53014
VBST
VFB
2
SS
3
VREG5
4
5
C3
10µF
C5
10µF
10
DRVH
9
SW
8
EN
DRVL
7
VIN
PGND
6
Q1
CSD17307Q5A
L1 1.5µH
C4
0.1µF
VOUT
Q2
CSD17510Q5A
R3
C6
22µF
C7
22µF
C8
22µF
PGND
PGND
Figure 18. Application Schematic
8.1.1 Detailed Design Procedure
8.1.1.1 Component Selection
8.1.1.1.1 Inductor
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 4 can be used to calculate te value for LOUT.
VIN(MAX) -VOUT
V
L OUT =
× OUT
IL(RIPPLE) ×fSW VIN(MAX)
(4)
The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current.
The RMS and peak inductor current can be estimated as follows:
VIN(MAX) -VOUT
V
IL(RIPPLE) =
× OUT
LOUT ×fSW
VIN(MAX)
(5)
V
IL(PEAK) = TRIP +IL(RIPPLE)
RDS(ON)
2
IL(RMS) = IOUT + 1 ×IL(RIPPLE)
12
(6)
2
(7)
Note:
The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.
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Typical Application (continued)
8.1.1.1.2 Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Ceramic output capacitors with X5R dielectric or better are recommended .
IL(RIPPLE)
1
COUT =
×
8×VOUT(RIPPLE) fSW
(8)
2
COUT =
ΔILOAD
×L OUT
2×VOUT ×ΔVOS
(9)
2
COUT =
ΔILOAD
×L OUT
2×K×ΔVUS
(10)
Where:
K= (VIN -VOUT )×
•
•
•
TON
TON -TOFF(MIN)
ΔVOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
TOFF(MIN) = Minimum off time
(11)
Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and
Equation 10. The minimum recommended output capacitance is 44 μF.
8.1.1.1.3 Input Capacitor
The TPS53014 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
8.1.1.1.4 Bootstrap Capacitor
The TPS53014 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side
drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The capacitor voltage rating should
be greater than 10 V.
8.1.1.1.5 VREG5 Capacitor
The TPS53014 requires that the VREG5 regulator is bypassed. A minimum 4.7-μF high-quality ceramic capacitor
must be connected between the VREG5 and PGND for proper operation. The capacitor voltage rating should be
greater than 10 V.
8.1.1.1.6 Choose Output Voltage Resistors
The output voltage is set with a resistor divider from output voltage node to the VFB pin. TI recommends using
1% tolerance or better resistors. Select R2 between 10 kΩ and 100 kΩ and use Equation 12 to calculate R1.
æV
ö
R1 = ç OUT -1÷ ×R2
V
è VFB ø
(12)
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9 Layout
9.1 Layout Guidelines
•
•
•
•
•
•
Keep the input switching current loop as small as possible.
Place the input capacitor close to the top switching FET. Keep the output current loop as small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (VFB) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.3 Trademarks
D-CAP2, Eco-mode, Eco-Mode, E2E are trademarks of Texas Instruments.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
18
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53014DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
53014
TPS53014DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
53014
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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