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TPS53015
SLVSBF0C – JULY 2012 – REVISED APRIL 2019
TPS53015 4.5-V to 28-V Input, D-CAP2TM Synchronous Step-Buck Converter With PGOOD
1 Features
3 Description
•
The TPS53015 device is a single, adaptive on-time
D-CAP2 ™ mode synchronous buck controller. The
device enables system designers to complete the
suite of various end equipment power bus regulators
with cost effective low external component count and
low standby current solution. The main control loop
for the TPS53015 uses the D-CAP2 mode control
which provides a very fast transient response with no
external compensation components. The adaptive ontime control supports seamless transition between
PWM mode at higher load condition and Eco-mode™
operation at light load. Eco-mode operation allows the
device to maintain high efficiency during lighter load
conditions. The device is also able to adapt to both
low equivalent series resistance (ESR) output
capacitors such as POSCAP or SP-CAP and ultralow ESR ceramic capacitors. The device provides
convenient and efficient operation with input voltages
from 4.5 V to 28 V and output voltage from 0.77 V to
7 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ mode control
– Fast transient response
– No external parts required for loop
compensation
– Compatible with ceramic output capacitors
High initial reference accuracy (±1%)
Wide input voltage 4.5 V to 28 V
Output voltage 0.77 V to 7 V
Low-side RDS(on) Loss-less current sensing
Fixed soft-start time: 1.4 ms
Non-sinking pre-biased soft start
Switching frequency: 500 kHz
Cycle-by-cycle overcurrent limiting control
Auto-Skip Eco-Mode™ for high efficiency at light
load
Power-good output
OCL/OVP/UVP/UVLO/TSD protections
Adaptive gate drivers with integrated boost PMOS
switch
Thermally compensated OCP, 4000 ppm/°C
10-Pin VSSOP
The TPS53015 is available in the 3-mm × 3-mm 10pin VSSOP (DGS) package and is specified for an
ambient temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS53015
2 Applications
•
PACKAGE
DGS (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Point-of-load regulation in low power systems for
wide range of applications
– Digital TV power supply
– Networking home terminal
– Digital set top box (STB)
– DVD player / recorder
– Gaming consoles and other
Simplified Application
VIN
TPS53015
1
VFB
VBST 10
2
PG
DRVH
9
3
VREG5
SW
8
EN
4
EN
DRVL
7
VIN
5
VIN
PNGD
6
PG
VOUT
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53015
SLVSBF0C – JULY 2012 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
Detailed Description ............................................ 13
11.1 Trademarks ........................................................... 22
11.2 Electrostatic Discharge Caution ............................ 22
11.3 Glossary ................................................................ 22
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (August 2012) to Revision C
•
Page
Update to latest TI documentation standards ........................................................................................................................ 1
Changes from Revision A (July 2012) to Revision B
Page
•
Changed "Adjustable soft-start" to "1.4 ms Fixed soft-start" in Features list.......................................................................... 1
•
Added "Power Good Output" to Features list ......................................................................................................................... 1
•
Changed literature number from revision A to revision B....................................................................................................... 1
•
Changed from "SS" to "PG" in the Absolute Maximum Ratings table.................................................................................... 4
•
Changed from "SS" to "PG" in the Recommended Operating Conditions table .................................................................... 4
•
Changed TSS spec from "1.0 ms" to "1.4 ms" Typical ............................................................................................................ 6
•
Changed TPGDLY spec from "1.5 ms" to "1.2 ms".................................................................................................................... 6
•
Changed TPGCOMPSS spec from "2.2 ms" to "2.3 ms" .............................................................................................................. 6
•
Changed MIN tUVPEN specification from "1.4 ms" to "1.7 ms" ................................................................................................. 7
•
Changed TYP tUVPEN specification from "1.7 ms" to "2.2 ms"................................................................................................. 7
•
Changed MAX tUVPEN specification from "2.0 ms" to "2.7 ms"................................................................................................ 7
•
Changed soft-start time from "1.0 ms" to "1.4 ms" in .......................................................................................................... 14
•
Changed adjusted reference to UVP delay timing from "1.7 ms" to "2.2 ms" in the section................................................ 14
•
Added section describing POWER GOOD operation........................................................................................................... 15
Changes from Original (July 2012) to Revision A
2
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SLVSBF0C – JULY 2012 – REVISED APRIL 2019
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
VFB
1
10
VBST
PG
2
9
VREG5
3
8
DRHV
SW
EN
4
7
DRVL
VIN
5
6
PGND
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
DRVH
9
O
High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and
VBST(ON).
DRVL
7
O
Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF)
and VREG5(ON).
EN
4
I
Enable. Pull high to enable converter.
PG
2
O
Open drain power good output.
PGND
6
I
System ground.
SW
8
I/O
VBST
10
I
High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal
diode is connected between VREG5 and VBST
VFB
1
I
D-CAP2 feedback input. Connect to output voltage with resistor divider.
VIN
5
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-μF high quality ceramic capacitor.
VREG5
3
O
Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-μF highquality ceramic capacitor. VREG5 is active when EN is asserted high.
(1)
Switch node connections for both the high-side driver and overcurrent comparator.
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Input voltage range
MIN
MAX
VIN, EN, SW
–0.3
30
VBST
–0.3
36
(VBST - SW), VFB
–0.3
6
SW (10 ns transient)
–3.0
30
DRVH
Output voltage range
–2
36
DRVH - SW
–0.3
6
DRVL, VREG5, PG
–0.3
6
UNIT
V
V
PGND
–0.3
0.3
Junction temperature range, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to device GND terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply input voltage range
Input voltage range
Output Voltage range
MIN
MAX
4.5
28
VBST
–0.1
33.5
VBST - SW
–0.1
5.5
VFB
–0.1
5.5
EN
–0.1
28
SW
–1.0
28
DRVH
–1.0
33.5
DRVH - SW
–0.1
5.5
DRVL, VREG5, PG
–0.1
5.5
PGND
–0.1
0.1
VIN
UNIT
V
V
V
Operating free-air temperature, TA
–40
85
°C
Operating junction temperature, TJ
–40
125
°C
6.4 Thermal Information
TPS53015
THERMAL METRIC
(1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
109.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information (continued)
TPS53015
THERMAL METRIC (1)
DGS (VSSOP)
UNIT
10 PINS
RθJB
Junction-to-board thermal resistance
54.7
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
54.1
°C/W
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6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V(unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
Supply current
VIN current, EN = 5 V, VVFB = 0.8 V,
VSW = 0 V,
TA = 25°C
660
μA
IVINSDN
Shutdown current
VIN current, TA = 25°C, No Load ,
VEN = 0V, VREG5 = OFF
6.0
μA
VFB VOLTAGE and DISCHARGE RESISTANCE
VVFBTHL
Threshold voltage
(1)
VOUT = 1.05 V, TA = 25°C
765.3
773.0
780.7
mV
TCVFB
Temperature coefficient
TA = 25°C
–140
IVFB
Input current
VFB = 0.8V, TA = 25°C
–150
VVREG5
Output voltage
TA=25°C, 6 V < VIN < 28 V, IVREG5 =
5 mA
5.1
V
IVREG5
Output current
VVIN = 5.5 V, VVREG5 = 4.0 V, TA =
25°C
120
mA
Source, IDRVH = –50 mA, TA = 25°C
3.2
4.7
Sink, IDRVH = 50 mA, TA = 25°C
1.4
2.4
Source, IDRVL = –50 mA, TA = 25°C
6.9
8.2
Sink, IDRVL = 50 mA, TA = 25°C
0.8
1.7
DRVH-low to DRVL-on
15
DRVL-low to DRVH-on
20
VVREG5-VBST, IF = 10 mA, TA = 25°C
0.1
-10
140
ppm/°C
100
nA
VREG5 OUTPUT
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
Resistance
RDRVL
Resistance
tD
Dead-time (1)
Ω
Ω
ns
INTERNAL BOOST DIODE
VFBST
Forward voltage
0.2
V
SOFT-START TIME
tss
Internal soft-start time
1.4
ms
PGOOD LOW
84
%
PGOOD HIGH
116
%
5
mA
1.2
ms
POWER GOOD
VPGTH
PGOOD threshold
IPG
PGOOD sink current
tPGDLY
PGOOD delay time
tPGCOMPSS
PGODD comparator start-up delay
VPG = 0.5 V
Delay for PGOOD in
Delay for PGOOD out
2
µs
PGOOD comparator wake up delay
2.3
ms
VREG5 Rising
4.0
Hysteresis
0.3
UVLO
VUVVREG5
VREG5 UVLO threshold
V
LOGIC THRESHOLD
VENH
High-level threshold voltage
VENL
Low-level threshold voltage
REN
EN pin resistance to GND
1.6
VEN = 12 V
225
14.3
V
0.5
V
450
900
kΩ
15
15.8
CURRENT SENSE
ITRIP
Source current
VDRVL = 0.1 V, TA = 25°C
TCVTRIP
VTRIP Temperature coefficient
Relative to TA = 25°C
VOCL
Current limit threshold
(1)
6
4000
μA
ppm/°C
RTRIP = 75 kΩ, TA = 25°C
234
336
424
RTRIP = 27 kΩ, TA = 25°C
121
174
220
RTRIP = 6.8 kΩ, TA = 25°C
35
50
63
mV
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 12 V(unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ON-TIME TIMER CONTROL
tON
On-time (1)
VOUT = 1.05 V
250
ns
tOFF(min)
Minimum off-time
VIN = 4.5 V, VVFB = 0.7 V, TA = 25°C
230
ns
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
tOVPDEL
Output OVP propagation delay
VUVP
Output UVP trip threshold
tUVPDEL
Output UVP delay
tUVPEN
Output UVP enable delay
OVP detect voltage
115%
120%
125%
UVP detect voltage
63%
68%
73%
1.7
2.2
10
1
μs
ms
2.7
ms
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature (1)
Hysteresis (1)
150
25
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7
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6.6 Typical Characteristics
1200
12
1000
10
Supply Current−Shutdown Current (µA)
Supply Current (µA)
VIN = 12 V, TA= 25°C (unless otherwise noted)
800
600
400
200
8
6
4
2
VIN = 12 V
0
−50
0
50
100
Junction Temperature (°C)
VIN = 12 V
0
−50
150
0
50
100
Junction Temperature (°C)
150
G001
G002
Figure 1. VIN Supply Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs Junction Temperature
600
80
70
500
Switching Frequency (kHz)
EN Input Current (µA)
60
50
40
30
400
300
200
20
100
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
10
IOUT = 3 A
VIN = 12 V
0
0
5
10
15
20
EN Input Voltage (V)
25
30
0
−50
G003
Figure 3. EN Input Current vs EN Input Voltage
8
0
50
100
Junction Temperature (°C)
150
G004
Figure 4. Switching Frequency vs Junction Temperature
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
600
0.800
0.795
0.790
0.785
400
VFB Voltage (V)
Switching Frequency (kHz)
500
300
200
0.775
0.770
0.765
0.760
100
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
IOUT = 3 A
0
0.780
0
5
10
15
20
Input Voltage (V)
25
0.755
0.750
30
IOUT = 50 mA
IOUT = 2 A
0
5
10
15
20
Input Voltage (V)
25
30
G005
G006
Figure 6. VFB Voltage vs Input Voltage
0.800
1.10
0.795
1.09
0.790
1.08
0.785
1.07
Output Voltage (V)
VFB Voltage (V)
Figure 5. Switching Frequency vs Input Voltage
0.780
0.775
0.770
1.06
1.05
1.04
0.765
1.03
0.760
1.02
0.755
0.750
−50
0
50
100
Ambient Temperature (°C)
VIN = 5 V
VIN = 12 V
VIN = 28 V
1.01
IOUT = 50 mA
IOUT = 2 A
150
1.00
0.0
1.0
2.0
3.0
4.0
5.0
Output Current (A)
6.0
7.0
G007
Figure 7. VFB Voltage vs Ambient Temperature
G008
Figure 8. Load Regulation
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9
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
1.10
1.09
VO (50 mV/div ac coupled)
1.08
Output Voltage (V)
1.07
1.06
1.05
IOUT (5 A/div)
1.04
1.03
1.02
1.01
1.00
Slew Rate (0.3 A/µsec)
IOUT = 50 mA
IOUT = 2 A
0
5
10
15
20
Input Voltage (V)
25
Time Scale (100 µsec/div)
30
G009
Figure 10. Transient Response
Figure 9. Line Regulation
100
EN (10 V/div)
90
80
70
Efficiency (%)
VREG5 (5 V/div)
VO (500 mV/div)
60
50
40
30
PG (5 V/div)
20
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
10
VIN = 12 V
Time (1 msec/div)
0
0.0
Figure 11. Start-Up Waveforms
10
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1.0
2.0
3.0
4.0
5.0
Output Current (A)
6.0
7.0
8.0
G012
Figure 12. Efficiency vs. Output Current
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
100
90
VO = 1.05 V
VO (20 mV/div ac coupled)
80
Efficiency (%)
70
60
50
SW (5 V/div)
40
30
20
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
10
VIN = 12 V
0
0.001
0.01
0.1
Output Current (A)
1
Time (1 µsec/div)
10
IOUT = 8 A
G013
Figure 13. Light Load Efficiency vs. Output Current
Figure 14. Output Voltage Ripple
VO = 1.05 V
VO (20 mV/div ac coupled)
SW (5 V/div)
VO = 1.05 V
VIN (50 mV/div ac coupled)
SW (5 V/div)
Time (1 µsec/div)
Time (10 µsec/div)
IOUT = 50 mA
IOUT = 8 A
Figure 15. Output Voltage Ripple
Figure 16. Input Voltage Ripple
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Typical Characteristics (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
VO = 1.05 V
VIN (10 mV/div ac coupled)
SW (5 V/div)
Time (10 µsec/div)
IOUT = 50 mA
Figure 17. Input Voltage Ripple
12
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7 Detailed Description
7.1 Overview
The TPS53015 is single synchronous step-down buck controller. It operates using D-CAP2 mode control. The
fast transient response of D-CAP2 control reduces the required amount of output capacitance to meet a specific
level of performance. Proprietary internal circuitry allows the use of low-ESR output capacitors including ceramic
and special polymer types.
7.2 Functional Block Diagram
± 32%
+
UV
+
OV
+20%
VFB
1
VREG
REF
SS
+
+
Control Logic
10 VBST
10 µA
ADC
SW
+ 16%
9
+
OCL
DRVH
8 SW
+
XCON
VREG
+
± 16%
PG
OneShot
2
UV
EN
4
Enable
Logic
SS Logic
OV
UVLO
Protection
Logic
TSD
VREG5
REF
REF
7
DRVL
6
PGND
5
VIN
3
VREG5
UVLO
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7.3 Feature Description
7.3.1 Drivers
The TPS53015 device contains two high-current resistive MOSFET gate drivers. The low-side driver is a PGND
referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET
whose source is connected to PGND. The high-side driver is a floating SW referenced, VBST powered driver
designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage
during the high-side driver ON-time, a capacitor is placed from SW to VBST. Each driver draws average current
equal to gate charge (Qg and Vgs = 5 V) times switching frequency (fSW). To prevent cross-conduction, there is a
narrow dead-time when both high-side and low-side drivers are OFF between each driver transition. During this
time the inductor current is carried by one of the MOSFETs body diodes.
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Feature Description (continued)
7.3.2 5-Volt Regulator
The TPS53015 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the device internal logic. A high-quality 4.7-µF or greater ceramic capacitor from VREG5 to GND is required
to stabilize the internal regulator.
7.3.3 Soft-Start and Pre-biased Soft-Start Time
The TPS53015 operates with an internally set, 1.4-ms soft-start time. When the EN pin becomes high and the
VREG5 voltage is above the UVLO threshold, an internal DAC ramps up the reference voltage to the PWM
comparator. Smooth control of the output voltage is maintained during start up.
The device contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start
time becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous
rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that ontime on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the
converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage
(VOUT) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
7.3.4 Overcurrent Protection
The TPS53015 device has a cycle-by-cycle over current limit feature. The over current limits the inductor valley
current by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If
the inductor current is larger than the overcurrent limit (OCL), the device delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, a resister should
be connected between DRVL and PGND. The recommended values are given inTable 1.
Table 1. OCL Resistor Values
Resistor Value ( kΩ)
VTRIP (V)
6.8
0.050
11
0.087
18
0.125
27
0.174
39
0.224
56
0.274
75
0.336
Use Equation 1 to calculate IOCL.
æ (V -V
) V ö V
IOCL = ç IN OUT × OUT ÷ + TRIP
ç 2×L×f
VIN ÷ø RDS(ON)
SW
è
(1)
The trip voltage is set between 0.05 V to 0.336 V over all operational temperature, including the 4000ppm/°C
temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the
overcurrent limit, the voltage begins to drop. If the overcurrent conditions continues the output voltage falls below
the undervoltage protection threshold and the device shuts down.
7.3.5 Overvoltage and Undervoltage Protection
The TPS53015 device monitors a resistor divided feedback voltage to detect an overvoltage or undervoltage
condition. If the feedback voltage is higher than 120% of the reference voltage, the OVP comparator output goes
high and the circuit latches the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 68% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 1 ms, the device latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 2.2 ms after power-on. The OVP and UVP latch off is
reset when EN goes low.
14
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7.3.6 UVLO Protection
The TPS53015 offers undervoltage lockout protection (UVLO) by monitoring the voltage of VREG5 pin. When the
VREG5 pin voltage is lower than UVLO threshold voltage, the device shuts off. All output drivers are OFF. The
UVLO is non-latch protection.
7.3.7 Thermal Shutdown
During normal operation, when the temperature of the TPS53015 device exceeds the threshold value (typically
150°C), the device shuts off. When the temperature falls below the threshold, the device starts again. During VIN
start-up when the VREG5 output voltage is below its nominal value, the device maintains the thermal shutdown
threshold lower than 150°C. During the period where VIN rises, the junction temperature (TJ) must be maintained
at lower than 110°C.
7.3.8 Power Good
The VFB pin measures the power-good output and the function activates after the soft-start period has
completed. If the output voltage is within ±16% of the target voltage, the internal comparator detects the powergood state and the power-good signal becomes high after 1.2-ms delay. During start-up, this internal delay starts
after 2.2 times the soft-start time to avoid a glitch of power-good signal. If the feedback voltage goes outside
±16% of target value, the power-good signal becomes low after 2-µs delay.
7.4 Device Functional Modes
7.4.1 PWM Operation
The main control loop of the TPS53015 device is an adaptive on-time pulse width modulation (PWM) controller
that supports a proprietary D-CAP2 control mode. D-CAP2 control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the
beginning of each cycle, the high-side MOSFET is turned on. this MOSFET is turned off when the internal timer
expires. This timer is set by the converter input voltage VIN, and the output voltage (VOUT) to maintain a pseudofixed frequency over the input voltage range, hence it is called adaptive on-time control. The timer is reset and
the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An
internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced
output ripple from D-CAP2 mode control.
7.4.2 Auto-skip Eco-Mode Control
The TPS53015 operates in Auto-Skip Eco-mode to increase light-load efficiency. As the output current decreases
from heavy load condition, the inductor current is also reduced and eventually comes to point where its rippled
valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The rectifying MOSFET turns off when the device detects a zero inductor current. As the load current
further decreases, the converter transitions into discontinuous conduction mode. The on-time is maintained to
almost half of what it was during continuous conduction mode operation because it takes longer to discharge the
output capacitor with a smaller load current to the level of the reference voltage. Use Equation 2 to calculate the
transition point to the light-load operation current (IOX(LL)) using a 500-kHz switching frequency.
(V -V )×VOUT
1
IOUT(LL) =
× IN OUT
2×L×fSW
VIN
(2)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This design example describes a D-CAP2 mode control in a cost sensitive application. Providing a 1.05-V output
at up to 8 A from a loosely regulated 12 V (8 V – 22 V) source, this design demonstrates the TPS53015 in a
typical point-of-load application.
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Disable (Default)
Enable
VIN
1.00k
R8
1.00k
R6
6
4
5
1
2
4.7uF
C11
140
R11
J1
VREG5
TP3
AGND
EN
TP5
S1
SW_G12AP
Enable Circuitry
PG
TP4
VOUT
PWRGND
VIN
8V - 22V
GND
VIN
VIN
1
C10
R4
R3
SH1
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C1
C13
TP9
GND
0.1uF
5
4
3
2
1
VIN
EN
VBST
6
7
8
9
10
D1
BAT54XV2T1
PGND
DRVL
SW
DRVH
NOT POPULATED
1
C4
VREG5
PG
1
C2
10uF
U1
TPS53015DGS
VFB
10uF
Notes:
23.7k
8.66k
R1
TP2
GND
VIN
TP1
C3
2.05
R7
5.11
R5
10uF
15.4k
R10
C5
G
G
Q2
CSD17507Q5A
0.1uF
10.0
R2
S
D
S
D
TP10
1000pF
C12
3.01
R9
SW
TP6
Q1
CSD17507Q5A
1.5uH
L1
22uF
C6
22uF
C7
1
C8
1
C9
TP8
GND
VOUT
TP7
GND
VOUT
1.05V/8A
J2
PWRGND
1
2
VOUT
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TPS53015
8.2 Typical Application
Figure 18. POL Application Using TPS53015
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Typical Application (continued)
8.2.1 Design Requirements
Table 2. TPS53015 Design Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Voltage range
8.0
12
22
V
Maximum input current
VIN = 12 V, IOUT = 8 A
0.9
A
No load input current
VIN = 12 V, IOUT = 0 A
0.6
mA
OUTPUT CHARACTERISTICS
Output voltage
1.05
Output voltage regulation
Setpoint accuracy
(VIN = 12 V, IOUT = 8 A)
-2%
Line regulation
(VIN = 8.0 V – 22 V, IOUT = 8 A)
1%
Load regulation
(VIN = 12 V, IOUT = 0 A – 8 A)
Output voltage ripple
1.5%
VIN = 12 V, IOUT = 8 A
Output load current
20
0
Overcurrent limit
VIN = 12 V
V
2%
mVpp
8.0
A
11
SYSTEMS CHARACTERISTICS
Switching frequency
500
Peak efficiency
VIN = 12 V, IOUT = 3.2 A
86.5%
Full load efficiency
VIN = 12 V, IOUT = 8.0 A
81.4%
Operating temperature
25
kHz
ºC
8.2.2 Detailed Design Procedure
8.2.2.1 Determine the Inductance Value
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve signal-to-noise ratio and contribute to stable
operation. Use Equation 3 to calculate te value for LOUT.
VIN(MAX) -VOUT
V
L OUT =
× OUT
IL(RIPPLE) ×fSW VIN(MAX)
(3)
The inductor current ratings must support both the RMS (thermal) current and the peak (saturation) current. The
RMS and peak inductor current can be estimated as shown in Equation 4.
VIN(MAX) -VOUT
V
IL(RIPPLE) =
× OUT
LOUT ×fSW
VIN(MAX)
(4)
V
IL(PEAK) = TRIP +IL(RIPPLE)
RDS(ON)
2
IL(RMS) = IOUT + 1 ×IL(RIPPLE)
12
(5)
2
(6)
NOTE
Equation 6 serves as a general reference. To further improve transient response, the
output inductance could be reduced further but must be considered along with the
selection of the output capacitor.
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8.2.2.2 Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Ceramic output capacitors with X5R dielectric or better are recommended.
IL(RIPPLE)
1
COUT =
×
8×VOUT(RIPPLE) fSW
(7)
COUT =
ΔILOAD2
×L OUT
2×VOUT ×ΔVOS
where
•
ΔVOS is the allowable amount of overshoot voltage in load transition
(8)
2
COUT =
ΔILOAD
×L OUT
2×K×ΔVUS
where
•
ΔVUS is the allowable amount of undershoot voltage in load transition
(9)
æ
ö
tON
÷
K = (VIN - VOUT )´ ç
ç tON - tOFF(min ) ÷
è
ø
where
•
tOFF(min) is the minimum off time
(10)
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and
Equation 9. The minimum recommended output capacitance is 44 μF.
8.2.2.3 Input Capacitor
The TPS53015 device requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating must be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor
The TPS53015 device requires a bootstrap capacitor from SW to VBST to provide the floating supply for the
high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The capacitor voltage rating
must be greater than 10 V.
8.2.2.5 VREG5 Capacitor
The TPS53015 device requires that the VREG5 regulator is bypassed. A minimum 4.7-μF high-quality ceramic
capacitor must be connected between the VREG5 and PGND for proper operation. The capacitor voltage rating
should be greater than 10 V.
8.2.2.6 Choose Output Voltage Resistors
The output voltage is set with a resistor divider from output voltage node to the VFB pin. It is recommended to
use 1% tolerance or better resistors. Select an R2 value between 10 kΩ and 100 kΩ and use Equation 11 to
calculate R1.
æV
ö
R1 = ç OUT -1÷ ×R2
è VVFB ø
(11)
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8.2.3 Application Curves
1.1
100
VOUT - Output Voltage - V
90
Efficiency - %
80
70
60
50
40
VIN = 8 V
30
20
VIN = 12 V
10
VIN = 22 V
1.08
1.06
VIN = 8 V
1.04
VIN = 12 V
1.02
VIN = 22 V
0
0.001
0.010
0.100
1.000
10.000
1
0.001
ILOAD - Load Current - A
0.010
0.100
1.000
10.000
ILOAD - Load Current - A
Figure 20. Load Regulation
Figure 19. Efficiency
NOTE
For more performance curves, see the PWR126 EVM user guide. (SLUU944)
9 Power Supply Recommendations
The TPS53015 device operates using an input voltage supply range from 4.5 V to 28 V. This input supply must
be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme
10 Layout
10.1 Layout Guidelines
Considerations these design guidelines before beginning the application layout process.
• Design an input switching current loop as small as possible.
• Place the input capacitor close to the top switching FET.
• Design the output switching current loop as small as possible.
• The SW node must be physically small and as short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions.
• Bring Kelvin connections from the output to the feedback pin (VFB) of the device.
• Place analog and non-switching components far away from switching components.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.
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10.2 Layout Example
Controller
VIN
HS FET
SW
GND
L
VOUT
LS FET
GND
Figure 21. TPS53015 Layout
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11 Device and Documentation Support
11.1 Trademarks
D-CAP2, Eco-Mode, Eco-mode are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS53015DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
53015
Samples
TPS53015DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
-40 to 85
53015
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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