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TPS53114
SLVS887C – APRIL 2009 – REVISED AUGUST 2014
TPS53114 Single Synchronous Step-down Controller for Low Voltage Power Rails
1 Features
3 Description
•
The TPS53114 is a single, adaptive on-time DCAP2™ mode synchronous buck controller. The
TPS53114 enables system designers to complete the
suite of various end equipment's power bus
regulators with cost effective low external component
count and low standby current solution. The main
control loop for the TPS53114 uses the D-CAP2™
mode control which provides a very fast transient
response with no external components. The
TPS53114 also has a circuit that enables the device
to adapt to both low equivalent series resistance
(ESR) output capacitors such as POSCAP or SPCAP and ultra-low ESR ceramic capacitors. The
device provides convenient and efficient operation
with input voltages from 4.5 V to 24 V and output
voltage from 0.76 V to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Control
– Fast Transient Response
– No External Parts Required For Loop
Compensation
– Compatible with Ceramic Output Capacitors
High Initial Reference Accuracy (±1%)
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(on) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost Diode
Adjustable Soft Start
Pre-Biased Soft Start
Selectable Switching Frequency
350 kHz / 700 kHz
Cycle-By-Cycle Over Current Limiting Control
Thermally Compensated OCP by 4000 ppm/°C at
ITRIP
2 Applications
•
Point-of-Load Regulation in Low Power Systems
for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set Top Box (STB)
– DVD Player / Recorder
– Gaming Consoles
The TPS53114 is available in the 16-pin TSSOP and
HTSSOP packages, and is specified from –40°C to
85°C ambient temperature range.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS53114
TSSOP (16)
5.00 mm x 4.40 mm
TPS53114
HTSSOP 916)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
VIN
VIN
R1
1
VO
2
VFB
VBST
16
R2
SGND
Q1
10uFx2
DRVH 15
3
SS
4
GND
SGND
5
CER
6
FSEL
SW 14
DRVL
THERMAL
PAD
L1
R2
SGND
VO
VBST
2
VFB
DRVH 15
3
SS
4
GND
SGND
EN
VREG5
8
SGND
1uF
V5FILT
VIN
DRVL
CER
PGND
6
FSEL
10
L1
Q2
13
C1
PGND 12
TRIP
11
R3
C5
10uFx2
(TSSOP16)
R3
7
SW 14
11
C6
Q1
TPS53114PW
SGND
5
TRIP
C3
C2
0.1uF
VO1
C1
PGND 12
16
C7
Q2
13
1
R1
VO1
(TSSOP16)
C7
SGND
C3
C2
0.1uF
TPS53114PWP
4.7uF
7
VIN
9
EN
VREG5
C5
C6
C4
1uF
4.7uF
VIN
8
SGND
PGND
10
V5FILT
VIN
9
C4
PGND
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53114
SLVS887C – APRIL 2009 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 350-kHz Operation Application .............................. 12
9.3 700 kHz Operation Application ............................... 16
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 20
12.1 Trademarks ........................................................... 20
12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2010) to Revision C
Page
•
Changed the datasheet to the new TI standard format.......................................................................................................... 1
•
Added Thermal PWP information .......................................................................................................................................... 5
•
Changed from 4.8 V to 4.6 V. ................................................................................................................................................ 5
•
Changed from 8 to 12 Ω. ....................................................................................................................................................... 5
•
Added Figures 8 and 9 .......................................................................................................................................................... 8
•
Added "The TPS53114 enables system designers to complete the suite of various end equipment power bus
regulators with cost effective, low external component count and low standby current solution." ........................................ 9
•
Changed Equation 1............................................................................................................................................................. 11
Changes from Revision A (August 2009) to Revision B
Page
•
Changed From: IOCL + To: IOCL - .......................................................................................................................................... 14
•
Added minus VOCLoff .............................................................................................................................................................. 14
2
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TPS53114
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SLVS887C – APRIL 2009 – REVISED AUGUST 2014
6 Pin Configurations and Functions
16-Pin TSSOP
PW Package
(Top View)
16-Pin HTSSOP
PWP Package
(Top View)
1
16
VBST
VFB
SS
2
15
DRVH
DRVH
14
SW
14
SW
GND
4
13
DRVL
13
DRVL
12
PGND
PGND
CER
FSEL
5
12
11
TRIP
11
TRIP
EN
7
10
VREG5
7
10
VREG5
V5FILT
8
9
8
9
16
VBST
VFB
SS
2
15
GND
4
CER
FSEL
5
EN
V5FILT
TPS 531 14
1
3
6
TPS 531 14
VO
VO
3
6
VIN
VIN
Pin Functions
PIN
NAME
NUMBER
VBST
16
EN
SS
I/O
DESCRIPTION
I
Supply input for high-side NFET driver. Bypass to SW with a high-quality 0.1-μF ceramic capacitor. An
external schottky diode can be added from VREG5 if forward drop is critical to drive the high-side FET.
7
I
Enable. Pull High to enable SMPS.
3
O
Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time.
VO
1
I
Output voltage input for on-time adjustment and output discharge. Connect directory to the output voltage.
VFB
2
I
D-CAP2 feedback input. Connect to output voltage with resistor divider.
GND
4
I
Signal ground pin. Connect to PGND and system ground at a single point.
DRVH
15
O
High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and
VBST(ON).
SW
14
I/O
Switch node connections for both the high-side driver and over current comparator.
DRVL
13
O
Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF)
and VREG5(ON).
PGND
12
TRIP
11
I
over current threshold programming pin. Connect to GND with a resister to set threshold for low-side RDS(on)
current limit.
VIN
9
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-quality 0.1-μF ceramic capacitor.
V5FILT
8
I
5-V supply input for the control circuitry except the MOSFET drivers. Bypass to GND with a minimum highquality 1.0-μF ceramic capacitor. V5FILT is connected to VREG5 via internal 10-Ω resistor.
VREG5
10
O
CER
5
I
Output capacitor select pin. Connect to GND for ceramic output capacitors. Connect to V5FILT for
conductive polymer electrolyte type output capacitors (SP-CAP, POS-CAP, PXE).
FSEL
6
I
Switching frequency selection pin. Connect to GND for low switching frequency or connect to V5FILT for
high switching frequency.
I/O
Power ground connection for both the low-side driver and over current comparator. Connect PGND and
GND strongly together near the IC.
Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum high-quality
4.7-μF ceramic capacitor. VREG5 is connected to V5FILT via internal 10-Ω resistor.
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TPS53114
SLVS887C – APRIL 2009 – REVISED AUGUST 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage range
(1)
MIN
MAX
VIN, EN
–0.3
26
VBST
–0.3
32
VBST - SW
–0.3
6
V5FILT, VFB, TRIP, VO, FSEL, CER
–0.3
6
–1
32
DRVH
DRVH - SW
Output voltage range
–0.3
6
–2
26
SW
DRVL, VREG5, SS
–0.3
6
PGND
–0.3
0.3
UNIT
V
V
TA
Operating ambient temperature range
–40
85
°C
TJ
Junction temperature range
–40
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–55
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
-2000
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
-500
500
Storage temperature
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply input voltage
Input voltage
Output voltage
MIN
MAX
VIN
4.5
24
V5FILT
4.5
5.5
VBST
–0.1
30
VBST - SW
–0.1
5.5
VFB, VO, FSEL, CER
–0.1
5.5
TRIP
–0.1
0.3
EN
–0.1
24
DRVH
–0.1
30
VBST - SW
–0.1
5.5
SW
1.8
24
DRVL, VREG5, SS
–0.1
5.5
PGND
–0.1
0.1
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
4
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7.4 Thermal Information
THERMAL METRIC (1)
TPS53114
PWP (16 PINS)
PW (16 PINS)
RθJA
Junction-to-ambient thermal resistance
51.2
109.6
RθJC(top)
Junction-to-case (top) thermal resistance
33.4
31.2
RθJB
Junction-to-board thermal resistance
28.3
54.7
ψJT
Junction-to-top characterization parameter
1.4
0.9
ψJB
Junction-to-board characterization parameter
28.1
54.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.9
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
350
600
μA
28
60
μA
SUPPLY CURRENT
IIN
VIN supply current
VIN current, TA = 25°C, VREG5 tied to
V5FLT, EN = 5V, VFB = 0.8V, SW = 0.5V
IVINSDN
VIN shutdown current
VIN current, TA = 25°C, No Load , EN = 0V,
VREG5 = ON
VFB VOLTAGE and DISCHARGE RESISTANCE
VBG
Bandgap Initial regulation
accuracy
VVFBTHL
VFB threshold voltage
VVFBTHH
VFB threshold voltage
IVFB
VFB input current
VFB = 0.8V, TA = 25°C
RDischg
Vo discharge resistance
EN = 0V, VO = 0.5V, TA = 25°C
TA = 25°C
–1.0%
TA = 25°C , FSEL = 0 V, CER = V5FILT
755
TA = –40°C to 85°C, FSEL = 0V, CER =
V5FILT
752
TA = 25°C , FSEL = CER = V5FILT
748
TA = –40°C to 85°C, FSEL = CER = V5FILT
745
–100
1.0%
765
775
778
758
768
771
mV
mV
–10
100
nA
40
80
Ω
5.0
5.2
V
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA=25°C, 5.5V < VIN < 24V, 0 < IVREG5 <
10mA
VLN5
Line regulation
5.5V < VIN < 24V, IVREG5 = 10mA
20
mV
VLD5
Load regulation
1mA < IVREG5 < 10mA
40
mV
IVREG5
Output current
VIN = 5.5V, VVREG5 = 4.0V, TA = 25°C
4.6
170
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
Source, IDRVH = –100mA
5.5
11
Sink, IDRVH = 100mA
2.5
5
Source, IDRVL = –100mA
4
12
Sink, IDRVL = 100mA
2
4
0.8
0.9
V
0.1
1
µA
2.6
µA
Ω
Ω
INTERNAL BST DIODE
VFBST
Forward voltage
VVREG5-VBST, IF = 10mA, TA = 25°C
IVBSTLK
VBST leakage current
VBST = 29V, SW = 24V, TA = 25°C
0.7
SOFT START
Issc
SS charge current
VSS = 0V , SOURCE CURRENT
1.4
2.0
Issd
SS discharge current
VSS = 0.5V , SINK CURRRENT
100
150
V5FILT rising
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
µA
UVLO
VUV5VFILT
V5FILT UVLO threshold
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD
VENH
EN H-level threshold
voltage
EN
VENL
EN L-level threshold
voltage
EN
2.0
V
0.3
V
11.5
µA
CURRENT SENSE
ITRIP
TRIP source current
VTRIP = 0.1V, TA = 25°C
TCITRIP
ITRIP temperature
coefficient
on the basis of 25°C
VOCLoff
OCP compensation offset
Current limit threshold
setting range
VRtrip
8.5
10
4000
ppm/°C
(VTRIP-GND-VPGND-SW) voltage,
VTRIP-GND = 60mV, TA = 25°C
–10
(VTRIP-GND-VPGND-SW) voltage,
VTRIP-GND = 60mV
–15
15
30
200
VTRIP-GND voltage
0
10
mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
VUVP
Output UVP trip threshold
OVP detect
110%
115%
120%
UVP detect
65%
70%
75%
Hysteresis (recovery