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TPS53119
SLUSD61A – DECEMBER 2017 – REVISED MARCH 2019
TPS53119 Wide input voltage, Eco-Mode, synchronous step-down controller
1 Features
2 Applications
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1
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Conversion input voltage range: 3 V to 26 V
VDD input voltage range: 4.5 V to 25 V
Output voltage range: 0.6 V to 5.5 V
Built-In 0.6-V (±0.8%) reference
Built-In LDO linear voltage regulator
Auto-skip Eco-Mode™ for light-load efficiency
D-CAP™ mode with 100-ns load-step response
Adaptive ON-time control architecture with 8
selectable frequency settings
4700-ppm/°C RDS(on) current sensing
0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable
internal voltage servo soft start
Pre-charged start-up capability
Built-in output discharge
Open-drain power-good output
Integrated boost switch
Built-In OVP/UVP/OCP
Thermal shutdown (non-latch)
3-mm × 3-mm 16-Pin VQFN (RGT) package
Create a custom design using the TPS53119 with
the WEBENCH® Power Designer
Storage
Servers
Multi-function printers
Embedded computing
3 Description
The TPS53119 device is a small-sized single buck
controller with adaptive ON-time D-CAP mode
control. The device is designed for low output
voltage, high current, PC system power rail and
similar point-of-load (POL) power supplies in digital
consumer products. The small package and minimal
pin count save space on the PCB, while the
dedicated EN pin and pre-set frequency selections
simplify the power supply design. The skip mode at
light load conditions, strong gate drivers, and low-side
FET RDS(on) current sensing supports low loss and
high efficiency over a broad load range. The
conversion input voltage (high-side FET drain
voltage) range is between 4.5 V and 25 V, and the
output voltage range is between 0.6 V and 5.5 V. The
TPS53119 is available in a 16-pin VQFN package
specified from –20°C to +85°C.
Device Information(1)
PART NUMBER
TPS53119
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V IN
VREG
VIN
16
EN
1
TRIP
2
EN
3
VFB
4
RF
15
14
CSD86350
SW
13
PGOOD NC VBST DRVH
SW 12
VIN
SW
DRVL 11
TG
SW
TGR
BG
TPS53119
VDRV 10
VREG
Pad MODE VDD
5
6
V OUT
GND PGND
7
9
PGND
8
VDD
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53119
SLUSD61A – DECEMBER 2017 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2017) to Revision A
Page
•
Added links for WEBENCH .................................................................................................................................................... 1
•
Added "Repetitive spikes up to 9 V can be tolerated for up to 50 ns." to Note 2 of Absolute Maximum Ratings. ................ 4
2
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5 Pin Configuration and Functions
TRIP
1
EN
2
PGOOD
N/C
VBST
DRVH
RGT Package
16-Pin VQFN With Exposed Thermal Pad
Top View
16
15
14
13
12
SW
11
DVRL
TPS53119
RF
4
9
VREG
5
6
7
8
PGND
VDRV
GND
10
VDD
3
MODE
VFB
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
DRVH
13
O
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is
defined by the voltage across VBST to SW node bootstrap flying capacitor.
DRVL
11
O
Synchronous MOSFET driver output. The PGND referenced driver. The gate drive voltage is defined by
VDRV voltage.
EN
2
I
Enable pin. Place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V.
GND
7
G
Ground pin. This is the ground of internal analog circuitry. Connect to GND plane at single point.
MODE
5
I
Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The softstart time is detected and stored into internal register during start-up.
NC
15
–
No connection.
PAD
–
–
Thermal pad. Use five vias to connect to GND plane.
PGOOD
16
O
Open-drain power-good flag. Provides 1-ms start-up delay after the VFB pin voltage falls within specified
limits. When VFB goes out specified limits PGOOD goes low after a 2-µs delay.
PGND
8
G
Power ground. Connect to GND plane.
RF
4
I
Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using
Table 2. The switching frequency is detected and stored during the start-up.
SW
12
P
Output of converted power. Connect this pin to the output inductor.
TRIP
1
I
OCL detection threshold setting pin —10 µA at room temp, 4700 ppm/°C current is sourced and set the
OCL trip voltage as follows: VOCL = VTRIP / 8 ( VTRIP ≤ 3 V, VOCL ≤ 375 mV)
VBST
14
P
Supply input for high-side FET gate driver (boost terminal). Connect a capacitor from this pin to SW
node. Internally connected to VREG through bootstrap MOSFET switch.
VDD
6
P
Controller power supply input. The input range is from 4.5 V to 25 V.
VDRV
10
I
Gate drive supply voltage input. Connect to VREG if using LDO output as gate-drive supply.
VFB
3
I
Output feedback input. Connect this pin to VOUT through a resistor divider.
VREG
9
O
6.2-V LDO output. This is the supply of internal analog circuitry and driver circuitry.
(1)
I=Input, O=Output, P=Power, G=Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
VBST
–0.3
35
VBST (2)
–0.3
7
VDD
–0.3
26
–2
28
DC
SW
Pulse < 20 ns, E = 5 µJ
–0.3
7
–2
35
DRVH (2)
–0.3
7
DRVL, VREG
–0.5
7
PGOOD
–0.3
DRVH
Storage temperature, Tstg
(2)
V
7
Junction temperature, TJ
(1)
V
–7
VDRV, EN, TRIP, VFB, RF, MODE
Output voltage
UNIT
–55
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the SW terminal. Repetitive spikes up to 9 V can be tolerated for up to 50 ns.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
MAX
VBST
–0.1
34.5
VDD
4.5
25
SW
–1
28
–0.1
6.5
VBST
(1)
EN, TRIP, VFB, RF, VDRV, MODE
–0.1
6.5
–1
34.5
DRVH (1)
–0.1
6.5
DRVL, VREG
–0.3
6.5
PGOOD
–0.1
6.5
–20
85
DRVH
Output voltage
Operating free-air temperature, TA
(1)
4
UNIT
V
V
°C
Voltage values are with respect to the SW terminal.
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6.4 Thermal Information
TPS53119
THERMAL METRIC (1)
RGT (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
51.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
85.4
°C/W
RθJB
Junction-to-board thermal resistance
20.1
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
19.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VDD = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
420
590
µA
10
µA
SUPPLY CURRENT
IVDD
VDD supply current
VDD current, TA = 25°C, no load, VEN = 5 V,
VVFB = 0.630 V
IVDDSDN
VDD shutdown current
VDD current, TA = 25°C, no load, VEN = 0 V
INTERNAL REFERENCE VOLTAGE
VVFB
VFB regulation voltage
VFB voltage, CCM condition (1)
TA = 25°C
VVFB
VFB regulation voltage
0°C ≤ TA ≤ 85°C
–20°C ≤ TA ≤ 85°C
IVFB
VFB input current
600
mV
597
600
603
595.2
600
604.8
592
600
608
0.002
0.2
VVFB = 0.63 V, TA = 25°C
mV
µA
OUTPUT DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
tDEAD
Dead time
Source, IDRVH = –50 mA
1.5
3
Sink, IDRVH = 50 mA
0.7
1.8
Source, IDRVL = –50 mA
Sink, IDRVL = 50 mA
1
2.2
0.5
1.2
DRVH-off to DRVL-on
7
17
30
DRVL-off to DRVH-on
10
22
35
5.76
6.2
6.67
Ω
Ω
ns
LDO OUTPUT
VVREG
LDO output voltage
0 mA ≤ IVREG ≤ 50 mA
IVREG
LDO output current (1)
Maximum current allowed from LDO
VDO
LDO dropout voltage
VVDD = 4.5 V, IVREG = 50 mA
V
50
mA
364
mV
BOOT STRAP SWITCH
VFBST
Forward voltage
VVREG-VBST, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakagecurrent
VVBST = 23 V, VSW = 17 V, TA = 25°C
0.1
0.2
V
0.01
1.5
µA
260
400
ns
DUTY AND FREQUENCY CONTROL
tOFF(min)
tON(min)
Minimum off-time
TA = 25°C
Minimum ON-time
VIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to VREG,
TA = 25°C (1)
150
35
0 V ≤ VOUT ≤ 95%, RMODE = 39 kΩ
0.7
0 V ≤ VOUT ≤ 95%, RMODE = 100kΩ
1.4
0 V ≤ VOUT ≤ 95%, RMODE = 200 kΩ
2.8
0 V ≤ VOUT ≤ 95%, RMODE = 470 kΩ
5.6
ns
SOFT START
tSS
(1)
Internal soft-start time
ms
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VDD = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
VTHPG
PG threshold
PG in from lower
92.5%
96%
98.5%
PG in from higher
108%
111%
114%
PG hysteresis
2.5%
5%
7.8%
RPG
PG transistor on-resistance
15
30
50
Ω
tPG(del)
PG delay after soft start
0.8
1
1.2
ms
LOGIC THRESHOLD AND SETTING CONDITIONS
EN voltage threshold enable
VEN
–20°C ≤ TA ≤ 85°C
1.8
0°C ≤ TA ≤ 85°C
1.7
V
EN voltage threshold disable
IEN
EN input current
fSW
Switching frequency
0.5
VEN = 5 V
1
RRF = 0 Ω to GND, TA = 25°C (2)
200
250
300
RRF = 187 kΩ to GND, TA = 25°C (2)
250
300
350
RRF = 619 kΩ to GND, TA = 25°C (2)
350
400
450
RRF = open, TA = 25°C (2)
450
500
550
RRF = 866 kΩ to VREG, TA = 25°C (2)
580
650
720
RRF = 309 kΩ to VREG, TA = 25°C (2)
670
750
820
RRF = 124 kΩ to VREG, TA = 25°C (2)
770
850
930
RRF = 0 Ω to VREG, TA = 25°C (2)
880
970
1070
VEN = 0 V, VSW = 0.5 V
5
13
9
µA
kHz
VO DISCHARGE
IDischg
VO discharge current
mA
PROTECTION: CURRENT SENSE
ITRIP
TRIP source current
VTRIP = 1 V, TA = 25°C
TCITRIP
TRIP current temp. coef.
TA = 25°C (1)
VTRIP
Current limit threshold setting
range
VTRIP-GND voltage
0.2
VTRIP = 3 V
355
375
395
VOCL
Current limit threshold
VTRIP = 1.6 V
185
200
215
VTRIP = 0.2 V
17
25
33
VTRIP = 3 V
–406
–375
–355
VTRIP = 1.6 V
–215
–200
–185
VTRIP = 0.2 V
–33
–25
–17
VOCLN
VAZC(adj)
Negative current limit
threshold
Auto zero cross adjustable
range
10
11
4700
Positive
3
Negative
µA
ppm/°C
3
15
–15
–3
120%
125%
V
mV
mV
mV
PROTECTION: UVP AND OVP
VOVP
OVP trip threshold voltage
OVP detect
tOVP(del)
OVP propagation delay time
VFB delay with 50-mV overdrive
115%
VUVP
Output UVP trip threshold
voltage
UVP detect
tUVP(del)
Output UVP propagation
delay time
tUVP(en)
1
µs
65%
70%
75%
0.8
1
1.2
ms
Output UVP enable delay time from EN to UVP workable, RMODE = 39 kΩ
2
2.55
3
ms
Wake up
4
4.18
4.5
UVLO
VUVVREG
VREG UVLO threshold
Hysteresis
0.25
Shutdown temperature (1)
145
V
THERMAL SHUTDOWN
TSDN
(2)
6
Thermal shutdown threshold
Hysteresis (1)
10
°C
Not production tested. Test conditions are VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A and using the application circuit shown in Figure 18
and Figure 22.
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6.6 Typical Characteristics
5.0
700
4.5
Supply Shutdown Current (µA)
Supply Current (µA)
600
500
400
300
200
100
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
0.0
−50
150
140
140
120
120
100
80
60
40
20
−25
0
25
50
75
Temperature (°C)
100
125
100
150
80
60
40
OVP
UVP
Figure 3. OVP/UVP Threshold vs Temperature
−25
0
25
50
75
Temperature (°C)
100
125
150
Figure 4. TRIP Pin Current vs Temperature
Frequency (kHz)
1000
100
fSET = 300 kHz
VIN = 12 V
VOUT = 1.1 V
10
100
fSET = 500 kHz
VIN = 12 V
VOUT = 1.1 V
10
FCC Mode
Skip Mode
1
0.01
125
100
0
−50
150
1000
Frequency (kHz)
25
50
75
Temperature (°C)
20
OVP
UVP
0
−50
0
Figure 2. VDD Shutdown Current vs Temperature
OVP/UVP Threshold (%)
OVP/UVP Threshold (%)
Figure 1. VDD Supply Current vs Temperature
−25
0.1
1
Output Current (A)
10
100
Figure 5. Switching Frequency vs Output Current
FCC Mode
Skip Mode
1
0.01
0.1
1
Output Current (A)
10
100
Figure 6. Switching Frequency vs Output Current
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Typical Characteristics (continued)
1000
Frequency (kHz)
Frequency (kHz)
1000
100
fSET =750 kHz
VIN = 12 V
VOUT = 1.1 V
10
100
fSET =1 MHz
VIN = 12 V
VOUT = 1.1 V
10
FCC Mode
Skip Mode
1
0.01
0.1
1
Output Current (A)
10
FCC Mode
Skip Mode
1
0.01
100
Figure 7. Switching Frequency vs Output Current
100
fSET = 500 kHz
VIN = 12 V
VOUT = 1.1 V
1.115
1000
1.110
800
fSET = 750 kHz
600
fSET = 500 kHz
400
fSET = 300 kHz
Output Voltage (V)
Switching Frequency (kHz)
10
1.120
fSET = 1 MHz
1.105
1.100
1.095
1.090
200
0
IOUT =10 A
VIN = 12 V
0
1
2
3
4
Output Voltage (V)
5
1.085
1.080
6
Figure 9. Switching Frequency vs Output Voltage
100
1.108
90
1.106
80
1.104
70
1.102
1.100
1.098
1.096
0
5
10
15
Output Current (A)
1.092
FCC Mode, No Load
Skip Mode, No Load
All Modes, IOUT = 20 A
fSW = 500 kHz
5
6
7
8
9
10
11
Input Voltage (V)
12
13
14
15
20
25
60
50
VIN = 12 V
VOUT = 1.1 V
40
30
1.094
1.090
FCC Mode
Skip Mode
Figure 10. Output Voltage vs Output Current
1.110
Efficiency (%)
Output Voltage (V)
1
Output Current (A)
Figure 8. Switching Frequency vs Output Current
1200
Skip Mode, fSW = 500 kHz
FCC Mode, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCC Mode, fSW = 300 kHz
20
10
0
0.01
Figure 11. Output Voltage vs Input Voltage
8
0.1
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0.1
1
Output Current (A)
10
100
Figure 12. Efficiency vs Output Current
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Typical Characteristics (continued)
Figure 13. Start-Up Waveform
Figure 14. Prebias Start-Up Waveform
Figure 15. Turnoff Waveform
Figure 16. Load Transient Response
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7 Detailed Description
7.1 Overview
The TPS53119 is a high-efficiency, single-channel, synchronous buck regulator controller suitable for low output
voltage point-of-load applications in computing and similar digital consumer applications. The device features
proprietary D-CAP mode control combined with an adaptive ON-time architecture. This combination is ideal for
building modern low duty ratio, ultra-fast load step response DC–DC converters. The output voltage ranges from
0.6 V to 5.5 V. The conversion input voltage range is from 3 V up to 26 V. The D-CAP mode uses the ESR of the
output capacitors to sense the device current. One advantage of this control scheme is that it does not require an
external phase compensation network. This allows a simple design with a low external component count. Eight
preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG.
Adaptive ON-time control tracks the preset switching frequency over a wide input and output voltage range while
allowing the switching frequency to increase at the step-up of the load.
The TPS53119 has a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms as shown in Table 1. The strong gate drivers allow low RDS(on) FETs for high-current applications.
When the device starts (either by EN or VDD UVLO), the TPS53119 sends out a current that detects the
resistance connected to the MODE pin to determine the soft-start time. After that (and before VOUT starts to ramp
up) the MODE pin becomes a high-impedance input to determine skip mode or FCCM mode operation. When
the voltage on the MODE pin is higher than 1.3 V, the converter enters into FCCM mode. If the voltage on
MODE pin is less than 1.3 V, then the converter operates in skip mode.
TI recommends connection of the MODE pin to the PGOOD pin if FCCM mode is desired. In this configuration,
the MODE pin is connected to the GND potential through a resistor when the device is detecting the soft-start
time, thus correct soft-start time is used. The device starts up in skip mode and only after the PGOOD pin goes
high does the device enter into FCCM mode. When the PGOOD pin goes high there is a transition between skip
mode and FCCM. A minimum off-time of 60 ns on DRVL is provided to avoid a voltage spike on the DRVL pin
caused by parasitic inductance of the driver loop and gate capacitance of the low-side MOSFET.
For proper operation, the MODE pin must not be connected directly to a voltage source.
10
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7.2 Functional Block Diagram
0.6 V –30%
+
UV
+
OV
0.6 V +10/15%
Delay
+
0.6 V +20%
0.6 V –5/10%
Enable/SS Control
2
VFB
3
PWM
12 SW
+
XCON
0.6 V
7
10 mA
TRIP
13 DRVH
+
+
Ramp Comp
GND
14 VBST
Control Logic
+
EN
16 PGOOD
+
1
+
tON
OneShot
OCP
x(-1/8)
FCCM
x(1/8)
+
ZC
Auto-skip
10 VDRV
11 DRVL
Auto-skip/FCCM
8
RF
Frequency
Setting
Detector
4
PGND
EN
LDO Linear
Regulator
TPS53119
5
MODE
9
6
VREG
VDD
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Enable and Soft-Start
When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its startup sequence. The internal LDO regulator starts immediately and regulates to 6.2 V at the VREG pin. The
controller then uses the first 250 µs to calibrate the switching frequency setting resistance attached to the RF pin
and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In
the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the
MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
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Table 1. Soft-Start and MODE
MODE
SELECTION
Auto skip
Forced CCM (1)
(1)
ACTION
SOFT-START
TIME (ms)
RMODE (kΩ)
0.7
39
1.4
100
2.8
200
5.6
475
Pulldown to GND
Connect to PGOOD
0.7
39
1.4
100
2.8
200
5.6
475
Device goes into forced CCM after PGOOD becomes high.
When the EN voltage is higher than 5.5 V, a 1-kΩ series resistor is needed for the EN pin.
7.3.2 Adaptive ON-Time D-CAP Control and Frequency Selection
The TPS53119 does not have a dedicated oscillator that determines switching frequency. However, the device
operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the ON-time oneshot timer. The adaptive ON-time control adjusts the ON-time to be inversely proportional to the input voltage
and proportional to the output voltage (tON ∝ VOUT/VIN).
This makes the switching frequency fairly constant in steady-state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 2. Leaving the resistance open sets the
switching frequency to 500 kHz.
Table 2. Resistor and Switching Frequency
RESISTOR (RRF) CONNECTIONS
SWITCHING
FREQUENCY (kHz)
0 Ω to GND
250
187 kΩ to GND
300
619 kΩ to GND
400
Open
500
866 kΩ to VREG
650
309 kΩ to VREG
750
124 kΩ to VREG
850
0 Ω to VREG
970
The OFF-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts a set signal to terminate the OFF-time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time
is extended until the current level falls below the threshold.
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7.3.3 Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP mode can be simplified as shown in Figure 17.
VIN
TPS53119
Switching Modulator
DRVH
R1
VFB
PWM
3
+
R2
+
0.6 V
Control
Logic
and
Driver
L
13
DRVL
IIND
11
VOUT
IOUT
IC
ESR
RLOAD
Voltage Divider
VC
C OUT
Output
Capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
1
H (s ) =
s ´ ESR ´ COUT
(1)
For the loop stability, the 0-dB frequency, f0, defined below must be lower than ¼ of the switching frequency.
f
1
£ SW
f0 =
2p ´ ESR ´ COUT
4
(2)
According to Equation 2, the loop stability of D-CAP mode modulator is mainly determined by the capacitor
chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance on the order of
several 100 µF and ESR in range of 10 mΩ. These yields an f0 on the order of 100 kHz or less and a more stable
loop. However, ceramic capacitors have an f0 at more than 700 kHz, and require special care when used with
this modulator. An application circuit for ceramic capacitor is described in External Parts Selection With All
Ceramic Output Capacitors.
7.3.4 Ramp Signal
The TPS53119 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in
Small Signal Model, the feedback voltage is compared with the reference information to keep the output voltage
in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle
is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start
with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady-state.
During skip mode operation, when the switching frequency is lower than 70% of the nominal frequency (because
of longer OFF-time), the ramp signal exceeds 0 mV at the end of the OFF-time but is clamped at 3 mV to
minimize DC offset.
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7.3.5 Adaptive Zero Crossing
The TPS53119 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too
early detection. As a result, better light load efficiency is delivered.
7.3.6 Output Discharge Control
When EN becomes low, the TPS53119 discharges output capacitor using internal MOSFET connected between
the SW pin and the PGND pin while the high-side and low-side MOSFETs are maintained in the OFF state. The
typical discharge resistance is 40 Ω. The soft discharge occurs only as EN becomes low. After VREG becomes
low, the internal MOSFET turns off, and the discharge function becomes inactive.
7.3.7 Low-Side Driver
The low-side driver is designed to drive high-current low-RDS(on) N-channel MOSFETs. The drive capability is
represented by its internal resistance, which is 1 Ω for VDRV to DRVL and 0.5 Ω for DRVL to GND. A dead time
to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and
low-side MOSFET off to high-side MOSFET on. The bias voltage VDRV can be delivered from 6.2-V VREG
supply or from external power source from 4.5 V to 6.5 V. The instantaneous drive current is supplied by an input
capacitor connected between the VDRV and PGND pins.
The average low-side gate drive current is calculated in Equation 3.
IGL = CGL ´ VVDRV ´ fSW
(3)
When VDRV is supplied by external voltage source, the device continues to be supplied by the VREG pin. There
is no internal connection from VDRV to VREG.
7.3.8 High-Side Driver
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFETs. When configured as a
floating driver, the bias voltage is delivered from the VDRV pin supply. The average drive current is calculated
using Equation 4.
IGH = CGH ´ VVDRV ´ fSW
(4)
The instantaneous drive current is supplied by the flying capacitor between VBST and SW pins. The drive
capability is represented by internal resistance, which is 1.5 Ω for VBST to DRVH and 0.7 Ω for DRVH to SW.
The driving power which needs to be dissipated from TPS53119 package.
PDRV = (IGL + IGH )´ VVDRV
(5)
7.3.9 Power Good
The TPS53119 has a power-good output that indicates high when switcher output is within the target. The powergood function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of the
target value, internal comparators detect power-good state and the power-good signal becomes high after a 1ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good signal
becomes low after two microsecond (2-µs) internal delay. The power-good output is an open-drain output and
must be pulled up externally.
In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic
before the TPS53119 is powered up, TI recommends that the PGOOD pin be pulled up to VREG (either directly
or through a resistor divider if a different pullup voltage is desired) because VREG remains low when the device
is powered off. The pullup resistance can be chosen from a standard resistor value between 1 kΩ and 100 kΩ.
14
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7.3.10 Current Sense and Overcurrent Protection
TPS53119 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller maintains the OFF state during the period in that the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost-effective solution, TPS53119 supports
temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip
voltage setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 µA typically at room
temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 6.
NOTE
The VTRIP is limited up to approximately 3 V internally.
VTRIP (mV ) = RTRIP (kW )´ ITRIP (mA )
(6)
The inductor current is monitored by the voltage between GND pin and SW pin so that SW pin should be
connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700-ppm/°C temperature slope to
compensate the temperature dependency of the RDS(on). The GND pin is used as the positive current-sensing
node. The GND pin should be connected to the proper current sensing device, (for example, the source terminal
of the low-side MOSFET.)
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 7.
IIND(ripple )
(VIN - VOUT )´ VOUT
VTRIP
VTRIP
1
IOCP =
+
=
+
´
2
2
´
L
´
f
VIN
SW
8 ´ RDS(on )
8 ´ RDS(on )
(
)
(
)
(7)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down. After a
hiccup delay (16 ms with 0.7-ms sort start), the controller restarts. If the overcurrent condition remains, the
procedure is repeated and the device enters hiccup mode.
During the CCM, the negative current limit (NCL) protects the external FET from carrying too much current. The
NCL detect threshold is set as the same absolute value as positive OCL but negative polarity.
NOTE
The threshold still represents the valley value of the inductor current.
7.3.11 Overvoltage and Undervoltage Protection
TPS53119 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. When the
feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an
internal UVP delay counter begins counting. After 1 ms, TPS53119 latches OFF both high-side and low-side
MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7-ms soft-start). This function is
enabled 1.5-ms after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The
output voltage decreases. If the output voltage reaches UV threshold, then both high-side MOSFET and low-side
MOSFET driver will be OFF and the device restarts after an hiccup delay. If the OV condition remains, both highside MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed.
7.3.12 UVLO Protection
The TPS53119 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than 3.95
V, the device shuts off. When the VREG voltage is higher than 4.2 V, the device restarts. This is non-latch
protection.
7.3.13 Thermal Shutdown
The TPS53119 uses temperature monitoring. If the temperature exceeds the threshold value (typically 145°C),
the device is shut off. This is non-latch protection.
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7.4 Device Functional Modes
7.4.1 Light Load Condition in Auto-Skip Operation
While the MODE pin is pulled low through RMODE, TPS53119 automatically reduces the switching frequency at
light load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The ON-time is
kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the
output capacitor with smaller load current to the level of the reference voltage. The transition point to the light
load operation IO(LL) (that is, the threshold between continuous and discontinuous conduction mode) can be
calculated as shown in Equation 8.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
where
•
fSW is the PWM switching frequency
(8)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IO(LL) given in Equation 8. For example, it is 60
kHz at IO(LL) / 5 if the frequency setting is 300 kHz.
7.4.2 Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load
range, which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS53119 device is a small-sized, single-buck controller with adaptive ON-time DCAP mode control.
8.2 Typical Applications
8.2.1 Typical Application With Power Block
R10
100 kW
R9
0W
VREG
R1
10 kW
VIN
PGOOD
R8
86.6 kW
1
16
15
14
13
PGOOD
NC
VBST
DRVH
TRIP
R2
10 kW
EN
3
VFB
4
RF
R4
187 kW
CSD86350
VIN
DRVL 11
2
VIN
SW
CIN
22 mF x 4
SW
SW 12
R11
1 kW
EN
C5
0.1 mF
TG
SW
TGR
BG
L1
0.44 mH
PA0513.441
VOUT
TPS53119
VDRV 10
VREG
MODE
VDD
5
6
R5
100 kW
PGOOD
PGND
9
COUT
POSCAP
330 mF x 2
GND PGND Pad
7
C4
4.7 mF
8
C3
1 mF
VDD
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Typical Application Circuit Diagram With Power Block
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Typical Applications (continued)
8.2.1.1 Design Requirements
This design uses the parameters listed in Table 3.
Table 3. Design Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
12
18
UNIT
INPUT CHARACTERISTICS
VIN
IMAX
Voltage range
Maximum input current
VIN = 5 V, IOUT = 25 A
No load input current
VIN = 12 V, IOUT = 0 A with auto-skip
mode
V
10
A
1
mA
OUTPUT CHARACTERISTICS
Output voltage
VOUT
Output voltage regulation
VRIPPLE
Output voltage ripple
ILOAD
Output load current
IOVER
Output overcurrent
tSS
Soft-start time
1.2
Line regulation, 5 V ≤ VIN ≤ 14 V with
FCCM
0.2%
Load regulation, VIN = 12 V, 0 A ≤ IOUT
≤ 25 A with FCCM
0.5%
VIN = 12 V, IOUT = 25 A with FCCM
V
10
0
mVPP
25
32
A
1
ms
500
kHz
SYSTEMS CHARACTERISTICS
fSW
η
TA
Switching frequency
Peak efficiency
VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A
91%
Full load efficiency
VIN = 12 V, VOUT = 1.2 V, IOUT = 8 A
91.5%
Operating temperature
25
°C
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS53119 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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8.2.1.2.2 External Components Selection
Selecting external components is a simple process using D-CAP mode.
1. Choose the Inductor
The inductance should be determined to give the ripple current of approximately ¼ to ½ of maximum output
current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps
stable operation.
L=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(9)
The inductor also requires a low DCR to achieve good efficiency. It also requires enough room above the
peak inductor current before saturation. The peak inductor current can be estimated in Equation 10.
IIND(peak ) =
)
(
VIN(max ) - VOUT ´ VOUT
VTRIP
1
+
´
8 ´ RDS(on ) L ´ fSW
VIN(max )
(10)
2. Choose the Output Capacitor
When organic semiconductor capacitors or specialty polymer capacitors are used, for loop stability,
capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 11 is a good starting point
to determine ESR.
V
´ 10mV ´ (1 - D) 10mV ´ L ´ fSW L ´ fSW
ESR = OUT
=
=
(W )
0.6 V ´ IIND(ripple )
0.6 V
60
where
•
•
D is the duty factor
the required output ripple slope is approximately 10 mV per tSW (switching period) in terms of VFB terminal
voltage
(11)
3. Determine the Value of R1 and R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 17. R1 is
connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is between 10 kΩ and 20 kΩ. Determine R1 using Equation 12.
æ IIND(ripple ) ´ ESR ö
÷ - 0.6
VOUT - ç
ç
÷
2
è
ø
R1 =
´ R2
0.6
(12)
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8.2.1.3 Application Curves
100.00%
1.30
1.28
90.00%
1.26
Effciency (%)
VOUT (V)
1.24
1.22
1.20
1.18
1.16
1.14
5
10
15
20
5.0Vin_1.2Vout_500kHz_25C
40.00%
0.01
25
IOUT (A)
60.00%
12.0Vin_1.2Vout_500kHz_25C
12.0Vin_1.2Vout_500kHz_25C
1.10
0
70.00%
50.00%
5.0Vin_1.2Vout_500kHz_25C
1.12
80.00%
0.10
1.00
IOUT (A)
C008
10.00
C009
Figure 20. Efficiency Performance
Figure 19. Load Regulation Performance
700.00
5.0Vin_1.2Vout_500kHz_25C
12.0Vin_1.2Vout_500kHz_25C
Frequency (KHz)
600.00
500.00
400.00
300.00
5
10
15
20
25
IOUT (A)
C010
Figure 21. Switching Frequency Performance
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8.2.2 Typical Application With Ceramic Output Capacitors
R1
10 kW
VIN
R10
100 kW
R9
0W
CIN
22 mF x 4
VREG
PGOOD
R8
20 kW
1
16
15
14
13
PGOOD
NC
VBST
DRVH
R2
10 kW
EN
3
VFB
4
RF
R4
187 kW
CSD86350
VIN
DRVL 11
2
VIN
SW
C2
1 nF
C1
0.1 mF
SW
SW 12
TRIP
R11
1 kW
EN
C5
0.1 mF
TG
SW
TGR
BG
R7
10 kW
L1
0.44 mH
PA0513.441
VOUT
TPS53119
VDRV 10
VREG
MODE
VDD
5
6
R5
100 kW
PGOOD
COUT
Ceramic
100 mF x 4
PGND
9
R12
0W
GND PGND Pad
7
8
C4
4.7 mF
C3
1 mF
VDD
Copyright © 2017, Texas Instruments Incorporated
Figure 22. Typical Application Circuit Diagram With Ceramic Output Capacitors
8.2.2.1 Design Requirements
This design uses the parameters listed in Table 4.
Table 4. Design Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
18
UNIT
INPUT CHARACTERISTICS
VIN
IMAX
Voltage range
5
Maximum input current
VIN = 5 V, IOUT = 8 A
No load input current
VIN = 12 V, IOUT = 0 A with auto-skip
mode
V
2.5
A
1
mA
OUTPUT CHARACTERISTICS
Output voltage
VOUT
Output voltage regulation
VRIPPLE
Output voltage ripple
ILOAD
Output load current
IOVER
Output overcurrent
tSS
Soft-start time
1.2
Line regulation, 5 V ≤ VIN ≤ 14 V with
FCCM
0.2%
Load regulation, VIN = 12 V, 0 A ≤ IOUT
≤ 8 A with FCCM
0.5%
VIN = 12 V, IOUT = 8 A with FCCM
V
10
0
mVPP
8
A
25
1
ms
SYSTEMS CHARACTERISTICS
fSW
η
TA
Switching frequency
500
Peak efficiency
VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A
91%
Full load efficiency
VIN = 12 V, VOUT = 1.2 V, IOUT = 8 A
91.5%
Operating temperature
1000
kHz
25
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8.2.2.2 Detailed Design Procedure
8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
When a ceramic output capacitor is used, the stability criteria in Equation 2 cannot be satisfied. The ripple
injection approach as shown in Figure 22 is implemented to increase the ripple on the VFB pin and make the
system stable. C2 can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.
The increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the
VFB pin has two components, one coupled from SW node and the other coupled from VOUT and they can be
calculated using Equation 13 and Equation 14.
VINJ(SW ) =
(VIN - VOUT ) ´
R7 ´ C1
D
fSW
VINJ(OUT ) = ESR ´ IIND(ripple ) +
(13)
IIND(ripple )
8 ´ COUT ´ fSW
(14)
The DC value of VFB can be calculated by Equation 15.
VFB = 0.6 +
(V
INJ(SW ) + VINJ(OUT )
)
2
(15)
And the resistor divider value can be determined by Equation 16.
R1 =
(VOUT - VFB ) ´ R2
VFB
(16)
8.2.2.3 Application Curves
1.40
100.00%
1.35
90.00%
80.00%
70.00%
Efficiency (%)
VOUT (V)
1.30
1.25
1.20
1.15
60.00%
50.00%
40.00%
30.00%
1.10
20.00%
5.0Vin_1.2Vout_500kHz_25C
1.05
1.00
0
1
2
3
4
5
6
7
12.0Vin_1.2Vout_500kHz_25C
0.00%
0.01
8
IOUT (A)
5.0Vin_1.2Vout_500kHz_25C
10.00%
12.0Vin_1.2Vout_500kHz_25C
0.10
1.00
IOUT (A)
C004
Figure 23. Load Regulation Performance
10.00
C005
Figure 24. Efficiency Performance
800.00
Frequency (KHz)
700.00
600.00
500.00
400.00
300.00
5.0Vin_1.2Vout_500kHz_25C
12.0Vin_1.2Vout_500kHz_25C
200.00
5.0
5.5
6.0
6.5
7.0
IOUT (A)
7.5
8.0
C006
Figure 25. Switching Frequency Performance
22
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9 Power Supply Recommendations
The TPS53119 is a small-sized single-buck controller with adaptive ON-time D-CAP mode control. The device is
suitable for low output voltage, high current, PC system power rail and similar point-of-load (POL) power supplies
in digital consumer products.
10 Layout
10.1 Layout Guidelines
Certain points must be considered before starting a layout work using the TPS53119.
• Inductors, VIN capacitors, VOUT capacitors and MOSFETs are the power components and must be placed on
one side of the PCB (solder side). Place other small signal components on another side (component side).
Insert at least one inner plane, connected to power ground, in order to shield and isolate the small signal
traces from noisy power lines.
• Place all sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF away from
high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layers as
ground planes and shield feedback trace from power traces and components.
• The DC–DC converter has several high-current loops. The area of these loops must be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitors through the high and
low-side MOSFETs, and back to the capacitors through ground. Connect the negative node of the VIN
capacitors and the source of the low-side MOSFET at ground as close as possible.
– The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors,
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of VOUT capacitors at ground as close as possible.
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from VDRV capacitor through gate driver and the low-side MOSFET, and
back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current
flows from gate of the low-side MOSFET through the gate driver and PGND of the device, and back to
source of the low-side MOSFET through ground. Connect negative node of VDRV capacitor, source of the
low-side MOSFET and PGND of the device at ground as close as possible.
• Because the TPS53119 controls output voltage referring to voltage across VOUT capacitor, the high-side
resistor of the voltage divider should be connected to the positive node of VOUT capacitor at the regulation
point. Connect the low-side resistor to the GND (analog ground of the device). The trace from these resistors
to the VFB pin must be short and thin. Place on the component side and avoid vias between these resistors
and the device.
• Connect the overcurrent setting resistors from the TRIP pin to GND and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to GND should avoid coupling to
a high-voltage switching node.
• Connect the frequency setting resistor from RF pin to GND, or to the PGOOD pin and make the connections
as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to GND
should avoid coupling to a high-voltage switching node.
• Connect all GND (analog ground of the device) trace together and connect to power ground or ground plane
with a single via or trace or through a 0-Ω resistor at a quiet point
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider traces of at least 0.5 mm (20
mils) diameter along this trace.
• The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side
MOSFET, and high-voltage side of the inductor, must be as short and wide as possible.
• Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 22) from the terminal of
ceramic output capacitor. The AC-coupling capacitor (C7 in Figure 22 ) can be placed near the device.
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10.2 Layout Example
TEXAS
I NSTRUMENTS
Copyright © 2017, Texas Instruments Incorporated
Figure 26. TPS53119EVM-690 Top Layer Assembly Drawing, Top View
Figure 27. TPS53119EVM-690 Bottom Assembly Drawing, Bottom View
24
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Layout Example (continued)
Figure 28. TPS53119EVM-690 Top Copper, Top View
Figure 29. TPS53119EVM-690 Layer-2 Copper, Top View
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Layout Example (continued)
Figure 30. TPS53119EVM-690 Layer-3 Copper, Top View
Figure 31. TPS53119EVM-690 Layer-4 Copper, Top View
26
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Layout Example (continued)
Figure 32. TPS53119EVM-690 Layer-5 Copper, Top View
Figure 33. TPS53119EVM-690 Bottom Layer Copper, Top View
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS53119 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
Eco-Mode, D-CAP, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53119RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-20 to 85
53119
TPS53119RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-20 to 85
53119
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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