Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
TPS53126 Dual Synchronous Step-down Controller For Low Voltage Power Rails
1 Features
3 Description
•
The TPS53126 is a dual, adaptive on-time, DCAP2™ mode synchronous Buck controller. The
TPS53126 enables system designers to complete the
suite of various end equipment's power bus
regulators with a cost effective, low external
component count, and low standby current solution.
The main control loop for the TPS53126 uses the DCAP2™ mode control which provides a very fast
transient response with no external components. The
TPS53126 also has a proprietary circuit that enables
the device to adapt to both low equivalent series
resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device provides convenient and
efficient operation with input voltages from 4.5 V to 24
V and output voltages from 0.76 V to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Control
– Fast Transient Response
– No External Parts Required For Loop
Compensation
– Compatible with Ceramic Output Capacitors
High Initial Reference Accuracy (±1%)
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(on) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost Diode
Internal 1.2 ms Voltage-Servo Soft Start
Pre-Biased Soft Start
Selectable Switching Frequency: 350 kHz / 700
kHz
Cycle-by-Cycle Over-Current Limiting Control
30 mV to 300 mV OCP Threshold Voltage
Thermally Compensated OCP by 4000 ppm/C° at
ITRIP
The TPS53126 is available in 4mm x 4mm 24 pin
VQFN (RGE) or 24 pin TSSOP (PW) packages and is
specified from –40°C to 85°C ambient temperature
range.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS53126
VQFN (24)
4.00 mm x 4.00 mm
2 Applications
TPS53126
TSSOP (24)
7.80 mm x 4.40 mm
•
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Point-of-Load Regulation in Low Power Systems
for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles and Other
4 Simplified Schematics
Input Voltage
4.5V to 24V
Q1
FDS8878
C9
10mF
VO1
TEST1
PowerPAD
TRI P1
PGND1 19
VIN
12 PGND2
V5FILT
DRVL1 20
R6
3.3kW
15
16
17
18
C8
1m F
Q1
FDS8878
L1
SPM6530T
1.5mH
SW1 21
11 DRVL2
14
C2
0.1mF
DRVH1 22
TPS53126
RGE
(QFN)
13
R1
13kW
EN1 24
VBST1 23
10 SW2
PGND
1
8 VBST2
9 DRVH2
Q4
FDS8690
2
GND
VO2
7 EN2
C5
0.1mF
3
VFB1
4
TRIP2
C4
22mF ´ 4
5
TEST2
VO2
1.05V/4A
L2
SPM6530T
1.5mH
6
C7
4.7mF
Q2
FDS8690
C3
10mF
R2
10kW
SW1 24
DRVL1 23
3 EN1
PGND1 22
4 VO1
TRIP1 21
5 VFB1
6 GND
R5
10kW
R3
3.3kW
PGND
Input Voltage
VIN 20
TPS53126
PW
(TSSOP)
7 TEST1
V5FILT 18
8 VFB2
TEST2 17
R4
3.52kW
C8
1m F
4.5V to 24V
C9
10mF
VREG5 19
SGND
R3
4.7kW
VO1
1.8V/4A
C1
22mF ´ 4
Q2
FDS8690
C7
4.7mF
VO1
1.8V/4A
C1
22mF ´ 4
1 DRVH1
2 VBST1
C3
10mF
L1
SPM6530T
1.5mH
R2
R1
10kW 13kW
VREG5
Q3
FDS8878
R5
10kW
VFB2
R4
3.52kW
PGND
C6
10mF
C2
0.1mF
SGND
PGND
R6
4.3kW
9 VO2
TRIP2 16
10 EN2
PGND2 15
11 VBST2
DRVL2 14
12 DRVH2
SW2 13
SGND
PGND
Q4
FDS8690
C4
22mF ´ 4
PGND
SGND
C5
0.1mF
L2
SPM6530T
1.5mH
Q3
FDS8878
C6
10mF
PGND
VO2
1.05V/4A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 350 kHz Operation Application .............................. 14
9.3 700 Khz Operation Application ............................... 19
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 23
12.1 Trademarks ........................................................... 23
12.2 Electrostatic Discharge Caution ............................ 23
12.3 Glossary ................................................................ 23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
5 Revision History
Changes from Revision A (July 2013) to Revision B
Page
•
Changed the datasheet to the new TI standard format ......................................................................................................... 1
•
Replaced QFN and TSSOP schematics ............................................................................................................................... 1
•
Changed VVREG5 MIN from 4.8 V to 4.6 V ............................................................................................................................. 5
•
Changed RDRVL Source, IDRVLx = –100 mA MAX from 8 Ω to 12 Ω ........................................................................................ 5
•
Added Design Parameter and Detailed Design Procedure sections ................................................................................... 19
Changes from Original (May 2009) to Revision A
Page
•
Changed Equation 1............................................................................................................................................................. 12
•
Changed Equation 13........................................................................................................................................................... 16
2
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
6 Pin Configurations and Functions
PGND1
DRVL1
20
24 Pin TSSOP
PW Package
(Top View)
DRVH1
VBST1
EN1
VO1
VFB1
GND
TEST1
VFB2
VO2
EN2
VBST2
DRVH2
19
SW1
21
EN1
DRVH1
22
23
24
VBST1
24 Pin VQFN
RGE Package
(Top View)
VO1
1
18
TRIP1
VFB1
2
17
VIN
GND
3
16
TEST1
4
15
VREG5
V5FILT
10
11
12
DRVL2
PGND2
TRIP2
SW2
13
9
6
DRVH2
VO2
8
TEST2
VBST2
14
7
5
EN2
VFB2
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
SW2
Pin Functions
PIN
NAME
VQFN 24
NUMBER
TSSOP 24
NUMBER
I/O
DESCRIPTION
VBST1,
VBST2
23, 8
2, 11
I
Supply input for high-side NFET driver (Boost Terminal). Bypass to SWx with a highquality 0.1μF ceramic capacitor. An external schottky diode can be added if forward drop
is critical to drive the high-side FET.
EN1, EN2
24, 7
3, 10
I
Channel 1 and channel 2 high level enable pins.
VO1, VO2
1, 6
4, 9
I
Output voltage inputs for on-time adjustment and output discharge. Connect directly to the
output voltage.
VFB1,
VFB2
2, 5
5, 8
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
GND
3
6
I
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point.
DRVH1,
DRVH2
22, 9
1, 12
O
High-side MOSFET gate driver outputs. SWx referenced drivers switch between SWx
(OFF) and VBSTx (ON).
SW1, SW2
21, 10
24, 13
I/O
Switch node connections for both the high-side drivers and the current comparators.
DRVL1,
DRVL2
20, 11
23, 14
O
Low-side MOSFET gate driver outputs. PGND referenced drivers switch between PGNDx
(OFF) and VREG5 (ON).
PGND1,
PGND2
19, 12
22, 15
I/O
Power ground connections for both the low-side drivers and the current comparators.
Connect PGND1, PGND2 and GND strongly together near the IC.
TRIP1,
TRIP2
18, 13
21, 16
I
Over current trip point programming pin. Connect to GND with a resistor to GND to set
threshold for low-side RDS(on) current limit.
VIN
17
20
I
Supply Input for 5V linear regulator.
V5FILT
15
18
I
5V supply input for the entire control circuit except the MOSFET drivers. Bypass to GND
with a minimum 1.0μF, high-quality ceramic capacitor. V5FILT is connected to VREG5 via
an internal 10Ω resistor.
VREG5
16
19
O
Output of 5V linear regulator and supply for MOSFET drivers. Bypass to GND with a
minimum 4.7μF high-quality ceramic capacitor. VREG5 is connected to V5FILT via an
internal 10Ω resistor.
TEST1
4
7
O
Test interface pin, not used during application. Connect directly to GND.
TEST2
14
17
I
Frequency select pin. Connect to GND for 350kHz switching. Connect to V5FILT for
700kHz switching.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
3
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
Output voltage
(1)
MIN
MAX
VIN, EN1, EN2
–0.3
26
VBST1, VBST2
–0.3
32
VBST1, VBST2 (wrt SWx)
–0.3
6
V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TEST1,
TEST2
–0.3
6
SW1, SW2
–2
26
DRVH1, DRVH2
–1
32
DRVH1, DRVH2 (wrt SWx)
–0.3
6
DRVL1, DRVL2, VREG5
–0.3
6
PGND1, PGND2
UNIT
V
V
–0.3
0.3
TA
Operating ambient temperature range
–40
85
°C
TJ
Junction temperature range
–40
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
7.3
Electrostatic discharge
MIN
MAX
UNIT
°C
–55
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–2000
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
MIN
Supply input voltage range
Input voltage range
Output voltage range
MAX
VIN
4.5
24
V5FILT
4.5
5.5
VBST1, VBST2
–0.1
30
VBST1, VBST2 (wrt SWx)
–0.1
5.5
VFB1, VFB2, VO1, VO2, TEST1, TEST2
–0.1
5.5
TRIP1, TRIP2
–0.1
0.3
EN1, EN2
–0.1
24
SW1, SW2
–1.8
24
DRVH1, DRVH2
–0.1
30
VBST1, VBST2 (wrt SWx)
–0.1
5.5
DRVL1, DRVL2, VREG5
–0.1
5.5
PGND1, PGND2
–0.1
0.1
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
4
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
7.4 Thermal Information
TPS53126
THERMAL METRIC (1)
PW (24 PINS)
RGE( 24 PINS)
RθJA
Junction-to-ambient thermal resistance
88.9
35.4
RθJC(top)
Junction-to-case (top) thermal resistance
26.5
39.1
RθJB
Junction-to-board thermal resistance
43.5
13.6
ψJT
Junction-to-top characterization parameter
1.1
0.5
ψJB
Junction-to-board characterization parameter
43.0
13.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
3.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5
Electrical Characteristics
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
450
800
μA
30
60
μA
SUPPLY CURRENT
IIN
VIN supply current
VIN current, TA = 25°C, VREG5 tied to V5FLT, EN1 =
EN2 = 5V, VFB1 = VFB2 = 0.8V, SW1 = SW2 = 0.5V
IVINSDN
VIN shutdown current
VIN current, TA = 25°C, No load, EN1 = EN2 = 0 V,
VREG5 = ON
VFB VOLTAGE and DISCHARGE RESISTANCE
VBG
Bandgap initial regulation
accuracy
VVFBTHLx
VFBx threshold voltage
VVFBTHHx
VFBx threshold voltage
IVFB
VFB input current
VFBx = 0.8 V, TA = 25°C
RDischg
VO discharge resistance
ENx = 0 V, VOx = 0.5 V, TA = 25°C
TA = 25°C
-1.0%
TA = 25°C, TEST2 = 0 V, SWinj = OFF
755
TA = –40°C to 85°C, TEST2 = 0 V, SWinj = OFF (1)
752
TA = 25°C, TEST2 = V5FILT, SWinj = OFF
748
TA = –40°C to 85°C, TEST2 = V5FILT, SWinj = OFF (1)
745
1.0%
765
775
778
758
768
771
mV
mV
–0.01
±0.1
μA
40
80
Ω
5.0
5.2
V
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA
VLN5
Line regulation
5.5 V < VIN < 24 V, IVREG5 = 10 mA
20
mV
VLD5
Load regulation
1 mA < IVREG5 < 10 mA
40
mV
IVREG5
Output current
VIN = 5.5 V, VVREG5 = 4 V, TA = 25°C
4.6
170
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
Source, IDRVHx = –100 mA
5.5
11
Sink, IDRVHx = 100 mA
2.5
5
Source, IDRVLx = –100 mA
4
12
Sink, IDRVLx = 100 mA
2
4
0.8
0.9
V
0.1
1
μA
0.85
1.2
1.4
ms
Wake up
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
Ω
Ω
INTERNAL BOOST DIODE
VFBST
Forward voltage
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VBSTx = 29 V, SWx = 24 V, TA = 25°C
0.7
SOFT START
Tss
Internal SS time
Internal soft start VFBx = 0.735 V
UVLO
VUV5VFILT
(1)
V5FILT UVLO threshold
V
Ensured by design. Not production tested.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
5
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
Electrical Characteristics (continued)
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD
VENH
ENx H-level input voltage
EN ½
VENL
ENx L-level input voltage
EN ½
2.0
V
0.3
V
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx = 0.1 V, TA = 25°C
TCITRIP
ITRIP temperature coefficient
On the basis of 25°C (2)
VOCLoff
VRtrip
OCP compensation offset
Current limit threshold setting
range
8.5
10
11.5
4000
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C
–15
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV
–20
20
30
300
0
μA
ppm/°C
15
mV
VTRIPx-GND voltage
mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
VUVP
Output UVP trip threshold
OVP detect
110%
115%
120%
UVP detect
65%
70%
75%
Hysteresis (recovery < 20 μs)
10%
THERMAL SHUTDOWN
TSDN
(2)
Thermal shutdown threshold
Shutdown temperature (2)
150
Hysteresis (2)
°C
20
Ensured by design. Not production tested.
7.6 Timing Requirements
TEST CONDITIONS
MIN
TYP
MAX
DRVHx-low to DRVLx-on
20
50
80
DRVLx-low to DRVHx-on
20
40
80
UNIT
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
tD
Dead time
ns
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tOVPDEL
Output OVP prop delay time
tUVPDEL
Output UVP delay time
tUVPEN
Output UVP enable delay time
μs
1.5
UVP enable delay
17
30
40
μs
1.2
2
2.5
ms
MIN
TYP
MAX
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UNIT
ON-TIME TIMER CONTROL
tON1L
CH1 on time
SW1 = 12 V, VO1 = 1.8 V, TEST2 = 0 V
490
ns
tON2L
CH2 on time
SW2 = 12 V, VO2 = 1.8 V, TEST2 = 0 V
390
ns
tOFF1L
CH1 min off time
SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V, TEST2 = 0 V
285
ns
tOFF2L
CH2 min off time
SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V, TEST2 = 0 V
285
ns
tON1H
CH1 on time
SW1 = 12 V, VO1 = 1.8 V, TEST2 = V5FILT
165
ns
tON2H
CH2 on time
SW2 = 12 V, VO2 = 1.8 V, TEST2 = V5FILT
140
ns
tOFF1H
CH1 min off time
SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V, TEST2 =
V5FILT
216
ns
tOFF2H
CH2 min off time
SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V, TEST2 =
V5FILT
216
ns
6
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
7.8 Typical Characteristics
60
800
IVINSDN − VIN Shutdown Current − µA
IVIN − VIN Supply Current − µA
700
600
500
400
300
200
50
40
30
20
10
100
0
−50
0
50
100
0
−50
150
TJ − Junction Temperature − °C
0
Figure 1. VIN Supply Current vs Junction Temperature
50
100
TJ − Junction Temperature − °C
G001
150
G002
Figure 2. VIN Shutdown Current vs Junction Temperature
5.07
20
VVREG5 − VREG5 Voltage − V
ITRIP − TRIP Source Current − µA
5.06
15
10
5
5.05
5.04
5.03
5.02
5.01
0
−50
0
50
100
TJ − Junction Temperature − °C
5.00
−50
150
Figure 3. Trip Source Current vs Junction Temperature
50
100
150
G004
Figure 4. VREG5 Voltage vs Junction Temperature
5.5
0.800
0.795
5.3
IOUT = 4A
VO1 = 1.8V
0.790
VVFB1 − VFB1 Voltage − V
VVREG5 − VREG5 Voltage − V
0
TJ − Junction Temperature − °C
G003
5.1
4.9
4.7
0.785
TEST2 = GND
0.780
0.775
0.770
0.765
0.760
0.755
4.5
0
5
10
15
20
VIN − Input Voltage − V
25
0.750
−50
0
50
100
TJ − Junction Temperature − °C
G005
150
G006
CH1 = 1.8 V, IO = 4 A
Figure 5. VREG5 Voltage vs Input Voltage
Figure 6. VFB1 Voltage vs Junction Temperature
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
7
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
Typical Characteristics (continued)
0.800
0.800
IOUT = 4A
VO2 = 1.05V
0.795
VVFB1 − VFB1 Voltage − V
VVFB2 − VFB2 Voltage − V
0.790
0.785
0.780
TEST2 = GND
0.775
0.770
0.765
0.780
0.775
0.770
TEST2 = V5FILT
0.765
0.760
0.755
0.755
0
50
100
TJ − Junction Temperature − °C
0.750
−50
150
50
100
150
G008
CH1 = 1.8 V, IO = 4 A
Figure 7. VFB2 Voltage vs Junction Temperature
Figure 8. VFB1 Voltage vs Junction Temperature
0.800
0.800
IOUT = 4A
VO2 = 1.05V
0.795
VO1 = 1.8V
0.795
0.790
VVFB1 − VFB1 Voltage − V
0.790
0.785
0.780
0.775
TEST2 = V5FILT
0.770
0.765
0.785
0.780
TEST2 = GND
0.775
0.770
0.765
0.760
0.760
0.755
0.755
0.750
−50
0.750
0
50
100
TJ − Junction Temperature − °C
150
0
5
10
15
20
VIN − Input Voltage − V
G009
CH2 = 1.05 V, IO = 4 A
25
G010
CH1 = 1.8 V
Figure 9. VFB2 Voltage vs Junction Temperature
Figure 10. VFB1 Voltage vs Input Voltage
0.800
0.800
VO2 = 1.05V
0.795
VO1 = 1.8V
0.795
0.790
VVFB1 − VFB1 Voltage − V
0.790
VVFB2 − VFB2 Voltage − V
0
TJ − Junction Temperature − °C
G007
CH2 = 1.05 V, IO = 4 A
VVFB2 − VFB2 Voltage − V
0.785
0.760
0.750
−50
0.785
0.780
TEST2 = GND
0.775
0.770
0.765
0.785
0.780
0.775
0.770
TEST2 = V5FILT
0.765
0.760
0.760
0.755
0.755
0.750
0.750
0
5
10
15
VIN − Input Voltage − V
20
25
0
5
10
15
VIN − Input Voltage − V
G011
CH2 = 1.05 V
20
25
G012
CH1 = 1.8 V
Figure 11. VFB2 Voltage vs Input Voltage
8
IOUT = 4A
VO1 = 1.8V
0.795
0.790
Submit Documentation Feedback
Figure 12. VFB1 Voltage vs Input Voltage
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
Typical Characteristics (continued)
0.800
VO2 = 1.05V
0.795
VVFB2 − VFB2 Voltage − V
0.790
0.785
0.780
0.775
TEST2 = V5FILT
0.770
0.765
0.760
0.755
0.750
0
5
10
15
20
VIN − Input Voltage − V
25
G013
CH2 = 1.05 V
Figure 13. VFB2 Voltage vs Input Voltage
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
9
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
8 Detailed Description
8.1 Overview
The TPS53126 is a dual, adaptive on-time, D-CAP2™ mode synchronous Buck controller. The TPS53126
enables system designers to complete the suite of various end equipment's power bus regulators with a cost
effective, low external component count, and low standby current solution. The main control loop for the
TPS53126 uses the D-CAP2™ mode control which provides a very fast transient response with no external
components. The TPS53126 also has a proprietary circuit that enables the device to adapt to both low equivalent
series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
The device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output
voltages from 0.76 V to 5.5 V.
8.2 Functional Block Diagram
VREG5
4V/3.7V
TSD
V5FILT
VO1
VO2
VBST1
VBST2
Ref
DRVH1
Ref
BGR
Switcher Controller
DRVH2
Switcher Controller
Fault
SW2
DRVL1
Sdn
Sdn
DRVL2
PGND1
ON2
Fault
ON1
SW1
PGND2
10
Submit Documentation Feedback
TRIP2
VFB2
TEST2
GND
EN2
EN1
TEST1
VFB1
TRIP1
EN/SS Control
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
Functional Block Diagram (continued)
–30%
UV
V5FILT
GND
OV
15%
Ref
SSx
ERR
COMP
V5OK
VFBx
VREG5
GND
Control Logic
TRIPx
VBSTx
OCP
LL
DRVHx
SWx
1 Shot
PGNDx
XCON
VREG5
DRVLx
PGNDx
LLx
VOx
VOx
PGNDx
ENx
On/Off Time
Minimun On/Off
OVP/UVP,
Discharge
Control
Fault
Sdn
8.3 Feature Description
8.3.1 PWM Operation
The main control loop of the TPS53126 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 Mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP mode control.
8.3.2 Drivers
Each SMPS of the TPS53126 contains 2 high-current resistive MOSFET drivers. The Low-side driver is a ground
referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET
whose source is connected to PGND. The High-side Driver is a floating SW referenced VBST powered driver
designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the BST voltage during
the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to
Gate Charge (Qg AT Vgs = 5V) times Switching Frequency (fsw).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
11
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
Feature Description (continued)
8.3.3 PWM Frequency And Adaptive On-time Control
The TPS53126 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS53126 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
8.3.4 5 Volt Regulator
The TPS53126 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all four
drivers and the ICs internal logic. A capacitor from VREG5 to GND is required to stabilize the internal regular. An
internal 10Ω resistor from VREG5 filters the regulator output to the IC’s analog and logic input voltage, V5FILT.
An additional capacitor is required from V5FILT to GND to filter switching noise from VREG5.
8.3.5 Soft Start
The TPS53126 has an internal, 1.2ms, voltage servo soft-start for each channel. When the ENx pin becomes
high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the
output voltage is maintained during start up. As the TPS53126 shares one DAC with both channels, if ENx pin is
set to high while another channel is starting up, soft start is postponed until another channel soft start has
completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time.
8.3.6 Pre-Bias Support
The TPS53126 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage [VFB]), then the TPS53126 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the prebias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
8.3.7 Switching Frequency Selection
The TPS53126 allows the user to select from 2 different switching frequencies by connecting the TEST2 pin to
either GND or V5FILT. Connect TEST2 to GND for a switching frequency (fsw) of 350KHz. Connect TEST2 to
V5FILT for a switching frequency of 700KHz.
8.3.8 Output Discharge Control
The TPS53126 discharges the outputs when ENx is low, or when the controller is turned off by the protection
functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges an output using an internal 40-Ω
MOSFET which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the
output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge
ensures that, on start, the regulated voltage always initializes from zero volts.
8.3.9 Overcurrent Limit
The TPS53126 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current
by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53126 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIPx pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
Vtrip = IOCL
R trip (kW) =
12
2
x
VIN VO
L1 x fsw
x
VO
VIN
x
RDS(on)
(1)
Vtrip (mV)
Itrip (mA)
(2)
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
Feature Description (continued)
The trip voltage should be between 30mV to 300mV over all operational temperature, including the 4000ppm/°C
temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the
over-current limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall
below the under voltage protection threshold and the TPS53126 will shut down.
8.3.10 Over/under Voltage Protection
The TPS53126 monitors the output voltage via the feedback voltage to detect over and under voltage. When the
feedback voltage becomes higher than 115% of the reference voltage, the TPS53126 turns off the high-side
MOSFET driver, turns on the low-side MOSFET driver and latches off.
When the feedback voltage becomes lower than 70% of the reference voltage, the TPS53126 begins an internal
UVP delay counter. After 30μs, the TPS53126 turns off both top and bottom MOSFET drivers and latches off.
The UVP function is enabled approximately 2.0ms after power-on to prevent detecting UVP during soft-start.
Both OVP and UVP latch conditions are reset when V5FILT triggers UVLO or the ENx pin goes low.
8.3.11 UVLO Protection
The TPS53126 has under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the
V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. During shut-off, VREG5 and all
output drivers are OFF and output discharge is ON. The UVLO is non-latch protection.
8.3.12 Thermal Shutdown
The TPS53126 includes an over temperature protection shut-down feature. If the TPS53126 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
8.4 Device Functional Modes
The TPS53126 has two operating modes. The TPS53126 is in shut down mode when the EN1 and EN2 pins are
low. When the EN1 and EN2 pins is pulled high, the TPS53126 enters the normal operating mode.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
13
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
9 Application and Implementation
9.1 Application Information
9.2 350 kHz Operation Application
The schematic of Figure 14 shows a typical 350 kHz application schematic. The 350 kHz switching frequency is
selected by connecting TEST2 to the GND pin. The input voltage is 4.5 V to 24 V and the output voltage is 1.8 V
for VO1 and 1.05 V for VO2.
Input Voltage
4.5V to 24V
C9
10mF
SGND
6
5
4
3
2
1
VFB2
TEST1
GND
VFB1
VO1
R2
R1
10kW 13kW
VO2
PGND
7 EN2
Q3
FDS8878
C6
10mF
R5
10kW
R4
3.52kW
C5
0.1mF
L2
SPM6530T
1.5mH
VBST1 23
8 VBST2
PowerPAD
9 DRVH2
PGND
VIN
TRI P1
PGND1 19
VREG5
12 PGND2
V5FILT
DRVL1 20
TEST2
11 DRVL2
13
14
15
16
17
18
R6
3.3kW
L1
SPM6530T
1.5mH
SW1 21
TRIP2
C4
22mF ´ 4
Q4
FDS8690
Q1
FDS8878
C2
0.1mF
DRVH1 22
TPS53126
RGE
(QFN)
10 SW2
VO2
1.05V/4A
EN1 24
C7
4.7mF
R3
4.7kW
Q2
FDS8690
C3
10mF
VO1
1.8V/4A
C1
22mF ´ 4
PGND
C8
1m F
PGND
SGND
Figure 14. Typical Application Circuit at 350kHz Switching Frequency Selection (TEST2 Pin = GND)
9.2.1 Design Requirements
Table 1. Design Parameters
PARAMETERS
CHANNEL 1
CHANNEL 2
Input voltage
4.5 V to 24 V
4.5 V to 24 V
Output voltage
1.8 V
1.05 V
Output Current
4A
4A
Switching Frequency
350 kHz
350 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Choose Inductor
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 3 can be used to calculate L1.
14
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
L1 =
SLUS909B – MAY 2009 – REVISED AUGUST 2014
(VIN(max)
)´
- Vo1
IL1(ripple) ´ ƒsw
Vo1
VIN(max)
=
3 ´
(VIN(max) - Vo1) ´
Io1 ´ ¦ sw
Vo1
VIN(max)
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current.
The RMS and peak inductor current can be estimated as follows:
VIN(max) - Vo1
Vo1
IL1(ripple) =
´
L1 ´ ¦ sw
VIN(max)
(4)
IL1(peak) =
Vtrip
RDS(on)
+ IL1(ripple)
(5)
(
IL1(RMS) = Io12 + 112 IL1(ripple)
2
)
(6)
Note: The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.
9.2.2.2 Choose Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Recommend to use ceramic output capacitor.
C1 =
DIload2 ´ L1
2 ´ Vo1 ´ DVos
(7)
2
C1 =
ΔIload ´ L1
2 ´ K ´ DVus
(8)
Where:
Tmin(off)
Ton1
æ
ö
K = ç (VIN - Vo1) ´ Vo1÷ ´
Ton1
è
ø Ton1 + Tmin(off)
C1 =
IL1(ripple)
8 Vo1(ripple)
´
(9)
1
¦ sw
(10)
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and
Equation 10. The capacitance for C1 should be greater than 66 μF.
Where:
ΔVos = the allowable amount of overshoot voltage in load transition
ΔVus = the allowable amount of undershoot voltage in load transition
Tmin(off) = Min-off time
9.2.2.3 Choose Input Capacitor
The TPS53126 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
9.2.2.4 Choose Bootstrap Capacitor
The TPS53126 requires a bootstrap capacitor from SWx to VBSTx to provide the floating supply for the high-side
drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater
than 6 V.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
15
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
9.2.2.5 Choose VREG5 and V5FILT Capacitors
The TPS53126 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF highquality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum
1.0-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation.
Both of these capacitors’ voltage ratings should be greater than 6 V.
9.2.2.6 Choose Output Voltage Set Point Resistors
The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to
use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 and
Equation 12 to calculate R1.
æ
ö
ç
÷
Vo1
- 1÷ ´ R2
R1 = ç
VFB1(ripple)
ç
÷
ç 0.765 +
÷
2
è
ø
(TEST2=GND)
(11)
æ
ö
ç
÷
Vo1
R1 = ç
- 1÷ ´ R2
ç 0.758 + VFB1(ripple)
÷
ç
÷
2
è
ø
(TEST2 = V5FILT)
(12)
Where:
VFB1(ripple) = Ripple Voltage at VFB1
9.2.2.7 Choose Over Current Limit Set Point Resistors
Vtrip = IOCL
R trip (kW) =
2
x
VIN VO
L1 x fsw
x
VO
VIN
x
RDS(on)
(13)
Vtrip (mV)
Itrip (mA)
(14)
Where:
RDS(on) = Low Side FET on-resistance
Itrip = TRIP pin source current （= 10 μA）
IOCL = Over current limit
16
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
9.2.3 350 kHz Application Curves
Application curves Figure 15, Figure 16, Figure 17, Figure 18, Figure 23 and Figure 24 apply to both the circuits
of 350 kHz Operation Application and 700 Khz Operation Application.
800
800
700
700
fSW − Switching Frequency − kHz
fSW − Switching Frequency − kHz
TEST2 = V5FILT
600
500
400
TEST2 = GND
300
200
IOUT = 3A
VO1 = 1.8V
100
600
TEST2 = V5FILT
500
400
300
TEST2 = GND
200
IOUT = 3A
VO2 = 1.05V
100
0
0
0
5
10
15
20
25
VIN − Input Voltage − V
0
5
10
G014
IO1 = 3 A
15
20
25
VIN − Input Voltage − V
G015
IO2 = 3 A
Figure 16. SWITCHING FREQUENCY vs INPUT VOLTAGE
(CH2)
1.85
1.10
1.84
1.09
1.83
1.08
1.82
VOUT − Output Voltage − V
VOUT − Output Voltage − V
Figure 15. SWITCHING FREQUENCY vs INPUT VOLTAGE
(CH1)
TEST2 = V5FILT
1.81
1.80
TEST2 = GND
1.79
1.78
1.77
1.76
1.75
0.0
1.07
1.06
TEST2 = V5FILT
1.05
TEST2 = GND
1.04
1.03
1.02
VIN = 12V
VO1 = 1.8V
0.5
1.01
1.0
1.5
2.0
2.5
3.0
3.5
1.00
0.0
4.0
IOUT − Output Current − A
VIN = 12V
VO2 = 1.05V
0.5
VIN = 12 V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT − Output Current − A
G016
G017
VIN = 12 V
Figure 17. OUTPUT VOLTAGE vs OUTPUT CURRENT
(CH1)
Figure 18. OUTPUT VOLTAGE vs OUTPUT CURRENT
(CH2)
VO2 (50mV/div)
VO1 (50mV/div)
TEST2 = GND
350kHz Selection
TEST2 = GND
350kHz Selection
Iout2 (2A/div)
Iout1 (2A/div)
t − time − 100µs/div
COUT = 22µF × 4
t − time − 100µs/div
G018
COUT = 22µF × 4
G020
CH2, TEST2 = GND
CH1, TEST2 = GND
Figure 19. 1.8V LOAD TRANSIENT RESPONSE
Figure 20. 1.05V LOAD TRANSIENT RESPONSE
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
17
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
100
TEST2 = GND
350kHz Selection
80
η − Efficiency − %
EN1 (10V/div)
VO1 (0.5V/div)
60
40
TEST2 = GND
350kHz Selection
20
VIN = 12V
VO1 = 1.8V
G022
0
0
1
2
3
4
IOUT − Output Current − A
Figure 21. 1.8V START-UP WAVEFORMS
G024
VIN = 12 V
1.90
1.15
1.88
1.13
1.86
1.11
VOUT − Output Voltage − V
VOUT − Output Voltage − V
Figure 22. 1.8V EFFICIENCY vs OUTPUT CURRENT (CH1)
1.84
TEST2 = V5FILT
1.82
1.80
TEST2 = GND
1.78
1.76
1.74
1.09
TEST2 = V5FILT
1.07
1.05
TEST2 = GND
1.03
1.01
0.99
IOUT = 3A
VO1 = 1.8V
1.72
IOUT = 3A
VO2 = 1.05V
0.97
1.70
0.95
0
5
10
15
VIN − Input Voltage − V
20
25
0
5
G026
IO = 3 A
10
15
VIN − Input Voltage − V
20
25
G027
IO = 3 A
Figure 23. 1.8V OUTPUT VOLTAGE vs INPUT VOLTAGE
Figure 24. 1.05V OUTPUT VOLTAGE vs INPUT VOLTAGE
VO1 (20mV/div)
VO1 = 1.8V
TEST2 = GND
350kHz Selection
G028
Figure 25. 1.8V OUTPUT RIPPLE VOLTAGE
18
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
9.3 700 Khz Operation Application
The schematic of Figure 26 shows a typical 700 kHz application schematic. The 700 kHz switching frequency
is selected by connecting TEST2 to the V5FILT pin. The input voltage is 4.5 V to 24 V and the output voltage
is 1.8 V for VO1 and 1.05 V for VO2.
Input Voltage
4.5V to 24V
C9
10mF
SGND
Q3
FDS8878
C6
10mF
L2
SPM6530T
1.5mH
6
5
4
3
2
1
TEST1
GND
VFB1
VO1
R2
R1
10kW 13kW
VFB2
PGND
R5
10kW
VO2
R4
3.52kW
7 EN2
C5
0.1mF
VBST1 23
8 VBST2
PowerPAD
9 DRVH2
PGND
VIN
TRI P1
PGND1 19
VREG5
12 PGND2
V5FILT
DRVL1 20
TEST2
11 DRVL2
13
14
15
16
17
18
R6
3.3kW
Q1
FDS8878
L1
SPM6530T
1.5mH
C3
10mF
SW1 21
TRIP2
C4
22mF ´ 4
Q4
FDS8690
C2
0.1mF
DRVH1 22
TPS53126
RGE
(QFN)
10 SW2
VO2
1.05V/4A
EN1 24
C7
4.7mF
R3
4.7kW
VO1
1.8V/4A
C1
22mF ´ 4
Q2
FDS8690
PGND
C8
1m F
PGND
SGND
Figure 26. Typical Application Circuit at 700 kHz Switching frequency Selection (TEST2 Pin = V5FILT)
9.3.1 Design Parameters
PARAMETERS
CHANNEL 1
CHANNEL 2
Input voltage
4.5 to 24 V
4.5 to 24 V
Output voltage
1.8 V
1.05 V
Output current
4A
4A
Switching Frequency
700 kHz
700 kHz
9.3.2 Detailed Design Procedure
For the Detailed Design Procedure, refer to Detailed Design Procedure.
9.3.3 700 kHz Application Curves
Application curves Figure 15, Figure 16, Figure 17, Figure 18, Figure 23 and Figure 24 apply to both the
circuits of 350 kHz Operation Application and 700 Khz Operation Application.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
19
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
VO1 (50mV/div)
VO2 (50mV/div)
TEST2 = V5FILT
700kHz Selection
TEST2 = V5FILT
700kHz Selection
Iout1 (2A/div)
t − time − 100µs/div
Iout2 (2A/div)
COUT = 22µF × 2
t − time − 100µs/div
G019
CH1, TEST2 = V5FILT
COUT = 22µF × 2
G021
CH2, TEST2 = V5FILT
Figure 27. 1.8V LOAD TRANSIENT RESPONSE
Figure 28. 1.05V LOAD TRANSIENT RESPONSE
100
80
EN2 (5V/div)
η − Efficiency − %
TEST2 = V5FILT
700kHz Selection
VO2 (0.2V/div)
TEST2 = V5FILT
700kHz Selection
60
40
20
VIN = 12V
VO2 = 1.05V
G023
0
0
1
2
3
IOUT − Output Current − A
Figure 29. 1.05V START-UP WAVEFORMS
4
G025
VIN = 12 V
Figure 30. 1.05V EFFICIENCY vs OUTPUT CURRENT (CH2)
VO2 (20mV/div)
VO2 = 1.05V
TEST2 = V5FILT
700kHz Selection
G029
Figure 31. 1.05V OUTPUT RIPPLE VOLTAGE
20
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
10 Power Supply Recommendations
The TPS53126 is designed to operate from an input voltage supply range between 4.5 V and 24 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS53126 device
additional 0.1 µF ceramic capacitance may be required in addition to the ceramic bypass capacitors, 10 µF.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
Keep the input switching current loop as small as possible. (VIN ≥ C3 ≥ PNGD ≥ Sync FET ≥ SW ≥ Control
FET)
Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as
small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal (FBx) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.(1)
Do not allow switching current to flow under the device.
DRVH and DRVL line should not run close to SW node or minimize it. (2)
GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected
to SGND. (3)
GND terminals for capacitors of VREG5 and VIN should be connected to PGND. (4)
Signal lines should not run under/near Output Inductor or minimize it. (5)
11.2 Layout Example
The layout example of Figure 32 corresponds to the schematic of Figure 14.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
21
TPS53126
SLUS909B – MAY 2009 – REVISED AUGUST 2014
www.ti.com
Layout Example (continued)
VIN
Q3
Q1
SW2
SW1
C3
C6
Q4
Q2
(4)
C9
(5)
(5)
L1
L2
(3) R6
C8
R3
(3)
C7
TRIP2
TEST2
V5FILT
12 PGND2
C4, 1
16
17
18
TRIP1
15
VREG5
14
VIN
13
PGND1 19
C1, 1
DRVL1 20
11 DRVL2
(QFN )
10 SW2
C4, 2
TPS53126
9 DRVH2
C5
VFB2
TEST1
GND
VFB1
VO1
5
4
3
2
1
TO EN 1
C1, 3
R1
R4
C4, 4
C1, 2
EN1 24
6
R2
R5
VOUT2
C2
VBST1 23
VO2
7 EN2
TO EN 2
DRVH1 22
RGE
Thermal PAD
8 VBST2
C4, 3
SW1 21
PGND
(3)
C1, 4
VOUT1
(1)
Top Side Component or Via
Bottom Side Component
Top Side Etch
Bottom Side Etch
Component Pads Shown in White
SGND
Figure 32. Board Layout
22
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
TPS53126
www.ti.com
SLUS909B – MAY 2009 – REVISED AUGUST 2014
12 Device and Documentation Support
12.1 Trademarks
D-CAP2 is a trademark of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS53126
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53126PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS53126
TPS53126PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS53126
TPS53126RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53126
TPS53126RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53126
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
