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TPS53127
SLVSA93A – MARCH 2010 – REVISED AUGUST 2014
TPS53127 Dual Synchronous Step-Down Controller
For Low Voltage Power Rails
1 Features
3 Description
•
The TPS53127 is a dual, adaptive on-time D-CAP2™
mode synchronous buck controller. The part enables
system designers to cost effectively complete the
suite of various end equipment's power bus
regulators with a low external component count and
low standby consumption. The main control loop for
the TPS53127 uses the D-CAP2™ Mode topology
which provides a very fast transient response with no
external component.
1
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Control
– Fast Transient Response
– No External Parts Required for Loop
Compensation
– Compatible With Ceramic Output Capacitors
High Initial Reference Accuracy (±1%)
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(ON) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost Diode
Adjustable Soft Start
Non-Sinking Pre-Biased Soft Start
700-kHz Switching Frequency
Cycle-by-Cycle Over-Current Limiting Control
30-mV to 300-mV OCP Threshold Voltage
Thermally Compensated OCP by 4000 ppm/°C at
ITRIP
The TPS53127 also has a proprietary circuit that
enables the device to adapt not only low equivalent
series resistance (ESR) output capacitors such as
POSCAP/SP-CAP, but also ceramic capacitor. The
part provides a convenient and efficient operation
with conversion voltages from 4.5 V to 24 V and
output voltage from 0.76 V to 5.5 V.
The TPS53127 is available in the 24 pin RGE/PW
package, and is specified from –40°C to 85°C
ambient temperature range.
Device Information(1)
DEVICE NAME
2 Applications
•
PACKAGE
TPS53127
Point-of-Load Regulation in Low Power Systems
for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Pin
– Digital Set-Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles
BODY SIZE (NOM)
TSSOP (24)
7.80mm x 4.40mm
VQFN (24)
4.00mm x 4.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet
4 Simplified Schematic
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
C5
0.1uF
VBST2
9
3
2
1
VFB1
VO1
VO2
EN2
8
4
SS1
5
GND
6
7
SGND
R1
13.5kΩ
EN1
24
VBST1 23
Power PAD
C2
0.1uF
DRVH1 22
DRVH2
TPS53127 RGE
SW1
Q1
FDS8878
L1
SPM6530T
1.5uH
10
SW2
21
L1
11
DRVL2
DRVL1 20
PGND2
PGND1 19
Q2
FDS8690
C3
10uF
VO1
1.8V/4A
PGND
V5FILT
VREG5
VIN
TRIP1
12
C4
22uFx2
SS2
(QFN )
Q4
FDS8690
TRIP2
VO2
1.05V/4A
Q3
FDS8878
L2
SPM6530T
1.5uH
R2
10kΩ
VFB2
R4
3.63kΩ
PGND
C6
10uF
R5
10kΩ
13
14
15
16
17
18
R6
4.7kΩ
C7
4.7uF
C８
1uF
C1
22uFx2
R３
4.3kΩ
PGND
PGND
C11
4700pF
SGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53127
SLVSA93A – MARCH 2010 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application, QFN ........................................ 13
9.3 Typical Application Circuit, TSSOP......................... 18
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Trademarks ........................................................... 20
12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
5 Revision History
Changes from Original (March 2010) to Revision A
Page
•
Changed the data sheet to the new TI format ....................................................................................................................... 1
•
Added TA value to the Abs Max table .................................................................................................................................... 4
•
Added the Handling Ratings table ......................................................................................................................................... 4
•
Added TA value to the ROC table........................................................................................................................................... 4
•
Added the Thermal Information table .................................................................................................................................... 5
•
Changed the VVREG5 MIN value From: 4.8 V to 4.6 V ........................................................................................................... 5
•
Changed the RDRVL MAX value for –100 mA From: 8 Ω To 12 Ω .......................................................................................... 5
•
Changed the I(SSC) Min value From: -1.5 to -2.5 µA and the Max value From: -2.5 To: -1.5 µA............................................ 6
•
Added the Timing Requirements table .................................................................................................................................. 6
•
Added the Switching Characteristics table ............................................................................................................................. 6
•
Added the Layout Example, Figure 28 ................................................................................................................................ 19
2
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SLVSA93A – MARCH 2010 – REVISED AUGUST 2014
6 Pin Configuration and Functions
20
PGND1
TSSOP Package
Top View
DRVH1
VBST1
4
15
V5 FILT
VFB2
5
14
SS2
VO2
6
13
TRIP2
11
SS1
12
VREG5
PGND2
16
10
3
SW2
GND
DRVL2
VIN
9
17
DRVH2
TRIP1
8
18
2
VBST2
1
VFB1
7
VO1
EN2
EN1
VO1
VFB1
GND
19
SW1
DRVL1
21
DRVH1
22
VBST1
23
24
EN1
QFN Package
Top View
SS1
VFB2
VO2
EN2
VBST2
DRVH2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
SS2
TRIP2
PGND2
DRVL2
SW2
Pin Functions
PIN
NAME
QFN
24
TSSOP
24
I/O
VBST1,
VBST2
23, 8
2, 11
I
Supply input for high-side NFET driver. Bypass to SWx with a high-quality 0.1μF ceramic capacitor. An external schottky diode can be added from VREG5 if
forward drop is critical to drive the high-side FET.
EN1, EN2
24, 7
3, 10
I
Enable. Pull High to enable SMPS.
VO1, VO2
1, 6
4, 9
I
Output voltage inputs for on-time adjustment and output discharge. Connect
directly to the output voltage.
VFB1,
VFB2
2, 5
5, 8
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
GND
3
6
I
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
point.
DRVH1,
DRVH2
22, 9
1, 12
O
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
switch between SWx (OFF) and VBSTx (ON).
SW1, SW2
21, 10
24, 13
I/O
Switch node connections for both the high-side drivers and the over current
comparators.
DRVL1,
DRVL2
20, 11
23, 14
O
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
switch between PGNDx (OFF) and VREG5 (ON).
PGND1,
PGND2
19, 12
22, 15
I/O
Power ground connections for both the low-side drivers and the over current
comparators. Connect PGND1, PGND2 and GND strongly together near the
IC.
TRIP1,
TRIP2
18, 13
21, 16
I
Over current threshold programming pin. Connect to GND with a resistor to
GND to set threshold for low-side RDS(ON) current limit.
VIN
17
20
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum highquality 0.1-μF ceramic capacitor.
V5FILT
15
18
I
5-V supply input for the entire control circuitry except the MOSFET drivers.
Bypass to GND with a minimum high-quality 1.0-μF ceramic capacitor. V5FILT
is connected to VREG5 via an internal 10-Ω resistor.
VREG5
16
19
O
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
with a minimum high-quality 4.7-μF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-Ω resistor.
4,14
7, 17
O
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
soft-start time.
SS1, SS2
DESCRIPTION
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range
(1)
MIN
MAX
VIN, EN1, EN2
–0.3
26
VBST1, VBST2
–0.3
32
VBST1 - SW1, VBST2 - SW2
–0.3
6
V5FILT, VFB1, VFB2, TRIP1, TRIP2,
VO1, VO2
–0.3
6
SW1, SW2
–2
26
DRVH1, DRVH2
–1
32
DRVH1 - SW1, DRVH2 - SW2
–0.3
6
DRVL1, DRVL2, VREG5, SS1, SS2
–0.3
6
PGND1, PGND2
UNIT
V
VO
Output voltage range
–0.3
0.3
TA
Operating free-air temperature
–40
85
°C
TJ
Junction temperature range
–40
150
°C
(1)
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
TSTG
V(ESD)
(1)
(2)
Storage temperature range
Electrostatic discharge
MIN
MAX
UNIT
–55
150
°C
Human body model (HBM), per
AN/ESDA/JEDEC JS-001, all pins (1)
–2000
2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VI
VO
Supply input voltage
Input voltage
Output voltage
MIN
MAX
VIN
4.5
24
V5FILT
4.5
5.5
VBST1, VBST2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
VFB1, VFB2, VO1, VO2
–0.1
5.5
TRIP1, TRIP2
–0.1
0.3
EN1, EN2
–0.1
24
SW1, SW2
–1.8
24
DRVH1, DRVH2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
DRVL1, DRVL2, VREG5, SS1, SS2
–0.1
5.5
PGND1, PGND2
–0.1
0.1
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
4
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7.4 Thermal Information
TPS53127
THERMAL METRIC (1)
PW 24 PINS
RGE 24 PINS
RθJA
Junction-to-ambient thermal resistance
88.9
35.4
RθJC(top)
Junction-to-case (top) thermal resistance
26.5
39.1
RθJB
Junction-to-board thermal resistance
43.5
13.6
ψJT
Junction-to-top characterization parameter
1.1
0.5
ψJB
Junction-to-board characterization parameter
43.0
13.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
3.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
450
800
μA
30
60
μA
1
%
SUPPLY CURRENT
IIN
VIN supply current
VIN current, TA = 25°C, VREG5 tied
to V5FILT, EN1 = EN2 = 5 V,
VFB1 = VFB2 = 0.8 V,
SW1 = SW2 = 0.5 V
I(VINSDN)
VIN shutdown current
VIN current, TA = 25°C,
no load , EN1 = EN2 = 0 V,
VREG5 = ON
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG
Bandgap initial regulation accuracy
TA = 25°C
TA = 25°C, SWinj = OFF
V(VFBTHx)
VFBx threshold voltage
TA = 0°C to 70°C,
SWinj = OFF (1)
TA = -40°C to 85°C,
SWinj = OFF (1)
I(VFB)
VFB input current
VFBx = 0.8 V, TA = 25°C
R(Dischg)
VO discharge resistancee
ENx = 0 V, VOx = 0.5 V, TA = 25°C
–1
748
758
768
746.6
769.4
745
771
–100
mV
–10
100
nA
40
80
Ω
5.0
5.2
V
VREG5 OUTPUT
V(VREG)5
VREG5 output voltage
TA = 25°C, 5.5 V < VIN < 24 V,
0 < I(VREG5) < 10 mA
V(LN5)
Line regulation
5.5 V < VIN < 24 V, I(VREG5) = 10
mA
20
mV
V(LD5)
Load regulation
1 mA < I(VREG5) < 10 mA
40
mV
Output current
VIN = 5.5 V, V(REG5) = 4.0 V,
TA = 25°C
I(VREG5)
4.6
170
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
R(DRVH)
DRVH resistance
R(DRVL)
DRVL resistance
Source, I(DRVHx) = –100 mA
5.5
11
Sink, I(DRVHx) = 100 mA
2.5
5
Source, I(DRVLx) = –100 mA
4
12
Sink, I(DRVLx) = 100 mA
2
4
0.8
0.9
V
0.1
1
μA
Ω
Ω
INTERNAL BOOST DIODE
V(FBST)
Forward voltage
V(VREG5-VBSTx), IF = 10 mA,
TA = 25°C
I(VBSTLK)
VBST leakage current
VBSTx = 29 V, SWx = 24 V,
TA = 25°C
(1)
0.7
Not production tested - specified by design.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–2.5
–2
–1.5
UNIT
SOFT START
I(SSC)
SS1/SS2 charge current
VSS1/VSS2 = 0 V, TA = 25°C
TC(ISSC)
ISSC temperature coefficient
On the basis of 25°C (2)
ISSD
SS1/SS2 discharge current
VSS1/VSS2 = 0.5 V
100
150
Wake up
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
2.0
–4
3
μA
nA/°C
μA
UVLO
V(UV5VFILT)
V5FILT UVLO threshold
V
LOGIC THRESHOLD
V(ENH)
ENx high-level input voltage
EN 1/2
V(ENL)
ENx low-level input voltage
EN 1/2
V
0.3
V
CURRENT SENSE
I(TRIP)
TRIP source current
V(TRIPx) = 0.1 V, TA = 25°C
TC(ITRIP)
ITRIP temperature coefficient
On the basis of 25°C
VOC(Loff)
OCP compensation offset
VR(trip)
Current limit threshold setting range
8.5
10
11.5
4000
μA
ppm/°C
(V(TRIPx-GND) - V(PGNDx-SWx)) voltage,
V(TRIPx-GND) = 60 mV, TA = 25°C
–15
(V(TRIPx-GND) - V(PGNDx-SWx)) voltage,
V(TRIPx-GND) = 60 mV
–20
20
30
300
mV
%
V(TRIPx-GND) voltage
0
15
mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
VUVP
Output UVP trip threshold
OVP detect
110
115
120
UVP detect
65
70
75
Hysteresis (recover < 20 μs)
10
%
THERMAL SHUTDOWN
TSDN
(2)
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(2)
150
(2)
°C
20
Not production tested - specified by design.
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
DRVHx-low to DRVLx-on
20
50
80
ns
DRVLx-low to DRVHx-on
20
40
80
ns
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
tD
Dead time
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tOVPDEL
Output OVP prop delay
tUVPDEL
Output UVP delay
tUVPEN
Output UVP enable delay
1.5
UVP enable delay / soft-start time
µs
17
30
40
µs
x1.4
x1.7
x2.0
ms
MIN
TYP
MAX
UNIT
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
ON-TIME TIMER CONTROL
tON1L
CH1 on time
SW1 = 12 V, VO1 = 1.8 V
165
ns
tON2L
CH2 on time
SW2 = 12 V, VO2 = 1.8 V
140
ns
tOFF1L
CH1 min off time
SW1 = 0.7 V, TA = 25°C,
VFB1 = 0.7 V
216
ns
tOFF2L
CH2 min off time
SW2 = 0.7 V, TA = 25°C,
VFB2 = 0.7 V
216
ns
6
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7.8 Typical Characteristics
800
60
IVINSDN - Shutdown Current - mA
IIN - Supply Current - mA
700
600
500
400
300
200
50
40
30
20
10
100
VREG5=ON
0
-50
0
50
100
0
-50
150
0
50
TJ - Junction Temperature - °C
100
150
TJ - Junction Temperature - °C
Figure 1. VIN Supply Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs Junction Temperature
5.070
20
5.060
VREG5 Voltage - V
ITRIP - Source Current - mA
15
10
5.050
5.040
5.030
5.020
5
5.010
0
-50
0
50
100
5.000
-50
150
0
50
100
150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 4. VREG5 Voltage vs Junction Temperature
Figure 3. Trip Source Current vs Junction Temperature
0.790
5.500
0.785
0.780
VFB1 Voltage - V
VREG5 Voltage - V
5.300
5.100
4.900
0.775
0.770
0.765
0.760
0.755
0.750
4.700
0.745
0.740
4.500
0
5
10
15
20
25
-50
VIN - Input Voltage - V
0
50
100
150
TJ - Junction Temperature - °C
Figure 5. VREG5 Voltage vs Input Voltage
Figure 6. VFB1 Voltage vs Junction Temperature
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0.790
0.790
0.785
0.785
0.780
0.780
0.775
0.775
VFB1 Voltage - V
VFB2 Voltage - V
Typical Characteristics (continued)
0.770
0.765
0.760
0.755
0.770
0.765
0.760
0.755
0.750
0.750
0.745
0.745
0.740
0.740
-50
0
50
100
150
0
5
TJ - Junction Temperature - °C
10
15
20
25
VIN - Input Voltage - V
Figure 7. VFB2 Voltage vs Junction Temperature
Figure 8. VFB1 Voltage vs Input Voltage
0.790
800
0.785
700
VO1 = 5 V
VO1 = 3.3 V
fSW - Switching Frequency - kHz
VFB2 Voltage - V
0.780
0.775
0.770
0.765
0.760
0.755
0.750
VO1 = 2.5 V
600
VO1 = 1.8 V
500
VO1 = 1.2 V
400
VO1 = 1.05 V
300
200
100
0.745
0
0
0.740
0
5
10
15
20
5
10
15
20
25
VIN - Input Voltage - V
25
VIN - Input Voltage - V
Figure 9. VFB2 Voltage vs Input Voltage
Figure 10. Switching Frequency (IO1 = 3 A) vs Input Voltage
(CH1)
800
VO2 = 5 V
fSW - Switching Frequency - kHz
700
VO2 = 3.3 V
VO2 = 2.5 V
600
VO2 = 1.8 V
500
VO2 = 1.2 V
400
VO2 = 1.05 V
300
200
100
0
0
5
10
15
VIN - Input Voltage - V
20
25
Figure 11. Switching Frequency (IO2 = 3 A) vs Input Voltage (CH2)
8
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8 Detailed Description
8.1 Overview
The TPS53127 is a dual, adaptive on-time D-CAP2™ mode synchronous Buck controller. The main control loop
for the TPS53127 uses the D-CAP2™ mode control which provides a fast transient response with no external
components. The TPS53127 also has a proprietary circuit that enables the device to adapt to both low equivalent
series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
The device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output
voltages from 0.76 V to 5.5 V.
8.2 Functional Block Diagram
SS2
SW
SS1
SW
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Functional Block Diagram (continued)
ERR
COMP
SWx
8.3 Feature Description
8.3.1 PWM Operation
The main control loop of the TPS53127 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer
expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot
timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage
VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal
ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output
ripple from D-CAP mode control.
8.3.2 Drivers
Each channel of the TPS53127 contains two high-current resistive MOSFET gate drivers. The low-side driver is a
PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(ON) N-channel
MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered
driver designed to drive the gate of a high-current, low RDS(ON) N-channel MOSFET. To maintain the VBST
voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws
average current equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW).
10
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Feature Description (continued)
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
8.3.3 PWM Frequency and Adaptive On-Time Control
TPS53127 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53127 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
8.3.4 5-Volt Regulator
The TPS53127 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the IC's internal logic. A high-quality 4.7-μF or greater ceramic capacitor from VREG5 to GND is required to
stabilize the internal regulator. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's
analog and logic input voltage, V5FILT. An additional high-quality 1.0-μF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
8.3.5 Soft Start
The TPS53127 has a programmable soft-start . When the ENx pin becomes high, 2.0-μA current begins charging
the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control
comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference
for smooth control of the output voltage during start up.
8.3.6 Pre-Bias Support
The TPS53127 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage (VFB)), then the TPS53127 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the prebias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
8.3.7 Output Discharge Control
TPS53127 discharges the outputs when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which
is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start
the regulated voltage always initializes from 0 V.
8.3.8 Over Current Limit
TPS53127 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(ON) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53127 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(ON) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(
)
(VIN - VO) VO
VTRIP = IOCL - ¾
· ¾
2 · L1 · fSW VIN
·
RDS(ON)
(1)
VTRIP (mV)
RTRIP (kW) = ¾
ITRIP (mA)
(2)
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Feature Description (continued)
The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the 4000ppm/°C temperature slope compensation for the temperature dependency of the RDS(ON).
If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions
continues the output voltage will fall below the under voltage protection threshold and the TPS53127 will shut
down.
In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
8.3.9 Over/Under Voltage Protection
TPS53127 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 30 μs, TPS53127 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 x TSS after power-on. The OVP and UVP latch off is
reset when EN goes low level.
8.3.10 UVLO Protection
TPS53127 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.
When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF
and output discharge is ON. The UVLO is non-latch protection.
8.3.11 Thermal Shutdown
The TPS53127 includes an over temperature protection shut-down feature. If the TPS53127 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
8.4 Device Functional Modes
The TPS53127 has two operating modes. The TPS53127 is in shut down mode when the EN1 and EN2 pins are
low. When the EN1 and EN2 pins is pulled high, the TPS53127 enters the normal operating mode.
12
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9 Application and Implementation
9.1 Application Information
9.2 Typical Application, QFN
The TPS53127 is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application.
Providing both a low core-type 1.05 V and I/O type 1.8 V output from a loosely regulated 12 V source. Idea
applications are: Digital TV Power Supply, Networking Home Pin, Digital Set-Top Box (STB), DVD
Player/Recorder, and Gaming Consoles.
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
R5
10kΩ
C6
10uF
Q3
FDS8878
L2
SPM6530T
1.5uH
VO2
1.05V/4A
VBST2
9
DRVH2
10
SW2
3
2
1
VFB1
VO1
VO2
EN2
8
4
SS1
5
GND
6
7
C5
0.1uF
SGND
R1
13.5kΩ
R2
10kΩ
VFB2
R4
3.63kΩ
PGND
EN1
24
VBST1 23
Power PAD
Q1
FDS8878
L1
SPM6530T
1.5uH
C2
0.1uF
DRVH1 22
TPS53127 RGE
SW1
21
L1
Q2
FDS8690
C3
10uF
VO1
1.8V/4A
(QFN )
PGND1 19
C4
22uFx2
PGND
TRIP1
PGND2
VIN
12
VREG5
DRVL1 20
V5FILT
DRVL2
SS2
11
TRIP2
Q4
FDS8690
13
14
15
16
17
18
R6
4.7kΩ
C7
4.7uF
C８
1uF
C1
22uFx2
R３
4.3kΩ
PGND
PGND
C11
4700pF
SGND
Figure 12. Typical Application Circuit
9.2.1 Design Requirements (QFN)
Table 1. Design Parameters
PARAMETERS
EXAMPLE VALUES
Input voltage
12 V
Output voltage
VO1 = 1.8 V, VO2 = 1.05 V
9.2.2 Detailed Design Procedure (QFN)
9.2.2.1 Choose Inductor
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 3 can be used to calculate L1.
L1 =
(VIN(MAX) - VO1) VO1
(VIN(MAX) - VO1)
¾ · ¾ = ¾
IL1(RIPPLE) · fSW VIN(MAX)
0.3 · IO1 · fSW
·
Vo1
¾
VIN(MAX)
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current.
The RMS and peak inductor current can be estimated as follows.
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VIN(MAX) - VO1
IL1(RIPPLE) = ¾
L1 · fSW
·
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Vo1
¾
VIN(MAX)
(4)
VTRIP
¾
IL1(PEAK) = R
+ IL1(RIPPLE)
DS(ON)
¾
2
1 (I
IL1(RMS) = IO 12 + ¾
)
12 L1(RIPPLE)
(5)
Ö
(6)
Note: The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.
9.2.2.2 Choose Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it is
recommended to use a ceramic output capacitor.
IL1(RIPPLE)
C1 = ¾
8 · VO1(RIPPLE)
·
1
¾
fSW
(7)
2
D Iload · L1
C1 = ¾
2 · VO1 · DVOS
(8)
2
load ·
L1
DI
C1 = ¾
2 · K · DVUS
(9)
Where
Ton1
K = (VIN - VO 1) · ¾
Ton1 + Tmin(off)
(10)
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and
Equation 9. The capacitance for C1 should be greater than 66 μF.
Where
• ΔVOS = The allowable amount of overshoot voltage in load transition.
• ΔVUS = The allowable amount of undershoot voltage in load transition.
• tmin(off) = Minimum off time
9.2.2.3 Choose Input Capacitor
The TPS53127 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
9.2.2.4 Choose Bootstrap Capacitor
The TPS53127 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side
drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater
than 10 V.
9.2.2.5 Choose VREG5 and V5FILT Capacitor
The TPS53127 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF highquality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of
these capacitors’ voltage ratings should be greater than 10 V.
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9.2.2.6 Choose Output Voltage Set Point Resistors
The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is recommended
to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 or
Equation 12 to calculate R1.
Vswinj = (VIN - VO1 · 0.5875) ·
R1 =
( )( )
1
¾
fSW
(
VO1
¾
VIN
·
)
VO 1
-1
¾
VFB(RIPPLE) + Vswinj
VFB + ¾
2
·
·
10127
(11)
R2
(12)
Where
VFB(RIPPLE) = Ripple voltage at VFB
Vswinj = Ripple voltage at error comparator
9.2.2.7 Choose Over Current Set Point Resistor
VTRIP =
(
)
(VIN - VO) VO
·¾
IOCL - ¾
2 · L1 · fSW VIN
·
RDS(ON)
(13)
VTRIP (mV) - VOCLoff
RTRIP (kW) = ¾
ITRIP(min) (mA)
(14)
Where:
• RDS(ON) = Low side FET on-resistance
• ITRIP(min) = TRIP pin source current （8.5 μA）
• VOCL0ff = Minimum over current limit offset voltage (–20 mV)
• IOCL = Over current limit
9.2.2.8 Choose Soft Start Capacitor
Soft start time equation is as follows.
TSS · ISSC
CSS = ¾
VFB
(15)
800
800
700
700
fSW - Switching Frequency - kHz
fSW - Switching Frequency - kHz
9.2.3 Application Curves (QFN)
600
500
400
300
200
600
500
400
300
200
100
100
VO2 = 1.05 V
VO1 = 1.8 V
0
0.0
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IO - Output Current - A
IO - Output Current - A
Figure 13. Switching Frequency (VIN = 12 V) vs Output
current (CH1)
Figure 14. Switching Frequency (VIN = 12 V) vs Output
Current (CH2)
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1.850
1.100
1.840
1.090
1.830
1.080
VOUT - Output Voltage - V
VOUT - Output Voltage - V
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1.820
1.810
1.800
1.790
1.070
1.060
1.050
1.040
1.030
1.780
1.020
1.770
1.010
1.760
VO2 = 1.05 V
1.000
VO1 = 1.8 V
0.0
1.750
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.5
1.0
4.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT - Output Current - A
IOUT - Output Current - A
Figure 16. Output Voltage (VIN = 12 V) vs Output Current
(CH2)
1.850
1.100
1.840
1.090
1.830
1.080
VOUT - Output Voltage - V
VOUT - Output Voltage - V
Figure 15. Output Voltage (VIN = 12 V) vs Output Current
(CH1)
1.820
1.810
1.800
1.790
1.780
1.070
1.060
1.050
1.040
1.030
1.020
1.770
1.010
1.760
VO1 = 1.8 V
VO2 = 1.05 V
1.000
1.750
0
0
5
10
15
20
25
5
10
15
20
25
VIN - Input Voltage - V
VIN - Input Voltage - V
Figure 17. Output Voltage (VIN = 12 V) vs Input Voltage
(CH1)
Figure 18. Output Voltage (VIN = 12 V) vs Input Voltage
(CH2)
VO1 = 1.8 V (50mv/div)
VO2 = 1.05 V (50mv/div)
Iout1 (2A/div)
Iout2 (2A/div)
Figure 19. Load Transient Response
16
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Figure 20. Load Transient Response
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EN1 (5V/div)
EN2 (5V/div)
SS1 (0.2V/div)
SS2 (0.2V/div)
VO1 = 1.8 V (0.5V/div)
VO2 = 1.05 V (0.5V/div)
Figure 22. Start-Up Waveforms
100
100
80
80
Efficiency - %
Efficiency - %
Figure 21. Start-Up Waveforms
60
40
60
40
20
20
VO1 = 1.8 V
VO2 = 1.05 V
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT - Output Current - A
IOUT - Output Current - A
Figure 23. 1.8 V Efficiency vs Output Current (CH1)
Figure 24. 1.05 V Efficiency vs Output Current (CH2)
VO1 (20mv/div)
VO2 (20mv/div)
VO1 = 1.8 V
VO2 = 1.05 V
Figure 25. 1.8-V Output Ripple Voltage
Figure 26. 1.05-V Output Ripple Voltage
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9.3 Typical Application Circuit, TSSOP
The TPS53127is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application.
Providing both a low core-type 1.05 V and I/O type 1.8V output from a loosely regulated 12 V source.
C2
0.1uF
R1
13.5k
Ω
R2
10kΩ
R5
10kΩ
C10
SGND4700pF
R4
3.63kΩ
1
DRVH1
2
VBST1
3
EN1
PGND1
22
4
VO1
TRIP1
21
5
VFB1
VIN
20
SW1
TSSOP24
C3
10uF
VO1
1.8V/4A
24
Q2
FDS8690
DRVL1 23
TPS53127PW
Q1
FDS8878
L1
SPM6530T
1.5uH
C1
22uFx2
R３
4.3kΩ
PGND
Input Voltage
VREG5 19
6
GND
7
SS1
8
VFB2
9
VO2
TRIP2 16
10
EN2
PGND2 15
11
VBST2
DRVL2
14
12
DRVH2
SW2
13
V5FILT 18
SS2
17
C7
4.7uF
4.5V to 24V
C9
10uF
C８
1uF
PGND
C11
4700pF
R6
4.7kΩ
SGND
PGND
Q4
FDS8690
C5
0.1uF
C4
22uFx2
L2
SPM6530T
1.5uH
Q3
FDS8878
C6
10uF
VO2
1.05V/4A
Figure 27. Typical Application Circuit
9.3.1 Design Requirements
For the Design Requirements, refer to Design Requirements (QFN).
9.3.2 Detailed Design Procedure
For the Detailed Design Procedure, refer to Detailed Design Procedure (QFN).
9.3.3 Application Curves
For the Application Curves, refer to Application Curves (QFN).
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10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 24 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS53127 device
additional 0.1 µF ceramic capacitance may be required in addition to the ceramic bypass capacitors, 10 µF.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
Keep the input switching current loop as small as possible. (VIN ≥ C3 ≥ PNGD ≥ Sync FET ≥ SW ≥ Control
FET)
Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as
small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal (FBx) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.(1)
Do not allow switching current to flow under the device.
DRVH and DRVL line should not run close to SW node or minimize it. (2)
GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected
to SGND. (3)
GND terminals for capacitors of VREG5 and VIN should be connected to PGND. (4)
Signal lines should not run under/near Output Inductor or minimize it. (5)
11.2 Layout Example
Reference designators shown correspond to the schematic of Figure 28.
VIN
Q3
Q1
SW2
SW1
C3
C6
Q4
Q2
(4)
C9
(5)
(5)
L2
L1
(3) R6 C11 C8
R3
(3)
C7
TRIP2
SS2
V5FILT
C4, 1
16
17
18
VREG5
15
TRIP1
14
VIN
13
12 PGND2
PGND1 19
C1, 1
DRVL1 20
11 DRVL2
(QFN )
10 SW2
9 DRVH2
C5
DRVH1 22
RGE
Thermal PAD
8 VBST2
C4, 2
SW1 21
TPS53127
4
3
2
C10
R4
VO1
5
VFB1
SS1
6
GND
VFB2
VOUT2
C1, 2
EN1 24
VO2
TO EN 2
C2
VBST1 23
7 EN2
TO EN 1
R2
R5
VOUT1
1
R1
(3)
PGND
(1)
Top Side Component or Via
Bottom Side Component
Top Side Etch
Bottom Side Etch
Component Pads Shown in White
SGND
Figure 28. Board Layout
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12 Device and Documentation Support
12.1 Trademarks
D-CAP2 is a trademark of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53127PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS53127
TPS53127PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS53127
TPS53127RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53127
TPS53127RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
53127
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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