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TPS53316
SLUSAP5A – DECEMBER 2011 – REVISED NOVEMBER 2016
TPS53316 High-Efficiency, 5-A Step-Down Regulator With Integrated Switcher
1 Features
3 Description
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The TPS53316 device provides a fully integrated 3.3V or 5-V input, synchronous buck converter with 16
total components, in 200 mm2 of PCB area. Due to
low RDS(on) and TI proprietary SmoothPWM skip
mode of operation, it enables 96% peak efficiency,
and over 90% efficiency at load as light as 100 mA. It
requires only two 22-µF ceramic output capacitors for
a power-dense, 5-A solution.
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96% Maximum Efficiency
Continuous 5-A Output Current Capability
Support all MLCC Output Capacitor
SmoothPWM™ Auto-Skip Eco-Mode™ for LightLoad Efficiency
Voltage Mode Control
Single Rail Input
Selectable Frequency
Selectable OCP Threshold
Selectable Soft-Start Time
2.9-V to 6-V Input Voltage Range
Adjustable Output Voltage Ranging from 0.6 V up
to 0.8 × VIN
Soft-Stop Output Discharge During Disable
Overcurrent, Overvoltage, and Overtemperature
Protection
Open-Drain Power Good Indication
Internal Bootstrap Switch
Supports Prebias Start-Up Functionality
Small 3 mm × 3 mm, 16-Pin, QFN Package
Low RDS(on), 22-mΩ With 3.3-V Input and 18-mΩ
With 5-V Input
TPS53316 features 750-kHz, 1.1-MHz, and 2-MHz
switching frequency selections, prebias start-up,
selectable internal softstart, output soft discharge,
internal VBST switch, power good, EN/Input UVLO,
overcurrent,
overvoltage,
undervoltage,
and
overtemperature protections and all ceramic output
capacitor support. It supports input voltages from
2.9 V to 6 V, and no extra bias voltage is needed.
The output voltage is adjustable from 0.6 V up to
0.8 × VIN.
TPS53316 is available in the 3 mm × 3 mm, 16-pin
QFN package (Green RoHs compliant and Pb free)
and is specified from –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS53316
PACKAGE
BODY SIZE (NOM)
QFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
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•
Low-Voltage Applications for 5-V Step-Down Rails
Low-Voltage Applications for 3.3-V Step-Down
Rails
Typical Application Circuit
2.9 V to 6 V
Output All MLCCs
VREG3
VIN
CBST
SW
VIN
VBST
AGND
TPS53316
EN
EN
RF/OC
PS
PowerPad
PGD
PGD
FB
COMP
UDG-11233
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53316
SLUSAP5A – DECEMBER 2011 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2011) to Revision A
Page
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Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
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Deleted Lead temperature, 1.6 mm (1/16 inch) from case for 10 seconds: 300°C maximum ............................................... 4
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Changed R8 value in the Typical 3.3-V Input Application Circuit Diagram From: 5.76 kΩ To: 57.6 kW ............................. 18
2
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53316
TPS53316
www.ti.com
SLUSAP5A – DECEMBER 2011 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
EN
1
RF/OC
2
PGND
PGND
VIN
VIN
16
15
14
13
RGT Package
16-Pin QFN
Top View
12
VREG3
11
AGND
PowerPad
PS
SW
SW
SW
FB
COMP
8
9
7
10
4
6
3
5
PGD
VBST
Not to scale
Pin Functions
PIN
NO.
1
NAME
EN
TYPE (1)
DESCRIPTION
I
Enable pin. Internally pulled-up to the VIN pin through a 2-MΩ resistor. The EN voltage must be less
than (VIN + 0.5 V).
2
RF/OC
I
Switching frequency and OC level configuration pin:
Connecting to ground: 1.1 MHz, 6.5-A OCP
Pulled high or floating (internal pulled high): 1.1 MHz, 4.5-A OCP
Connect with 24.3 kΩ to GND: 750 kHz, 4.5-A OCP
Connect with 57.6 kΩ to GND: 750 kHz, 6.5-A OCP
Connect with 105 kΩ to GND: 2 MHz, 4.5-A OCP
Connect with 174 kΩ to GND: 2 MHz, 6. 5-A OCP
3
PGD
O
Power good output flag. Open-drain output. Pull up to an external rail through a resistor.
4
VBST
P
Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW
terminal.
5
SW
B
Output inductor connection to integrated power devices
6
SW
B
Output inductor connection to integrated power devices
7
SW
B
Output inductor connection to integrated power devices
8
PS
I
Mode configuration pin (with10-µA current):
Connecting to ground: Forced CCM with 4x softstart time
Pulled high or floating (internal pulled high): Forced CCM master
Connect with 24.3 kΩ to GND: HEF mode with 4x softstart time
Connect with 57.6 kΩ to GND: HEFF mode
Connect with 105 kΩ to GND: DE mode
Connect with 174 kΩ to GND: DE mode with 4x softstart time
9
COMP
O
Error amplifier compensation terminal. Type III compensation method is generally recommended for
stability.
10
FB
I
Voltage feedback pin. Use for OVP, UVP, and PGD determination.
11
AGND
G
Device analog ground terminal
12
VREG3
O
3.3-V LDO output, serves as supply voltage for internal analog circuitry. The EN pin controls the turnon
function of the LDO.
13
VIN
P
Gate driver supply and power conversion input voltage. The input range is from 2.9 V to 6 V.
14
VIN
P
Gate driver supply and power conversion input voltage. The input range is from 2.9 V to 6 V.
15
PGND
P
Device power ground terminal
16
PGND
P
Device power ground terminal
—
PowerPad
—
Thermal pad of the device. Use 4 or 5 vias to connect to GND plane for heat dissipation.
(1)
B = Bidirectional, G = Ground, I = Input, O = Output, P = Supply
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS53316
3
TPS53316
SLUSAP5A – DECEMBER 2011 – REVISED NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
VIN
–0.3
7
VBST
–0.3
17
VBST (with respect to LL)
–0.3
7
EN
–0.3
7
–0.3
3.7
FB, PS, RF/OC
SW
Output voltage
UNIT
V
DC
–1
7
Pulse < 20 ns, E = 5 µJ
≥–5