TPS53627RSMT

Order Now Product Folder Technical Documents Support & Community Tools & Software TPS53627 SLUSCX9 – MARCH 2017 TPS53627 2-Phase, D-CAP+™ Step-Down Controller for VR13 CPU VCORE and DDR Memory 1 Features • • • • • • • • 1 • • • • • • • • • 3 Description ® Intel VR13 Serial VID (SVID) Compliant 1- or 2-Phase Operation Supports Both Droop and Non-Droop Applications 8-Bit DAC with 10-mV Step 4.5-V to 28-V Conversion Voltage Range Output Range: 0.5 V to 2.3 V Optimized Efficiency at Light and Heavy Loads 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR) Driverless Configuration for Efficient HighFrequency Switching Supports Discrete, Power Block, Power Stage™ or DrMOS MOSFET Implementations Accurate, Adjustable Voltage Positioning 300-kHz to 1-MHz Frequency Selections Patented AutoBalance™ Phase Balancing Programmable ON-Pulse Extension for Load Transient Boost Programmable Auto DCM and CCM Operation Selectable 8-level Current Limit Small, 4 mm × 4 mm, 32-Pin, VQFN PowerPad™ Package The TPS53627 device is a driverless, VR13 SVID compliant, synchronous buck controller. Advanced control features such as D-CAP+ ™architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) to provide fast transient response, lowest output capacitance and high efficiency. The device also supports singlephase operation in CCM and DCM operation for lightload efficiency boost. The device integrates a full set of VR13 I/O features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 00h to 07h. Adjustable control of VOUT slew rate can be programmed as high as 20mV/uS. Paired with the TI NexFET™ Power Stage, this total solution delivers exceptionally high speed and low switching loss. The TPS53627 device package is a space saving, thermally enhanced 32-pin VQFN package that operates from –40°C to +105°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS53627 VQFN (32) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the document. 2 Applications • • VDDQ for DDR Memory SoC Processor VCORE Power .. Simplified Schematic PWM1 SKIP CSD9537x Power Stage Microprocessor (µP) CSP1 CSN1 SVID PWM2 CSD9537x Power Stage CSP2 TPS53627 CSN2 Pin Strapping Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS53627 SLUSCX9 – MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device and Documentation Support.................... 5.2 5.3 5.4 5.5 5.6 1 1 1 2 3 6 5.1 Documentation Support ............................................ 3 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 3 3 3 3 3 Mechanical, Packaging, and Orderable Information ............................................................. 3 4 Revision History 2 DATE REVISION NOTES March 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated TPS53627 www.ti.com SLUSCX9 – MARCH 2017 5 Device and Documentation Support 5.1 Documentation Support 5.1.1 Related Documentation For related documentation see the following: TPS51604 Data Sheet 5.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 5.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 5.4 Trademarks Power Stage, AutoBalance, PowerPad, D-CAP+, NexFET, E2E are trademarks of Texas Instruments. Intel is a registered trademark of Intel Corporation. All other trademarks are the property of their respective owners. 5.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 5.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 6 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 3 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS53627RSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 TPS 53627 TPS53627RSMT ACTIVE VQFN RSM 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 TPS 53627 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of