TPS54062DGKR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 TPS54062 4.7-V to 60-V Input, 50-mA Synchronous Step-Down Converter With Low IQ 1 Features 3 Description • • • The TPS54062 device is a 60-V, 50-mA, synchronous step-down converter with integrated high-side and low-side MOSFETs. Current mode control provides simple external compensation and flexible component selection. The non-switching supply current is 89 µA. Using the enable pin, shutdown supply current is reduced to 1.7 µA. 1 • • • • • • • • Integrated High-Side and Low-Side MOSFET Peak Current Mode Control Diode Emulation for Improved Light-Load Efficiency 89 µA (typical) Operating Quiescent Current 100-kHz to 400-kHz Adjustable Switching Frequency Synchronizes to External Clock Internal Slow-Start 0.8 V ±2% Voltage Reference Stable with Ceramic Output Capacitors or LowCost Aluminum Electrolytic Cycle-by-Cycle Current Limit, Thermal and Frequency Foldback Protection MSOP-8 and 3mm × 3mm VSON-8 Packages Undervoltage lockout is internally set at 4.5 V, but can be increased using the accurate enable pin threshold. The output voltage start-up ramp is controlled by the internal slow-start time. Adjustable switching frequency range allows efficiency and external component size to be optimized. Frequency foldback and thermal shutdown protects the part during an overload condition. Device Information(1) PART NUMBER 2 Applications • • • • TPS54062 Low-Power Standby or Bias Voltage Supplies 4-20 mA Current-Loop Powered Sensors Industrial Process Control, Metering, and Security Systems High Voltage Linear Regulator Replacement PACKAGE MSOP (8) VSON (8) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. SPACER SPACER Simplified Schematic Efficiency 100 90 VIN = 10 V Efficiency (%) 80 70 60 50 40 30 20 Copyright © 2016, Texas Instruments Incorporated 10 0 0.001 VO = 5 V, fsw = 100 kHz, EN Floating VO = 3.3 V, fsw = 400 kHz 0.01 Output Current (A) 0.05 G000 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 16 8 Applications and Implementation ...................... 17 8.1 Application Information............................................ 17 8.2 Typical Applications ................................................ 17 9 Power Supply Recommendations...................... 31 10 Layout................................................................... 31 10.1 Layout Guidelines ................................................. 31 10.2 Layout Example .................................................... 31 11 Device and Documentation Support ................. 32 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History Changes from Revision C (December 2014) to Revision D • Added text to the Layout Guidelines section " All sensitive analog traces and components..."........................................... 31 Changes from Revision B (August 2012) to Revision C • Page Page Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1 Changes from Revision A (October 2011) to Revision B Page • Added features Item: Diode Emulation for Improved Light-Load Efficiency........................................................................... 1 • Changed Features Item From: 100 kHz to 400 kHz Switching Frequency To: 100 kHz to 400 kHz Adjustable Switching Frequency .............................................................................................................................................................. 1 • Changed the Efficiency Graph................................................................................................................................................ 1 • Changed VSON-8 package graphic to clarify ThermalPAD area........................................................................................... 4 • Changed the EN pin MAX value From: 5 V To: 8 V............................................................................................................... 5 • Changed the Enable and Adjusting Undervoltage Lockout section ..................................................................................... 13 • Changed Equation 22 through Equation 25 ......................................................................................................................... 21 2 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Changes from Original (May 2011) to Revision A Page • Changed Features Item From: MSOP8 and WSON8 Packages To: MSOP-8 and 3 mm x 3 mm VSON-8 Packages......... 1 • Changed the Efficiency Graph................................................................................................................................................ 1 • Added the VSON (DRB-8 Pin) Package ................................................................................................................................ 4 • Changed the RT/CLK pin Description .................................................................................................................................... 4 • Added VSON-8 Pins values to the Thermal Information table ............................................................................................... 6 • Changed the PLL lock in time Unit of Measure From: µA To: µs........................................................................................... 7 • Changed Equation 22........................................................................................................................................................... 21 • Changed the Efficiency vs Output Current Graphs, Figure 21 and Figure 22 ..................................................................... 22 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 3 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com 5 Pin Configuration and Functions MSOP PACKAGE 8 PINS TOP VIEW BOOT 1 8 PH VIN 2 7 GND EN 3 6 COMP RT/CLK 4 5 VSENSE VSON PACKAGE 8 PINS BOTTOM VIEW PH 8 Thermal Pad (9) GND 7 COMP 6 VSENSE 5 See appended Mechanical Data for size and shape 1 BOOT 2 VIN 3 EN 4 RT/CLK Pin Functions PIN NAME NUMBER BOOT 1 VIN 2 EN I/O O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. I Input supply voltage, 4.7 V to 60 V. I Enable pin, internal pull-up current source. Pull below 1.14 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors, see the Enable and Adjusting Undervoltage Lockout section. I Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor frequency programming. 3 RT/CLK 4 VSENSE 5 DESCRIPTION I Inverting input of the transconductance (gm) error amplifier. O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. COMP 6 GND 7 – Ground PH 8 O The source of the internal high-side power MOSFET and drain of the internal low side MOSFET – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. VSON-8 package only. Thermal Pad 4 9 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage MIN MAX UNIT VIN –0.3 62 V EN –0.3 8 V BOOT-PH –0.3 8 V VSENSE –0.3 6 V COMP –0.3 3 V PH –0.6 62 V –2 62 V –0.3 6 V EN 100 µA BOOT 100 mA VSENSE 10 µA COMP 100 µA PH, 10ns Transient RT/CLK VIN Current Internally Limited PH A Internally Limited RT/CLK A 200 µA Operating junction temperature –40 125 ºC Storage temperature, Tsg –65 150 °C (1) The Absolute Maximum Ratings specified in this section will apply to all specifications of this document unless otherwise noted. These specifications will be interpreted as the conditions which may damage the device with a single occurrence. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Input coltage MIN MAX 4.7 60 V 50 mA Output current UNIT Switching frequency set by RT/CLK resistor 100 400 kHz Switching frequency synchronized to external clock 300 400 kHz Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 5 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com 6.4 Thermal Information TPS54062 THERMAL METRIC (1) MSOP VSON 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 127.1 40.2 RθJC(top) Junction-to-case (top) thermal resistance 33.4 49.7 RθJB Junction-to-board thermal resistance 80 15.7 ψJT Junction-to-top characterization parameter 1 0.6 ψJB Junction-to-board characterization parameter 79 15.9 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.1 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics (1) TJ = –40°C to 125°C, VIN = 4.7 to 60 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Operating input voltage VIN Shutdown supply current EN = 0 V 4.7 1.7 60 V Iq Operating – Non-switching VSENSE = 0.9 V, VIN = 12 V 89 110 µA 1.24 1.4 V µA ENABLE AND UVLO (EN PIN) Enable threshold Input current Rising Falling 1 1.14 V Enable threshold +50 mV –4.7 µA Enable threshold –50 mV –1.2 µA Hysteresis 3.5 µA Enable to start switching time 450 µs 4.53 V VIN VIN start voltage VIN rising VOLTAGE REFERENCE Voltage reference 1mA < IOUT < Minimum Current Limit 0.784 0.8 0.816 V BOOT-PH = 5.7 V 1.5 2.8 Ω VIN = 12 V 0.8 1.5 Ω Input Current VSENSE pin 20 nA Error amp gm –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V 102 µS EA gm during slow-start –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, VSENSE = 0.4 V Error amp DC gain VSENSE = 0.8 V HIGH-SIDE MOSFET Switch resistance LOW-SIDE MOSFET Switch resistance ERROR AMPLIFIER Min unity gain bandwidth Error amp source/sink V(COMP) = 1 V, 100-mV Overdrive 26 µS 1000 V/V 0.5 MHz ±8 µA Start Switching Threshold 0.57 V COMP to Iswitch gm 0.65 A/V 134 mA –0.7 mA CURRENT LIMIT High-side sourcing current limit threshold VIN = 12V, BOOT-PH = 5.7 V Zero cross detect current (1) 6 75 The Electrical Ratings specified in this section will apply to all specifications in this document unless otherwise noted. These specifications will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the life of the product containing it. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Electrical Characteristics(1) (continued) TJ = –40°C to 125°C, VIN = 4.7 to 60 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN Thermal shutdown 146 C RT/CLK Operating frequency using RT mode Switching frequency 100 R(RT/CLK) = 510 kΩ 192 Minimum CLK pulse width RT/CLK voltage R(RT/CLK) = 510 kΩ 240 400 kHz 288 kHz 40 ns 0.53 V RT/CLK high threshold 1.3 RT/CLK low threshold 0.5 RT/CLK falling edge to PH rising edge delay Measure at 240 kHz with RT resistor in series PLL lock in time Measure at 240 kHz PLL frequency range V V 100 200 ns 400 kHz 100 300 µs PH Minimum On-time Measured at 50% to 50% of VIN IOUT = 50 mA 120 ns Dead time VIN = 12V, IOUT = 50 mA, One transition 30 ns VIN = 12 V 5.7 V 2.9 V 4.1 ms BOOT BOOT-PH regulation voltage BOOT-PH UVLO INTERNAL SLOW-START TIME Slow-start time fSW = 240 kHz, RT = 510 kΩ, 10% to 90% Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 7 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com 6.6 Typical Characteristics 3.0 1.6 VIN = 4.7V VIN = 12V VIN = 60V 1.2 Resistance (Ω) Resistance (Ω) 2.5 VIN = 4.7V VIN = 12V VIN = 60V 1.4 2.0 1.5 1.0 0.8 0.6 0.4 1.0 0.2 0.5 −50 −25 0 25 50 Temperature (°C) 75 100 0.0 −50 125 −25 Figure 1. High-Side RDS(on) vs Temperature 87.5 0.804 75.0 % of Normal Fsw Voltage Reference (V) 0.806 0.802 0.800 0.798 G002 50.0 37.5 25.0 0.794 12.5 −25 0 25 50 Temperature (°C) 75 100 0.0 125 VIN = 12V 0 100 200 G003 300 400 500 600 Feedback Voltage (mV) 700 800 900 G005 Figure 4. Frequency vs VSENSE Voltage 280 400 VIN = 12V RT = 510kΩ VIN = 12V 350 Oscillator Frequency (kHz) Oscillator Frequency (kHz) 125 VSENSE Rising VSENSE Falling Figure 3. VREF Voltage vs Temperature 260 250 240 230 220 210 300 250 200 150 100 50 −25 0 25 50 Temperature (°C) 75 100 125 0 300 G004 Figure 5. Frequency vs Temperature 8 100 62.5 0.796 200 −50 75 100.0 VIN = 12V 270 25 50 Temperature (°C) Figure 2. Low-Side RDS(on) vs Temperature 0.808 0.792 −50 0 G001 425 550 675 800 925 1050 Timing Resistance (kΩ) 1175 1300 G006 Figure 6. Frequency vs RT/CLK Resistance Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Characteristics (continued) 1.26 140 120 1.24 100 1.22 Enable Voltage (V) Transconductance (µS) VIN = 12V 80 60 40 VIN = 12V 1.20 1.16 1.14 20 0 −50 −25 0 25 50 Temperature (°C) 75 100 1.12 −50 125 −25 0 25 50 75 Junction Temperature (°C) G007 100 125 G013 Figure 8. Enable Pin Voltage vs Temperature Figure 7. Error Amp Transconductance vs Temperature −3.20 4.50 VIN = 12V −3.25 4.45 −3.30 4.40 Input Voltage (V) Enable Hysteresis Current (µA) VENA Rising VENA Falling 1.18 −3.35 −3.40 −3.45 4.30 4.25 4.20 −3.50 4.15 −3.55 4.10 −3.60 −50 −25 0 25 50 75 Junction Temperature (°C) 100 UVLO Start UVLO Stop 4.35 4.05 −50 125 −25 0 25 50 75 Junction Temperature (°C) G015 Figure 9. Enable Pin Hysteresis Current vs Temperature 100 125 G012 Figure 10. Input Voltage (UVLO) vs Temperature 3.0 0.0 −0.2 2.5 Shutdown Current (µA) Enable Current (µA) −0.4 −0.6 −0.8 −1.0 −1.2 −1.4 −1.6 2.0 1.5 1.0 TJ = 125°C TJ = 25°C TJ = −40°C 0.5 −1.8 −2.0 0 5 10 15 20 25 30 35 40 Input Voltage (V) 45 50 55 60 0.0 0 G016 Figure 11. Enable Pin Pullup Current vs Input Voltage 5 10 15 20 25 30 35 40 Input Voltage (V) 45 50 55 60 G009 Figure 12. Shutdown Supply Current (VIN) vs Input Voltage Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 9 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Characteristics (continued) 98 2.50 Non−Switching TJ = 125°C TJ = 25°C TJ = −40°C 2.25 96 Supply Current (µA) Supply Current (µA) 2.00 94 92 90 88 TJ = 125°C TJ = −40°C TJ = 25°C 86 84 0 5 10 15 20 25 30 35 40 Input Voltage (V) 45 50 55 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 60 0 Figure 13. Supply Current (VIN pin) vs Input Voltage 2 3 Input Voltage (V) 4 5 G011 Figure 14. Supply Current (VIN pin) vs Input Voltage (0V to VSTART) EN Pin Low 140 4.21 TJ = 125°C TJ = 25°C TJ = −40°C 120 FSW = 240KHz 4.20 4.19 100 SS Time (ms) Supply Current (µA) 1 G008 80 60 40 4.18 4.17 4.16 4.15 4.14 20 0 4.13 0 1 2 3 Input Voltage (V) 4 4.12 −50 5 −25 0 25 50 75 Junction Temperature (°C) G010 Figure 15. Supply Current (VIN pin) vs Input Voltage (0V to VSTART) EN Pin Open 100 125 G025 Figure 16. Slow-Start Time vs Temperature Current Limit Threshold (mA) 170 160 150 140 130 120 TJ = −40°C TJ = 25°C TJ = 125°C 110 100 0 5 10 15 20 25 30 35 40 Input Voltage (V) 45 50 55 60 G018 Figure 17. Current Limit vs Input Voltage 10 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 7 Detailed Description 7.1 Overview The TPS54062 device is a 60-V, 50-mA, step-down (buck) regulator with an integrated high-side and low-side nchannel MOSFET. To improve performance during line and load transients the device implements a constantfrequency, current mode control, which reduces output capacitance and simplifies external frequency compensation design. The switching frequency of 100 kHz to 400 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor-to-ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS54062 has a default start-up voltage of approximately 4.5 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating the device will operate. The operating current is 89 µA when not switching and under no load. When the device is disabled, the supply current is 1.7 µA. The integrated 1.5-Ω high-side MOSFET and 0.8-Ω low-side MOSFET allows for high efficiency power supply designs capable of delivering 50-mA of continuous current to a load. The TPS54062 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54062 can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference. The TPS54062 has an internal output OV protection that disables the high-side MOSFET if the output voltage is 109% of the nominal output voltage. The TPS54062 reduces external component count by integrating the slow-start time using a reference DAC system. The TPS54062 resets the slow-start times during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help control the inductor current. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 11 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com 7.2 Functional Block Diagram EN VIN Thermal Shutdown Enable Comparator UVLO Shutdown Shutdown Logic Enable Threshold VSENSE Boot Charge OV ERROR AMPLIFIER Boot UVLO Minimum Clamp Current Sense PWM Comparator BOOT Deadtime Control Logic Shutdown REFERENCE DAC Slope Compensation PH COMP Frequency Shift DRV REG Maximum Clamp ZX detect Oscillator with PLL GND RT /CLK Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Fixed-Frequency PWM Control The TPS54062 uses an adjustable fixed-frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. 7.3.2 Slope Compensation Output Current The TPS54062 adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations. 12 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Feature Description (continued) 7.3.3 Error Amplifier The TPS54062 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the internal slow-start voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 102 µS during normal operation. During the slow-start operation, the transconductance is a fraction of the normal operating gm. The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin-to-ground. 7.3.4 Voltage Reference The voltage reference system produces a precise ±2 voltage reference over temperature by scaling the output of a temperature stable band-gap circuit 7.3.5 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using 1% tolerance or better divider resistors. Start with a 10-kΩ for the RLS resistor and use the Equation 1 to calculate RHS. - 0.8 V ö æV RHS = RLS ´ ç OUT ÷÷ ç 0.8 V è ø (1) 7.3.6 Enable and Adjusting Undervoltage Lockout The TPS54062 is enabled when the VIN pin voltage rises above 4.53 V and the EN pin voltage exceeds the EN rising threshold of 1.24 V. The EN pin has an internal pullup current source, I1, of 1.2 µA that provides the default enabled condition when the EN pin floats. If an application requires a higher input undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 18 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.24 V, an additional 3.5 µA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.14 V, the 3.5-µA Ihys current is removed. This additional current facilitates adjustable input voltage hysteresis. Use Equation 2 to calculate RUVLO1 for the desired input start and stop voltages . Use Equation 3 to similarly calculate RUVLO2. In applications designed to start at relatively low input voltages (for example, from 4.7 V to 10 V) and withstand high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8 V during the high input voltage condition. TI recommends using a zener diode to clamp the pin voltage below the absolute maximum rating. VIN TPS54062 i1 ihys RUVLO1 EN Optional RUVLO2 VEN Copyright © 2016, Texas Instruments Incorporated Figure 18. Adjustable Undervoltage Lock Out Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 13 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Feature Description (continued) æV ö VSTART ç ENAFALLING ÷ - VSTOP è VENARISING ø RUVLO 1 = æ V ö I1 × ç 1- ENAFALLING ÷ + IHYS VENARISING ø è RUVLO 2 = VSTOP (2) RUVLO 1 ´ VENAFALLING - VENAFALLING + RUVLO 1 ´ (I1 + IHYS ) (3) 7.3.7 Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54062 is adjustable over a wide range from approximately 100 kHz to 400 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.53 V and must have a resistor-to-ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 4. To reduce the solution size, one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 130 ns and limits the maximum operating input voltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of the maximum switching frequency is located below. 116720 RT (kW) = fSW (kHz)0.9967 (4) 7.3.8 Selecting the Switching Frequency The TPS54062 implements current mode control which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high input voltages the TPS54062 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal start-up and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still have frequency shift protection. During shortcircuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on time and the output has a low voltage. During the switch on-time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off-time, the inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the ramp up amount. The frequency shift effectively increases the off time allowing the current to ramp down. æ 1 ö æ V OUT + R LS ´ I O + R DC ´ I O ö fSW (maxskip) = ç ÷ ´ ç ÷ è t ON ø è V IN - I O ´ R HS + I O ´ R LS ø (5) æ f div ö æ V OUTSC + R LS × I CL + R DC ´ I CL ö = ç ÷ × ç ÷ è t ON ø è V IN - I CL ´ R HS + I CL ´ R LS ø (6) f SW (shift) Where: IO = Output current ICL = Current Limit VIN = Input Voltage VOUT = Output Voltage VOUTSC Output Voltage during short RDC = Inductor resistance RHS = High-side MOSFET resistance RLS = Low-side MOSFET resistance 14 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Feature Description (continued) ton = Controllable on-time fdiv = Frequency divide (equals 1, 2, 4, or 8) 7.3.9 How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in Figure 19. The square wave amplitude must transition lower than 0.5 V and higher than 1.3 V on the RT/CLK pin and have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 400 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin-to-ground should the synchronization signal turn off. TI recommends using a frequency set resistor connected as shown in Figure 19 through another resistor-to-ground (for example, 50 Ω) for clock signal that are not Hi-Z or 3-state during the off-state. The sum of the resistance should set the switching frequency close to the external CLK frequency. TI recommends to AC couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK threshold, the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator, the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds. When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal start-up and fault conditions. TPS54062 TPS54062 RT/CLK RT/CLK PLL PLL RT Hi-Z Clock Source Clock Source RT Copyright © 2016, Texas Instruments Incorporated Figure 19. Synchronizing to a System Clock 7.3.10 Overvoltage Transient Protection The TPS54062 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low-value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low-value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 15 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Feature Description (continued) 7.3.11 Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 146°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 146°C, the device reinitiates the power-up sequence by restarting the internal slow-start. 7.4 Device Functional Modes 7.4.1 Operation Near Minimum Input Voltage The TPS54062 is recommended to operate with input voltages above 4.7 V. The typical VIN UVLO threshold is 4.53 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device will not switch. If EN is floating or externally pulled up to greater up than the typical 1.24-V rising threshold, when V(VIN) passes the UVLO threshold the TPS54062 will become active. Switching is enabled and the slow-start sequence is initiated. The TPS54062 starts linearly ramping up the internal reference DAC from 0 V to the reference voltage over the internal slow-start time period set by the switching frequency. 7.4.2 Operation With Enable Control The enable start threshold voltage is 1.24 V typical. With EN held below the 1.24-V typical rising threshold voltage the TPS54062 is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent current is reduced in this state. If the EN voltage is increased above the rising threshold voltage while V(VIN) is above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start sequence is initiated. The TPS54062 starts linearly ramping up the internal reference DAC from 0 V to the reference voltage over the internal slow-start time period set by the switching frequency. If EN is pulled below the 1.14-V typical falling threshold the TPS54062 will enter the reduced quiescent current state again. 16 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS54062 is a 60-V, 50-mA step-down regulator with an integrated high-side and low-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 50 mA. Example applications are: Low Power Standby or Bias Voltage Supplies, 4-20 mA CurrentLoop Powered Sensors, Industrial Process Control, Metering, and Security Systems or an efficient high voltage linear regulator replacement. Use the following design procedure to select component values for the TPS54062. This procedure illustrates the design of a high frequency switching regulator. These calculations can be done with the aid of the excel spreadsheet tool SLVC364. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. 8.2 Typical Applications 8.2.1 Continuous Conduction Mode (CCM) Switching Regulator + Copyright © 2016, Texas Instruments Incorporated Figure 20. Application Schematic 8.2.1.1 Design Requirements This example details the design of a continuous conduction mode (CCM) switching regulator design using ceramic output capacitors. If a low-output current design is needed, see DCM Application. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3 V Transient Response 0 to 50-mA load step ΔVOUT = 4% Maximum Output Current 50 mA Input Voltage 24 V nom. 8 V to 60 V Output Voltage Ripple 0.5% of VOUT Start Input Voltage (rising VIN) 7.88 V Stop Input Voltage (falling VIN) 6.66 V Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 17 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Selecting the Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high-switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage and the output voltage and the frequency shift limitation. Equation 5 and Equation 6 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse-skipping or the lack of overcurrent protection during a short circuit. The typical minimum on time, tonmin, is 130 ns for the TPS54062. For this example, the output voltage is 3.3 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 400 kHz when including the inductor resistance, on resistance and diode voltage in Equation 5 or Equation 6. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 6 to determine the maximum switching frequency. With a maximum input voltage of 60 V, inductor resistance of 3.7 Ω, high-side switch resistance of 2.3 Ω, low-side switch resistance of 1.1 Ω, a current limit value of 120 mA and a short circuit output voltage of 0.1 V. The maximum switching frequency is 400 kHz in both cases and a switching frequency of 400 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 4. The switching frequency is set by resistor R3 shown in Figure 20. R3 is calculated to be 298 kΩ. A standard value of 301 kΩ is used. 8.2.1.2.2 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 7. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. Typically, TI recommends using KIND values in the range of 0.2 to 0.4; however, for designs using low-ESR output capacitors such as ceramics and low output currents, a value as high as KIND = 1 may be used. In a wide-input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND = 0.8 and the minimum inductor value is calculated to be 195 µH. For this design, a near standard value was chosen: 220 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 9 and Equation 10. For this design, the RMS inductor current is 50 mA and the peak inductor current is 68 mA. The chosen inductor is a Coilcraft LPS4018-224ML. It has a saturation current rating of 235 mA and an RMS current rating of 200 mA. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. æ V max - VOUT ö VOUT LOmin ³ ç IN ÷ ´ Kind I V max ´ ´ fSW O IN è ø IRIPPLE ³ VOUT ´ - VOUT ) VINmax ´ LO ´ fSW IL rms = IO2 + 18 (VINmax (7) (8) æ VOUT ´ (VINmax - VOUT ) ö 1 ´ ç ÷÷ ç 12 VINmax ´ LO ´ fSW è ø 2 Submit Documentation Feedback (9) Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Applications (continued) IL peak = IOUT + IRIPPLE 2 (10) 8.2.1.2.3 Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance necessary to accomplish this. Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no load) to 50 mA (full load). For this example, ΔIOUT = 0.05-0 = 0.05 and ΔVOUT = 0.04 × 3.3 = 0.132. Using these numbers gives a minimum capacitance of 1.89 µF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The low-side FET of the regulator emulates a diode so it can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 26. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 13 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light-load, VF is the final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 50 mA to 0A. The output voltage will increase during this load transition and the stated maximum in our specification is 4% of the output voltage. This will make VF = 1.04 × 3.3 = 3.432 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 14 yields a minimum capacitance of 0.619 µF. Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. Equation 13 yields 0.671 µF. Equation 15 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 15 indicates the ESR should be less than 0.466 Ω. The most stringent criteria for the output capacitor is 1.89 µF of capacitance to keep the output voltage in regulation during an load transient. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which will increase this minimum value. For this example, 10-µF, 10V X5R ceramic capacitor with 0.003 Ω of ESR will be used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 11 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 11 yields 10.23 mA. ICOrms = æ VOUT ´ (VINmax - VOUT ) ö ´ ç ÷÷ ç VINmax ´ LO ´ fSW 12 è ø 1 (11) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 19 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) CO 1 ³ æ ö IRIPPLE 1 ´ ç ÷ VRIPPLE è 8 ´ fSW ø CO 2 ³ LO ´ (I 2 - IOL OH 2 2 (12) ) 2 VF - Vi (13) I 2 CO 3 ³ O DV fSW RC (14) V £ RIPPLE IRIPPLE (15) 8.2.1.2.4 Input capacitor The TPS54062 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1µF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a RMS current rating greater than the maximum RMS input current of the TPS54062. The input RMS current can be calculated using Equation 16. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 100-V voltage rating is required to support the maximum input voltage. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using rearranging Equation 17. Using the design example values, Ioutmax = 50 mA, CIN = 2.2 µF, ƒSW = 400 kHz, yields an input voltage ripple of 14.2 mV and a RMS input ripple current of 24.6 mA. ICINrms = IOUT ´ CIN ³ VOUT ´ VINmin (VINmin - VOUT ) VINMin æ 0.25 ö IO ´ ç ÷ VINripple è fSW ø (16) (17) 8.2.1.2.5 Bootstrap Capacitor Selection A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating. 8.2.1.2.6 Under Voltage Lock Out Set Point The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54062. The UVLO has two thresholds, one for power-up when the input voltage is rising and one for powerdown or brownouts when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.88 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.66 V (UVLO stop). The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 174-kΩ resistor between Vin and EN and a 31.6-kΩ resistor between EN and ground are required to produce the 7.88 and 6.66 volt start and stop voltages. 8.2.1.2.7 Output Voltage and Feedback Resistors Selection For the example design, 10-kΩ was selected for RLS. Using Equation 1, RHS is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. 20 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Applications (continued) 8.2.1.2.8 Closing the Loop There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the actual cross over frequency will usually be lower than the crossover frequency used in the calculations. This method assume the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro™ software for a more accurate design. To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 18 and Equation 19. For Cout, use a derated value of 8.9 µF. Use Equation 20 and Equation 21, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 271 Hz and fzero is 5960 kHz. Equation 20 is the geometric mean of the modulator pole and the ESR zero and Equation 21 is the mean of modulator pole and the switching frequency. Equation 20 yields 40.29 kHz and Equation 21 gives 7.36 kHz. Use a frequency near the lower value of Equation 20 or Equation 21 for an initial crossover frequency. For this example, fco is 7.8 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. To determine the compensation resistor, R4, use Equation 22. Assume the power stage transconductance, gmps, is 0.65 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 102 µS, respectively. R4 is calculated to be 27.1 kΩ, use the nearest standard value of 27.4 kΩ. Use Equation 23 to set the compensation zero to the modulator pole frequency. Equation 23 yields 0.0214 µF for compensating capacitor C5, a 0.022 µF is used on the board. Use the larger value of Equation 24 and Equation 25 to calculate the C6 value, to set the compensation pole. Equation 25yields 29 pF so the nearest standard of 27 pF is used. 1 f pole(Hz) = VO ´ CO ´ 2 ´ p IO (18) f zero(Hz) = 1 RC ´ CO ´ 2 ´ p (19) 0.5 f co1(Hz) = ( f zero ´ f pole) (20) 0.5 æ f sw ö f co2(Hz) = ç ´ f pole ÷ 2 è ø R4 = (21) 2 ´ p ´ fCO ´ CO VO ´ gmps VREF ´ gmea (22) 1 C5 = 2 ´ p ´ R4 ´ fPOLE (23) R ´ CO C6 = C R4 1 C6 = R4 ´ fSW ´ p (24) (25) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 21 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) 8.2.1.3 Application Curves 100 100 VOUT = 3.3V fSW = 400kHz 80 80 70 70 60 50 40 VIN = 10V VIN = 24V VIN = 36V VIN = 48V VIN = 60V 30 20 10 0 0 0.01 VOUT = 3.3V fSW = 400kHz 90 Efficiency (%) Efficiency (%) 90 0.02 0.03 Output Current (A) 0.04 60 50 40 VIN = 10V VIN = 24V VIN = 36V VIN = 48V VIN = 60V 30 20 10 0 0.001 0.05 10 100 1000 10000 Frequency (Hz) 100000 180 150 120 90 60 30 0 −30 −60 −90 −120 −150 −180 1000000 G041 0.10 Output Voltage Normalized (%) Gain Phase 0.1 Figure 22. Efficiency vs Output Current Phase (°) Gain (dB) Figure 21. Efficiency vs Output Current 60 50 40 30 20 10 0 −10 −20 −30 −40 −50 −60 0.01 Output Current (A) G040 IOUT = 25mA 0.08 0.06 0.04 0.02 0.00 −0.02 −0.04 −0.06 −0.08 −0.10 8 G031 Figure 23. Gain vs Phase 12 16 20 24 28 32 36 40 44 48 52 56 60 Input Voltage (V) G035 Figure 24. Output Voltage vs Input Voltage 0.20 Output Voltage Normalized (%) VIN = 24V 0.15 0.10 VOUT = 50 mV / div (ac coupled) 0.05 0.00 −0.05 −0.10 IOUT = 20 mA / div −0.15 −0.20 0 0.01 0.02 0.03 Output Current (A) 0.04 0.05 G033 Figure 25. Output Voltage vs Output Current 22 Submit Documentation Feedback Time = 1 msec / div Figure 26. Load Transient Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Applications (continued) VIN = 10 V / div VOUT = 100 mV / div (ac coupled) EN = 2 V / div VIN = 10 V / div VOUT = 2 V / div Time = 20 msec / div Time = 2 msec / div Figure 27. Line Transient Figure 28. Start-Up With ENA VIN = 10 mV / div (ac coupled) VIN = 10 V / div PH = 20 V / div EN = 2 V / div Inductor Current = 100 mA / div VOUT = 2 V / div Time = 2 µsec / div Time = 2 msec / div Figure 29. Start-Up With VIN Figure 30. Input Ripple in DCM VIN = 10 mV / div (ac coupled) VIN = 10 mV / div (ac coupled) PH = 20 V / div PH = 20 V / div Inductor Current = 100 mA / div Inductor Current = 100 mA / div Time = 2 µsec / div Time = 50 µsec / div Figure 31. Input Ripple in CCM Figure 32. Input Ripple Skip Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 23 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) VOUT = 10 mV / div (ac coupled) VOUT = 10 mV / div (ac coupled) PH = 20 V / div PH = 20 V / div Inductor Current = 100 mA / div Inductor Current = 100 mA / div Time = 2 µsec / div Time = 2 µsec / div Figure 33. Output Ripple in DCM Figure 34. Output Ripple in CCM VOUT = 10 mV / div (ac coupled) PH = 20 V / div Inductor Current = 100 mA / div Time = 50 µsec / div Figure 35. Output Ripple Skip 24 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Applications (continued) 8.2.2 DCM Application Copyright © 2016, Texas Instruments Incorporated Figure 36. DCM Application Schematic 8.2.2.1 Design Requirements This example details the design of a low output current, fixed switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3 V Transient Response 0 to 15 mA load-step ΔVOUT = 4% Maximum Output Current 10 mA Minimum Output Current 3 mA Input Voltage 24 V nom. 10 V to 40 V Output Voltage Ripple 0.5% of VOUT Switching Frequency 100 kHz Start Input Voltage (rising VIN) 9V Stop Input Voltage (falling VIN) 8V 8.2.2.2 Detailed Design Procedure It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output currents. A fixed frequency power supply will have a predictable output voltage ripple and noise. Using a traditional continuous conduction mode (CCM) design method to calculate the output inductor will yield a large inductance for a low output current supply. Using a CCM inductor will result in a large sized supply or will affect efficiency from the large DC resistance an alternative is to operate in discontinuous conduction mode (DCM). Use the procedure below to calculate the components values for designing a power supply operating in discontinuous conduction mode. The advantage of operating a power supply in DCM for low-output current is the fixed switching frequency, lower output inductance, and lower DC resistance on the inductor. Use the frequency shift and skip equations to estimate the maximum switching frequency. The TPS54062 is designed for applications which require a fixed operating frequency and low-output voltage ripple at low output currents, thus, the TPS54062 does not have a pulse skip mode at light loads. Since the device has a minimum controllable on-time, there is an output current at which the power supply will pulse skip. To ensure that the supply does not pulse skip at output current of the application, the inductor value will be need to be selected greater than a minimum value. The minimum inductance needed to maintain a fixed switching Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 25 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) frequency at the minimum load is calculated to be 0.9 mH using Equation 26. Since the equation is ideal and was derived without losses, assume the minimum controllable light-load on-time, tonminll, is 350 ns. To maintain DCM operation the inductor value and output current need to stay below a maximum value. The maximum inductance is calculated to be 1.42 mH using Equation 27. A 744062102 inductor from Wurth Elektronik is selected. If CCM operation is necessary, use the previous design procedure. Use Equation 28, to make sure the minimum current limit on the high-side power switch is not exceeded at the maximum output current. The peak current is calculated as 23.9 mA and is lower than the 134 mA current limit. To determine the RMS current for the inductor and output capacitor, it is necessary to calculate the duty cycle. The duty cycle, D1, for a step-down regulator in DCM is calculated in Equation 29. D1 is the portion of the switching cycle the high-side power switch is on, and is calculated to be 0.1153. D2 is the portion of the switching cycle the low-side power switch is on, and is calculated to be 0.7253. Using the Equation 31 and Equation 32, the RMS current of the inductor and output capacitor are calculated, to be 12.8 mA and 7.6 mA respectively. Select components that ratings exceed the calculated RMS values. Calculate the output capacitance using the Equation 33 to Equation 35 and use the largest value, VRIPPLE is the steady-state voltage ripple and ΔV is voltage change during a transient. A minimum of 1.5-µF capacitance is calculated. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 22-µF, 6.3-V X7R ceramic capacitor with 5-mΩ ESR is used. To have a low output ripple power supply use a low-ESR capacitor. Use Equation 36 to estimate the maximum esr for the output capacitor. Equation 37 and Equation 38 estimate the RMS current and capacitance for the input capacitor. An RMS current of 3.7 mA and capacitance of 0.2 µF is calculated. A 1-µF 100V/X7R ceramic is used for this example. æ V max - VO ö t Onmin2 æ VSmax ö LOmin ³ ç S x fSW ÷ ´ ç ÷ ´ VO IOmin è 2 ø è ø (26) æ VO ö 1 æ V min - VO ö LOmax £ ç S ÷ ´ ÷ ´ ç 2 V min f è ø SW ´ IO è S ø (27) æ 2 ´ VO ´ IOmax ´ (VSmax - VO ) ö IL peak = ç ÷÷ ç VSmax ´ LO ´ fSW è ø æ 2 ´ VO ´ IO ´ LO ´ fSW D1 = ç ç VS ´ (VS - VO ) è ö ÷÷ ø 0.5 (28) 0.5 (29) æ V - VO ö D2 = ç S ÷ ´ D1 VO è ø (30) æ D1 + D2 ö IL rms = IL peak ´ ç ÷ 3 è ø 0.5 (31) 2 æ æ D1 + D2 ö æ D1 + D2 ö ö ICOrms = IL peak ´ ç ç ÷ ç ÷ ÷÷ çè 3 4 ø è ø ø è 0.5 æ D1 + D2 ö I peak CO 1 £ L ´ ç ÷ VRIPPLE è 8 ´ fSW ø CO 2 ³ LO ´ (Io (VO 2 - 0 2 + DV ) 2 (33) ) - V O2 (34) I 1 CO 3 ³ O DV fCO RC 26 (32) (35) V £ RIPPLE IL peak (36) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Applications (continued) 2 æ æ D1 ö æ D1 ö ö ICINrms = IL peak ´ ç ç ç 4 ÷ ÷÷ ç è 3 ÷ø è ø ø è CIN ³ 0.5 (37) æ 0.25 ö IO ´ ç ÷ VINRIPPLE è fSW ø (38) 8.2.2.2.1 Closing the Feedback Loop The method presented here is easy to calculate and includes the effect of the slope compensation that is internal to the device. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Once the output components are determined, use the equations below to close the feedback loop. A current mode controlled power supply operating in DCM has a transfer function which has an ESR zero and pole as shown in Equation 39. To calculate the current mode power stage gain, first calculate, Kdcm, DCM gain, and Fm, modulator gain, in Equation 40 and Equation 41. Kdcm and Fm are 26.3 and 1.34 respectively. The location of the pole and ESR zero are calculated using Equation 42 and Equation 43 . The pole and zero are 67 Hz and 2 MHz, respectively. Use the lower value of Equation 44 and Equation 45 as a starting point for the crossover frequency. Equation 44 is the geometric mean of the power stage pole and the ESR zero and Equation 45 is the mean of power stage pole and the switching frequency. The crossover frequency is chosen as 2.5 kHz from Equation 45. To determine the compensation resistor, RCOMP, use Equation 46. Assume the power stage transconductance, gmps, is 0.65 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 102 µS, respectively. RCOMP is calculated to be 32.7 kΩ, use the nearest standard value of 32.4 kΩ. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 139 nF for compensating capacitor CCOMP, a 330 nF is used on the board. Use the larger value of Equation 48 or Equation 49 to calculate the CPOLE, to set the compensation pole. Equation 49 yields 98 pF so the nearest standard of 100 pF is used. s 1+ 2 ´ p ´ f ZERO Gdcm(s) » Fm ´ Kdcm ´ s 1+ 2 ´ p ´ fPOLE (39) Kdcm = VO ´ 2 ´ D1 (VS - VO ) æ ö ç ÷ Rdc ÷ - VO VS ´ ç 2 + VO ÷ ç ç IO ÷ø è gmps Fm = æ VS - VO ö ç ÷ + 0.277 è LO ´ fSW ø fPOLE (Hz) = f ZERO (Hz) = fCO1(Hz) = fCO2 (Hz) = 1 VO ´ CO IO (40) (41) VO ö æ ç2 - V ÷ S ÷ ´ ç VO ÷ ç ´ 2 ´ p ç1 - V ÷ S ø è (42) 1 RC ´ CO ´ 2 ´ p ( f ZERO ( fSW (43) 0.5 ´ fPOLE ) (44) 0.5 ´ fPOLE ) (45) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 27 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) fCO x Kdcm x Fm x fPOLE RCOMP = (46) 1 2 ´ p ´ RCOMP ´ Kdcm ´ Fm CCOMP = CPOLE1 VO VREF x gmea (47) R ´ CO = C RCOMP CPOLE2 = RCOMP (48) 1 ´ fSW ´ p (49) 8.2.2.3 Application Curves 100 100 VOUT =3.3V 90 80 80 70 70 Efficiency (%) Efficiency (%) 90 60 50 40 60 50 40 30 30 VIN = 10V VIN = 24V VIN = 40V 20 10 0 0 10 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 Output Current (A) G020 VOUT = 5V 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 Output Current (A) G021 Figure 37. Efficiency vs Output Current 90 10 45 0 0 −10 −45 −20 −90 Gain Phase −30 10 Output Voltage Normalized (%) Gain (dB) 135 20 −40 0.5 Phase (°) VIN = 24V IOUT = 5ma 30 −135 100 1000 Frequency (Hz) 10000 Figure 39. Gain vs Phase 28 Figure 38. Efficiency vs Output Current 180 40 VIN = 10V VIN = 24V VIN = 40 20 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 −180 100000 G018 VIN = 24V VOUT = 3.3V 0.4 0 0.01 0.02 0.03 Output Current (A) 0.04 0.05 G022 Figure 40. Output Voltage vs Output Current Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 Typical Applications (continued) Output Voltage Normalized (%) 0.25 IOUT = 7.5mA 0.20 0.15 0.10 0.05 0.00 −0.05 −0.10 −0.15 −0.20 −0.25 0 10 20 30 Input Voltage (V) 40 50 G023 Figure 41. Output Voltage vs Input Voltage Figure 42. Load Transient Figure 43. Unload Transient Figure 44. Start-Up With ENA Figure 45. Start-Up With VIN Figure 46. Prebias Start-Up With ENA Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 29 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com Typical Applications (continued) Figure 47. Prebias Start-Up With VIN Figure 48. Input and Output Ripple in DCM Figure 49. Input and Output Ripple in CCM 30 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 TPS54062 www.ti.com SLVSAV1D – MAY 2011 – REVISED JULY 2016 9 Power Supply Recommendations The TPS54062 is designed to operate from an input voltage supply range between 4.7 V and 60 V. This input supply should remain within the input voltage supply range. If the input supply is located more than a few inches from the TPS54062 converter bulk capacitance may be required in addition to the ceramic bypass capacitors. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See Figure 50 for a PCB layout example. Since the PH connection is the switching node and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has been shown to produce good results and is meant as a guideline. All sensitive analog traces and components such as VSENSE, RT/CLK and COMP should be placed away from high-voltage switching nodes such as PH, BOOT and inductor to avoid coupling. The topside resistor of the feedback voltage divider should be connected to the positive node of the VOUT capacitors or after the VOUT capacitors. 10.2 Layout Example VOUT GND Input Capacitor Route Boot Capacitor Trace on another layer to provide wide path for topside ground Output Capacitor Output Inductor Boot Capacitor BOOT VIN UVLO Adjust Resistor PH VIN GND EN COMP RT/CLK Compensation Network Feedback Resistors VSENSE Frequency Set Resistor Signal VIA Figure 50. PCB Layout Example Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 31 TPS54062 SLVSAV1D – MAY 2011 – REVISED JULY 2016 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks SwitcherPro, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TPS54062 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54062DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54062 TPS54062DRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 062 TPS54062DRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 062 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of