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TPS54116-Q1
SLVSCO3B – AUGUST 2016 – REVISED OCTOBER 2016
TPS54116-Q1 2.95-V to 6-V Input, 4-A Step-Down Converter and 1-A Source/Sink DDR
Termination Regulator
1 Features
•
1
•
•
•
•
•
•
•
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Single-chip DDR2, DDR3 and DDR3L Memory
Power Solution
4-A Synchronous Buck Converter
– Integrated 33-mΩ High-side and 25-mΩ Lowside MOSFETs
– Fixed Frequency Current-mode Control
– Adjustable Frequency from 100 kHz to 2.5
MHz
– Synchronizable to an External Clock
– 0.6-V ±1% Voltage Reference Over
Temperature
– Adjustable Cycle-by-Cycle Peak Current Limit
– Monotonic Start-up Into Pre-biased Outputs
1-A Source/Sink Termination LDO with ±20-mV
DC Accuracy
– Stable with 2 × 10-µF MLCC Capacitor
– 10-mA Source/Sink Buffered Reference Output
Regulated to Within 49% to 51% of VDDQ
Independent Enable Pins with Adjustable UVLO
and Hysteresis
Thermal Shutdown
-40°C to 150°C Operating TJ
24-pin, 4-mm x 4-mm WQFN Package
The TPS54116-Q1 buck regulator minimizes solution
size by integrating the MOSFETs and reducing
inductor size with up to 2.5-MHz switching frequency.
The switching frequency can be set above the
medium wave radio band for noise sensitive
applications and is synchronizable to an external
clock. Synchronous rectification keeps the frequency
fixed across the entire output load range. Efficiency is
maximized through integrated 25-mΩ low-side and
33-mΩ high-side MOSFETs. Cycle-by-cycle peak
current limit protects the device during an overcurrent
condition and is adjustable with a resistor at the ILIM
pin to optimize for smaller inductors.
The VTT termination regulator maintains fast
transient response with only 2 × 10-µF ceramic
output capacitance reducing external component
count. The TPS54116-Q1 uses remote sensing of
VTT for best regulation.
Using the enable pins to enter a shutdown mode
reduces supply current to 1-µA. Under voltage
lockout thresholds can be set with a resistor network
on either enable pin. The VTT and VTTREF outputs
are discharged when disabled with ENLDO.
Full integration minimizes the IC footprint with a small
4 mm × 4 mm thermally enhanced WQFN package.
Device Information(1)
PART NUMBER
PACKAGE
TPS54116-Q1
BODY SIZE (NOM)
WQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VIN
AVIN
TPS54116-Q1
BOOT
2 Applications
ENSW
•
ENLDO
PVIN
PGOOD
PGND
•
•
•
DDR2, DDR3, DDR3L, and DDR4 Memory Power
Supplies in Embedded Computing Systems
SSTL_18, SSTL_15, SSTL_135, SSTL_12 and
HSTL Termination
Infotainment and Cluster
Advanced Driver Assistance Systems (ADAS)
SW
VIN
VDDQSNS
ILIM
SS/TRK
VDDQ
LDOIN
VTT
COMP
FB
VTTSNS
3 Description
AGND
VTTGND
The TPS54116-Q1 device is a full featured 6-V, 4-A,
synchronous step down converter with two integrated
MOSFETs and 1-A sink/source double data rate
(DDR) VTT termination regulator with VTTREF
buffered reference output.
RT/SYNC
VTTREF
VTT
VTTREF
PAD
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54116-Q1
SLVSCO3B – AUGUST 2016 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 23
8
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application ................................................. 25
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
Changes from Revision A (August 2016) to Revision B
•
Page
Changed text From: "double date rate (DDR)" To: "double data rate (DDR)" in the Description .......................................... 1
Changes from Original (August 2016) to Revision A
Page
•
Changed pin 18 From: RT/CLK To: RT/SYNC in the Pin Functions table ............................................................................. 4
•
Changed R(RT/CLK) To: R(RT/SYNC) in Figure 16 and Figure 17.................................................................................................. 9
•
Changed "The RT/CLK is typically 0.5 V.." To: "The RT/SYNC is typically 0.5 V.." in Constant Switching Frequency
and Timing Resistor (RT/SYNC) .......................................................................................................................................... 20
2
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SLVSCO3B – AUGUST 2016 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
SW
SW
PVIN
PVIN
PGND
PGND
24
23
22
21
20
19
RTW Package
WQFN 24 Pins
Top View
SW
1
18
RT/SYNC
BOOT
2
17
SS/TRK
AVIN
3
16
COMP
PAD
ILIM
VDDQSNS
12
13
VTTREF
6
11
PGOOD
VTTSNS
AGND
10
14
VTTGND
5
9
ENLDO
VTT
FB
8
15
VLDOIN
4
7
ENSW
Pin Functions
PIN
I/O
DESCRIPTION
1, 23, 24
O
Switching node of the buck converter.
BOOT
2
I
Bootstrap capacitor node for high-side MOSFET gate driver of the buck converter. Connect
the bootstrap capacitor from this pin to the SW pin.
AVIN
3
I
The input supply pin to the IC, powering the control circuits of both the buck converter and
DDR termination regulator. Connect AVIN to a supply voltage between 2.95 V and 6 V.
ENSW
4
I
Buck converter enable pin with internal pull-up current source. Floating this pin will enable
the IC. Pull below 1.17 V to enter low current standby mode. Pull below 0.4 V to enter
shutdown mode. The ENSW pin can be used to implement adjustable under-voltage lockout
(UVLO) using two resistors.
ENLDO
5
I
VTT LDO enable pin with internal pull-up current source. Floating this pin will enable the IC.
Pull below 1.17 V to enter low current standby mode. Pull below 0.4 V to enter shutdown
mode. The ENLDO pin can be used to implement adjustable under-voltage lockout (UVLO)
using two resistors.
PGOOD
6
O
Power good indicator for the buck regulator. This pin is an open-drain output. A 10-kΩ pullup resistor is recommended between PGOOD and AVIN or an external logic supply pin.
VDDQSNS
7
I
VDDQ sense input to generate VDDQ/2 reference for VTTREF.
LDOIN
8
I
Power supply input for VTT LDO. Connected VDDQ in typical application. Alternatively this
pin can be used for split-rail configuration to reduce power dissipation when sourcing current
to the VTT output by powering the VTT LDO with a lower voltage.
VTT
9
O
1-A LDO output. Connect 2 x 10-µF ceramic capacitors to VTTGND for stability.
VTTGND
10
I
Power ground for VTT LDO.
VTTSNS
11
I
VTT LDO voltage feedback.
VTTREF
12
O
Buffered low-noise VTT reference output. Connect to a 0.22 µF or larger ceramic capacitor to
AGND for stability.
ILIM
13
I
Programmable current limit pin. An internal amplifier holds this pin at a fixed voltage then
sets the high-side MOSFET peak current limit based on the value of an external resistor to
AGND.
AGND
14
I
Analog signal ground of the IC. AGND should be connected to PGND via a single point on
the PCB, typically to the thermal pad.
NAME
SW
NO.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
FB
15
I
Error amplifier inverting input and feedback pin for voltage regulation of the buck converter.
Connect this pin to the center of a resistor divider to set the output voltage of the buck
converter. The resistor divider should go from the regulated output voltage to AGND.
COMP
16
I
Output of the internal transconductance error amplifier for the buck converter. The feedback
loop compensation network is connected from this pin to AGND.
SS/TRK
17
I
Soft-start programming pin. A capacitor between the SS/TRK pin and AGND pin sets softstart time. The voltage on this pin overrides the internal reference allowing it to be used for
tracking and sequencing.
18
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to AGND to set the switching frequency. If the pin is pulled
above the upper threshold, a mode change occurs and the pin becomes a synchronization
input. The internal amplifier is disabled and the pin is a high impedance clock input. If
clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to
resistor frequency programming.
PGND
19, 20
I
Power ground of the buck regulator. PGND should be connected to AGND via a single point
on PCB board, typically to the thermal pad.
PVIN
21, 22
I
The input supply pin for power MOSFETs. Connect PVIN to a supply voltage between 2.95 V
and 6 V.
–
The exposed thermal pad must be electrically connected to AGND and PGND on the printed
circuit board for proper operation. Connect to the largest possible copper area for best
thermal performance.
RT/SYNC
PAD
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage Range
(1)
MIN
MAX
PVIN, AVIN, ENSW, ENLDO, PGOOD
-0.3
7
V
FB, COMP, SS/TRK, ILIM
-0.3
3
V
RT/SYNC
-0.3
6
V
BOOT with respect to SW
-0.3
7
V
LDOIN, VTTSNS, VDDQSNS
-0.3
3.6
V
SW
-0.6
7
V
V
SW, 10-ns transient
Current Range
UNIT
-4
10
VTT, VTTREF
-0.3
3.6
V
RT/SYNC
-100
100
µA
-5
5
mA
Operating junction temperature
-40
150
°C
Storage temperature, Tstg
-65
150
°C
(1)
PGOOD
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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Product Folder Links: TPS54116-Q1
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SLVSCO3B – AUGUST 2016 – REVISED OCTOBER 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V(AVIN), V(PVIN)
Input voltage
2.95
6
V
VOUT
Buck output voltage
0.6
4.5
V
IOUT
Buck output current
0
4
A
V(VDDQSNS)
VDDQSNS input voltage
1
3.5
V
V(LDOIN)
LDOIN input voltage
VTT + VDO
3.5
V
V(VTT), V(VTTREF)
VTT and VTTREF output voltage
0.5
3.5
V
6.4 Thermal Information
TPS54116-Q1
THERMAL METRIC (1)
RTW (WQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
36.2
RθJC(top)
Junction-to-case (top) thermal resistance
35.0
RθJB
Junction-to-board thermal resistance
14.3
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
14.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.6
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
V
2.7
2.8
V
0.05
0.12
V
1
3.5
µA
SUPPLY VOLTAGE (AVIN and PVIN PINS)
AVIN and PVIN operating
AVIN internal UVLO threshold
2.95
AVIN rising
AVIN internal UVLO hysteresis
Iq shutdown
V(ENSW) = V(ENLDO) = 0 V, V(VDDQSNS) = 1.8
V, TJ = 25°C
Iq operating — LDO and buck enabled
V(ENSW) = V(ENLDO) = V(AVIN) = 5 V, V(FB) =
0.7 V, V(VDDQSNS) = 1.8 V, TJ = 25°C
650
800
µA
Iq operating — LDO enabled, buck
disabled
V(ENLDO) = V(AVIN) = 5 V, V(ENSW) = 0 V,
V(VDDQSNS) = 1.8 V, TJ = 25°C
190
300
µA
Iq operating — LDO disabled, buck
enabled
V(ENSW) = V(AVIN) = 5 V, V(ENLDO) = 0 V,
V(FB) = 0.7 V, V(VDDQSNS) = 1.8 V, TJ =
25°C
570
700
µA
ENABLE (ENSW and ENLDO PINS)
VENRISING
ENLDO rising threshold
ENLDO voltage ramping up
1.20
VENFALLING
ENLDO falling threshold
ENLDO voltage ramping down
1.17
ENLDO input current above voltage
threshold
V(ENLDO) = Enable threshold + 50 mV
-4.4
Ip
ENLDO input current below voltage
threshold
V(ENLDO) = Enable threshold - 50 mV
-1.7
Ih
ENLDO hysteresis current
VENRISING
ENSW rising threshold
ENSW voltage ramping up
1.20
VENFALLING
ENSW falling threshold
ENSW voltage ramping down
1.17
ENSW input current above voltage
threshold
V(ENSW) = Enable threshold + 50 mV
-4.4
Ip
ENSW input current below voltage
threshold
V(ENSW) = Enable threshold - 50 mV
-1.7
Ih
ENSW hysteresis current
-2.7
Input current above voltage threshold with V(ENLDO) = V(ENSW) = Enable threshold +
ENLDO and ENSW connected
50 mV
-8.5
V
µA
-2.7
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V
µA
µA
5
TPS54116-Q1
SLVSCO3B – AUGUST 2016 – REVISED OCTOBER 2016
www.ti.com
Electrical Characteristics (continued)
TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)
PARAMETER
Input current below voltage threshold with
ENLDO and ENSW connected
TEST CONDITIONS
MIN
V(ENLDO) = V(ENSW) = Enable threshold 50 mV
Hysteresis current with ENLDO and
ENSW connected
TYP
MAX
UNIT
-3.4
µA
-5.1
µA
VOLTAGE REFERENCE AND ERROR AMPLIFIER (FB AND COMP PINS)
VREF
Voltage Reference
0.594
FB pin input current
gmEA
0.6
0.606
7
260
V
nA
Error Amp transconductance (gm)
-2 µA < I(COMP) < 2 µA, V(COMP) = 1 V
Error Amp source/sink
V(COMP) = 1 V, V(FB) = 100 mV overdrive
22
360
V(BOOT-SW) = 5 V
33
66
V(BOOT-SW) = 3.3 V
42
84
V(PVIN) = 5 V
25
50
V(PVIN) = 3.3 V
30
60
µS
µA
MOSFETS AND POWER STAGE (SW AND BOOT PINS)
High side switch resistance
Low side switch resistance
gmPS
mΩ
BOOT-SW UVLO
V(PVIN) = 2.95 V
High-side FET current limit
V(PVIN) = 6V, R(ILIM) = 100k
5.2
6.6
8.2
A
High-side FET current limit
V(PVIN) = 6V, R(ILIM) = 200k
1.5
3
3.8
A
2
4.5
A
Low-side FET reverse current limit
2.2
mΩ
V
V(COMP) to I(SW)peak transconductance
R(ILIM) = 100k
16
A/V
Minimum pulse width
Measured at 50% points on V(SW), IOUT =
2A
60
ns
Minimum pulse width
Measured at 50% points V(SW), V(PVIN) = 5
V, IOUT = 0 A, TJ = -40°C to 125°C
100
Minimum off-time
Prior to skipping off pulses, IOUT = 2 A
125
60
ns
ns
TIMING RESISTOR AND EXTERNAL CLOCK (RT/SYNC PIN)
Switching frequency range using RT
mode
Switching frequency
100
2500
kHz
R(RT/SYNC) = 150 kΩ
370
400
430
kHz
R(RT/SYNC) = 27 kΩ
1910
2070
2230
kHz
340
420
480
kHz
2500
kHz
V(RT/SYNC) > 2.2 V or V(RT/SYNC) < 0.35 V
Switching frequency range using SYNC
mode
100
Minimum SYNC input pulse width
10
RT/SYNC high threshold
ns
1.5
RT/SYNC low threshold
RT/SYNC rising edge to SW rising edge
delay
fSW = 500 kHz
RT to SYNC lock in time
R(RT/SYNC) = 150 kΩ
0.35
0.4
30
45
2.2
V
V
80
ns
55
µs
60
µs
Internal RT to SYNC lock in time
Logic high or logic low at RT/SYNC to
SYNC signal
55
µs
SYNC to internal RT lock in time
SYNC signal to logic high or logic low at
RT/SYNC
60
µs
SYNC to RT lock in time
SOFT START AND TRACKING (SS/TRK PIN)
VSSTHR
ISS
6
SS voltage threshold
Charge Current
V(SS/TRK) < VSSTHR
V(SS/TRK) > VSSTHR
1.5
0.15
V
47
µA
2.4
3.2
V(SS/TRK) = 0.3 V
SS/TRK to reference crossover
98% normal
0.85
SS/TRK discharge voltage (overload)
V(FB) = 0 V
120
mV
SS/TRK discharge voltage (fault)
V(FB) = 0 V
5
mV
SS/TRK discharge current (overload)
V(FB) = 0 V, V(SS/TRK) = 0.4 V
160
µA
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60
µA
SS/TRK to FB matching
mV
1
V
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Product Folder Links: TPS54116-Q1
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SLVSCO3B – AUGUST 2016 – REVISED OCTOBER 2016
Electrical Characteristics (continued)
TJ = -40°C to 150°C, AVIN = PVIN = 2.95 V to 6 V, VLDOIN = VDDQSNS (unless otherwise noted)
PARAMETER
SS/TRK discharge current (AVIN UVLO,
ENSW low, thermal fault)
TEST CONDITIONS
MIN
V(AVIN) = 5 V, V(SS/TRK) = 0.4 V
TYP
MAX
UNIT
760
µA
POWER GOOD (PGOOD PIN)
Threshold
V(FB) falling (fault)
91
V(FB) rising (good)
94
V(FB) rising (fault)
105
V(FB) falling (good)
95
109
% VREF
106
Hysteresis
V(FB) falling and rising
3
Output high leakage
V(FB) = VREF, V(PGOOD) = 5.5 V
5
125
nA
On resistance
V(AVIN) = 2.95 V
85
170
Ω
Minimum V(AVIN) for valid output
V(PGOOD) < 0.5 V, I(PGOOD) = 100 µA
1.3
1.7
V
TERMINATION REGULATOR INPUTS (VLDOIN AND VDDQSNS PINS)
V(LDOIN) Operating
VDO
DC V(LDOIN) – V(VTT) dropout
1.2 V < V(VDDQSNS) < 2.5 V, I(VTT) = 0.5 A,
V(VTT) = V(VTTREF) - 40 mV
VDO
DC V(LDOIN) – V(VTT) dropout
1.2 V < V(VDDQSNS) < 2.5 V, I(VTT) = 1.5 A,
V(VTT) = V(VTTREF) - 40 mV
VLDOIN supply current
V(LDOIN) = 1.8 V, TJ = 25°C
VDDQSNS input current
V(VDDQSNS) = 1.8 V
39
3.5
V
0.15
V
0.45
V
1
µA
46
µA
VTTREF OUTPUT (VTTREF PIN)
V(VTTREF)
VTTREF output voltage
V(VDDQSNS)/2
V
|I(VTTREF)| < 10 mA, V(VDDQSNS) = 1.8 V
-18
18
|I(VTTREF)| < 10 mA, V(VDDQSNS) = 1.5 V
-15
15
|I(VTTREF)| < 10 mA, V(VDDQSNS) = 1.2 V
-15
15
|I(VTTREF)| < 5 mA, V(VDDQSNS) = 1.2 V
-12
V(VTTREF)TOL
VTTREF output voltage difference from
V(VDDQSNS)/2
I(VTTREF)SRC
VTTREF source current limit
V(VDDQSNS) = 1.8 V, V(VTTREF) = 0 V
10
18
mA
I(VTTREF)SNK
VTTREF sink current limit
V(VDDQSNS) = 0 V, V(VTTREF) = 1.8 V
10
19
mA
VTTREF discharge current
TJ = 25°C, V(VTTREF) = 0.5V, V(ENLDO) = 0
V
0.9
1.1
mA
|I(VTT)|≤ 10 mA, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V
-20
20
|I(VTT)|≤ 1 A, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V
-30
30
|I(VTT)|≤ 1.5 A, 1.2 V ≤ V(VDDQSNS) ≤ 1.8 V
-40
40
I(VTTREF)DIS
mV
12
VTT OUTPUT (VTT PIN)
V(VTT)
V(VTT)TOL
VTT output voltage
VTT output voltage tolerance to VTTREF
V(VTTREF)
V
mV
I(VTT)SRC
VTT source current limit
V(VDDQSNS) = 1.8 V, V(VTT) = V(VTTSNS) =
0.7 V
1.5
2.5
A
I(VTT)SNK
VTT sink current limit
V(VDDQSNS) = 1.8 V, V(VTT) = V(VTTSNS) =
1.1 V
1.5
2.5
A
I(VTTSNS)BIAS
VTTSNS input bias current
I(VTT)DIS
VTT discharge current
-0.1
TJ = 25°C, V(VTT) = 0.5 V, V(ENLDO) = 0 V
4.8
0.1
µA
6
mA
175
℃
16
℃
THERMAL SHUTDOWN
Thermal shutdown temperature
Thermal shutdown hysteresis
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6.6 Typical Characteristics
800
VIN = 3.3 V
VIN = 5 V
7
Nonswitching Supply Current (PA)
Shutdown Supply Current (PA)
8
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
700
675
650
625
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D002
Figure 2. Non-switching Supply Current - LDO and Buck
Enabled vs Temperature
610
VIN = 3.3 V
VIN = 5 V
300
Nonswitching Supply Current (PA)
Nonswitching Supply Current (PA)
725
D001
325
275
250
225
200
175
150
125
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
1.2
1.195
1.19
1.185
1.18
1.175
1.17
1.165
-25
0
25
50
75
100
Junction Temperature (qC)
595
590
585
580
575
570
565
560
-25
0
125
150
125
150
D004
-1
-1.5
-2
-2.5
V(EN) = Threshold - 50 mV
V(EN) = Threshold + 50 mV
-3
-3.5
-4
-4.5
-5
-50
-25
D005
Figure 5. ENSW and ENLDO Voltage Threshold vs
Temperature
25
50
75
100
Junction Temperature (qC)
Figure 4. Non-switching Supply Current - LDO Disabled and
Buck Enabled vs Temperature
ENSW and ENLDO Individual Input Current (PA)
EN Rising
EN Falling
1.16
-50
600
D003
1.21
1.205
VIN = 3.3 V
VIN = 5 V
605
555
-50
Figure 3. Non-switching Supply Current - LDO Enabled and
Buck Disabled vs Temperature
ENSW and ENLDO Voltage Threshold (V)
VIN = 3.3 V
VIN = 5 V
750
600
-50
150
Figure 1. Shutdown Supply Current vs Temperature
8
775
0
25
50
75
100
Junction Temperature (qC)
125
150
D006
Figure 6. ENSW and ENLDO Individual Input Current vs
Temperature
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0.606
-2
0.605
-3
0.604
-4
Voltage Reference (V)
ENSW and ENLDO Parallel Input Current (PA)
Typical Characteristics (continued)
-5
V(EN) = Threshold - 50 mV
V(EN) = Threshold + 50 mV
-6
-7
-8
0.603
0.602
0.601
0.6
0.599
0.598
0.597
0.596
-9
0.595
-10
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
0.594
-50
150
0
25
50
75
100
Junction Temperature (qC)
125
150
D008
Figure 8. Voltage Reference vs Temperature
Figure 7. ENSW and ENLDO Parallel Input Current vs
Temperature
320
Error Amplifier Transconductance (PS)
-25
D007
75
70
300
MOSFET Rds(on) (m:)
65
280
260
240
220
60
High-side, V(BOOT-SW) = 3.3 V
High-side, V(BOOT-SW) = 5 V
Low-side, V(PVIN) = 3.3 V
Low-side, V(PVIN) = 5 V
55
50
45
40
35
30
25
20
200
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
15
-50
150
7
6.5
6.5
6
5.5
R(ILIM) = 100 k
R(ILIM) = 200 k
5
0
4
3.5
3
25
50
75
100
Junction Temperature (qC)
125
150
D010
Figure 10. MOSFET Rds(on) vs Temperature
7
High-side Current Limit (A)
High-side Current Limit (A)
Figure 9. Error Amplifier Transconductance vs Temperature
4.5
-25
D009
6
5.5
5
4.5
4
3.5
3
2.5
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
2.5
100
110
120
D011
V(PVIN) = 5 V
V(PVIN) = 5 V
Figure 11. High-side Current Limit vs Temperature
130
140
150 160
R(ILIM)
170
180
190
200
D012
TA = 25°C
Figure 12. High-side Current Limit vs RILIM
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Typical Characteristics (continued)
140
VIN = 3.3 V
VIN = 5 V
18
17
16
15
14
13
120
110
100
90
80
70
60
50
12
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
40
-50
150
100
125
D014
650
VIN = 3.3 V
VIN = 5 V
95
600
550
90
Switching Frequency
Minimum pulse-width (ns)
0
25
50
75
Ambient Temperature (qC)
Figure 14. Minimum Pulse-width vs Temperature
100
85
80
75
70
65
500
450
400
350
300
250
200
60
150
55
0
0.5
1
1.5
2
2.5
IOUT (A)
3
3.5
100
100 150 200 250 300 350 400 450 500 550 600 650
R(RT/SYNC) (k:)
D016
4
D015
TA = 25°C
TA = 25°C
Figure 15. Minimum pulse-width vs Load Current
Figure 16. Switching Frequency vs R(RT/SYNC) Low Range
2800
410
2600
408
2400
406
Switching Frequency (kHz)
Switching Frequency
-25
D013
Figure 13. V(COMP) to I(SW) Transconductance vs
Temperature
2200
2000
1800
1600
1400
1200
1000
404
402
400
398
396
394
800
392
600
20
390
-50
30
40
50
60
70
R(RT/SYNC) (k:)
80
90
100
-25
D017
TA = 25°C
0
25
50
75
100
Junction Temperature (qC)
125
150
D018
R(RT/SYNC) = 150 kΩ
Figure 17. Switching Frequency vs R(RT/SYNC) High Range
10
VIN = 3.3 V, IOUT = 0 A
VIN = 5 V, IOUT = 0 A
VIN = 3.3 V, IOUT = 2 A
VIN = 5 V, IOUT = 2 A
130
Minimum Pulse-width (ns)
V(COMP) to I(SW) Transconductance (S)
19
Figure 18. Switching Frequency vs Temperature
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Typical Characteristics (continued)
430
2080
2076
Switching Frequency (kHz)
Switching Frequency (kHz)
2078
2074
2072
2070
2068
2066
2064
425
420
415
410
405
2062
2060
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
400
-50
150
R(RT/SYNC) = 27 kΩ
25
50
75
100
Junction Temperature (qC)
125
150
D020
Figure 20. Switching Frequency vs Temperature
2.5
54.5
2.48
54
2.46
53.5
I(SS/TRK) (µA)
I(SS/TRK) (µA)
Figure 19. Switching Frequency vs Temperature
53
52.5
2.44
2.42
2.4
52
2.38
51.5
2.36
-25
0
Internal RT
55
51
-50
-25
D019
0
25
50
75
100
Junction Temperature (qC)
125
2.34
-50
150
-25
0
D021
V(SS/TRK) < VSS(THR)
25
50
75
100
Junction Temperature (qC)
125
150
D022
V(SS/TRK) > VSS(THR)
Figure 21. I(SS/TRK) vs Temperature
of VREF)
108
PGOOD Threshold (
V(FB) (V)
Figure 22. I(SS/TRK) vs Temperature
110
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
106
104
102
V(FB) falling (fault)
V(FB) rising (good)
V(FB) rising (fault)
V(FB) falling (good)
100
98
96
94
92
0
0.2
0.4
0.6
0.8
1
V(SS/TRK) (V)
1.2
1.4
1.6
1.8
90
-50
-25
D023
0
25
50
75
100
Junction Temperature (qC)
125
150
D024
TA = 25°C
Figure 23. V(FB) vs V(SS/TRK)
Figure 24. PGOOD Thresholds vs Temperature
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Typical Characteristics (continued)
10
10
TA = -40 C
TA = 25 C
TA = 125 C
6
4
2
0
-2
-4
-6
-8
-10
-10
-8
-6
-4
-2
0
2
4
VTTREF Current (mA)
4
2
0
-2
-4
-6
8
-10
-10
10
-8
-6
D026
VDDQSNS = 1.5 V
-4
-2
0
2
4
VTTREF Current (mA)
6
8
10
D026
VIN = 5 V
Figure 25. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
Figure 26. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
10
10
TA = -40 C
TA = 25 C
TA = 125 C
6
4
2
0
-2
-4
-6
-8
-10
-10
TA = -40 C
TA = 25 C
TA = 125 C
8
VTTREF Regulation (mV)
VTTREF Regulation (mV)
6
VIN = 5 V
8
6
4
2
0
-2
-4
-6
-8
-8
-6
VDDQSNS = 1.35
V
-4
-2
0
2
4
VTTREF Current (mA)
6
8
-10
-10
10
-8
-6
D026
VIN = 5 V
VDDQSNS = 1.2 V
-4
-2
0
2
4
VTTREF Current (mA)
6
8
10
D026
VIN = 5 V
Figure 28. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
Figure 27. VTTREF Regulation to VDDQSNS/2 vs I(VTTREF)
25
25
TA = -40 C
TA = 25 C
TA = 125 C
20
15
10
5
0
-5
-10
10
5
0
-5
-10
-15
-15
-20
-20
-25
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
VTT Current (A)
VDDQSNS = 1.8 V
0.6
0.9
1.2
1.5
D030
VIN = 5 V
TA = -40 C
TA = 25 C
TA = 125 C
20
VTT Regulation (mV)
15
VTT Regulation (mV)
6
-8
VDDQSNS = 1.8 V
-25
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
VTT Current (A)
VDDQSNS = 1.5 V
Figure 29. VTT Regulation to VTTREF vs I(VTT)
12
TA = -40 C
TA = 25 C
TA = 125 C
8
VTTREF Regulation (mV)
VTTREF Regulation (mV)
8
0.6
0.9
1.2
1.5
D030
VIN = 5 V
Figure 30. VTT Regulation to VTTREF vs I(VTT)
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Typical Characteristics (continued)
25
25
TA = -40 C
TA = 25 C
TA = 125 C
20
15
VTT Regulation (mV)
10
5
0
-5
-10
10
5
0
-5
-10
-15
-15
-20
-20
-25
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
VTT Current (A)
VDDQSNS = 1.35
V
0.6
0.9
1.2
-25
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
VTT Current (A)
1.5
D030
VIN = 5 V
VDDQSNS = 1.2 V
0.9
1.2
0.6
D030
VIN = 5 V
40
TA = -40 C
TA = 25 C
TA = 125 C
0.55
0.5
1.5
Figure 32. VTT Regulation to VTTREF vs I(VTT)
Figure 31. VTT Regulation to VTTREF vs I(VTT)
200
Gain
Phase
30
150
0.45
0.4
Gain (dB)
Minimum VLDOIN - VTT Difference (V)
0.6
0.35
0.3
0.25
20
100
10
50
0
0
0.2
Phase (q)
VTT Regulation (mV)
15
TA = -40 C
TA = 25 C
TA = 125 C
20
0.15
0.1
-10
-50
0.05
0
0
0.1
0.2
VDDQSNS = 1.5 V
0.3 0.4 0.5 0.6 0.7
IVTT Sourcing Transient (A)
0.8
0.9
-20
10000
1
D034
VIN = 5 V
V(VTT) = 1.5 V
TA = 25°C
Figure 33. VTT Dropout
-100
1E+7
100000
1000000
Frequency (Hz)
D035
VIN = 5 V
I(VTT) = +1 A
Figure 34. VTT Sourcing Frequency Response
Gain
Phase
30
95
150
90
85
100
10
50
0
0
-10
Phase (q)
20
Gain (dB)
100
200
-50
Efficiency (%)
40
80
75
70
65
VDDQ = 1.8 V
VDDQ = 1.5 V
VDDQ = 1.35 V
VDDQ = 1.2 V
60
55
-20
10000
100000
1000000
Frequency (Hz)
V(VTT) = 1.5 V
TA = 25°C
VIN = 5 V
-100
1E+7
50
0.0
0.5
D036
I(VTT) = –1 A
fSYNC = 2.1 MHz
TA = 25°C
Figure 35. VTT Sinking Frequency Response
1.0
1.5
2.0
2.5
Output Current (A)
VIN = 3.3 V
3.0
3.5
D044
L = 744373240068
Figure 36. Efficiency
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
Typical Characteristics (continued)
80
75
70
80
75
70
65
65
60
60
VDDQ = 1.8 V
VDDQ = 1.5 V
55
50
0.0
0.5
fSYNC = 2.1 MHz
TA = 25°C
1.0
1.5
2.0
2.5
Output Current (A)
VIN = 5 V
3.0
3.5
VDDQ = 1.8 V
VDDQ = 1.5 V
VDDQ = 1.35 V
VDDQ = 1.2 V
55
4.0
50
0.0
0.5
1.0
1.5
2.0
2.5
Output Current (A)
D045
L = 744373240068
fSYNC = 400 kHz
TA = 25°C
Figure 37. Efficiency
VIN = 3.3 V
3.0
3.5
4.0
D046
L = 744310200
Figure 38. Efficiency
100
95
90
Efficiency (%)
85
80
75
70
65
VDDQ = 1.8 V
VDDQ = 1.5 V
VDDQ = 1.35 V
VDDQ = 1.2 V
60
55
50
0.0
fSYNC = 400 kHz
TA = 25°C
0.5
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
4.0
D047
VIN = 5 V
L = 744310200
Figure 39. Efficiency
14
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7 Detailed Description
7.1 Overview
The TPS54116-Q1 is a 6-V, 4-A, synchronous step-down (buck) converter with two integrated N-channel
MOSFETs and integrated 1-A sink/source double data rate (DDR) VTT termination regulator with a VTTREF
buffed reference output.
To improve the performance during line and load transients the buck converter implements a constant frequency,
peak current mode control which reduces output capacitance and simplifies external frequency compensation
design. The wide switching frequency range of 100 kHz to 2500 kHz allows for efficiency and size optimization
when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on
the RT/SYNC pin. The RT/SYNC pin can also be used to synchronize the power switch turn on to the rising edge
of an external clock. The switching frequency can be set using an internal resistor by pulling the RT/SYNC below
the low threshold or above the high threshold.
The TPS54116-Q1 has a typical default start-up voltage of 2.7 V. The ENSW pin can be used to enable the buck
converter and the ENLDO pin can be used to enable VTT and VTTREF. The ENSW and ENLDO pins have
internal pullup current sources that can be used to adjust the input voltage under voltage lockout (UVLO) with
two external resistors. In addition, the pullup current provides a default condition when the ENSW or ENLDO pin
is floating for the device to operate. The total operating current for the TPS54116-Q1 is typically 650 µA when
not switching and under no load. When the device is disabled, the supply current is less than 3.5 µA.
The integrated 33-mΩ and 25-mΩ MOSFETs allow for high-efficiency power supply designs with continuous
output currents up to 4 amperes. The TPS54116-Q1 reduces the external component count by integrating the
boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between
the BOOT and SW pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side
MOSFET when the voltage falls below the BOOT-SW UVLO threshold. This BOOT circuit allows the TPS54116Q1 to operate approaching 100% duty cycle. The output voltage can be stepped down to as low as the 0.60-V
reference.
The TPS54116-Q1 features monotonic start-up under prebias conditions. The low-side FET turns on for a short
time period every cycle before the output voltage reaches the prebiased voltage. This ensures the boot capacitor
has enough charge to turn on the top FET when the output voltage reaches the prebiased voltage.
The TPS54116-Q1 has a power good comparator (PGOOD) with 3% hysteresis. Excessive output overvoltage
transients are minimized by taking advantage of the overvoltage power good comparator. When the regulated
output voltage (as sensed by the FB voltage) is greater than 109% of the nominal voltage, the overvoltage
comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output
voltage is lower than 106%.
The SS/TRK (soft-start or tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for soft-start. The SS/TRK pin is
discharged before the output power up to ensure a repeatable restart after an over temperature fault, UVLO fault
or disabled condition. To optimize the output startup waveform, two levels of SS/TRK output current are
implemented.
The TPS54116-Q1 limits the peak inductor current by sensing the current through the high-side MOSFET with
cycle-by-cycle protection. The peak current limit is adjusted using a resistor to ground on the ILIM pin. The
reverse current through the low-side MOSFET is also limited.
The 10-mA VTTREF buffered reference uses an internal resistor divider to regulate its output within 49% to 51%
of VDDQSNS. The 1-A VTT termination regulates to VTTREF and maintains fast transient response with only 2 ×
10-µF ceramic output capacitance. Remote sensing of VTT is used for best regulation. The VTT and VTTREF
outputs are discharged when disabled with the AVIN UVLO or with ENLDO.
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7.2 Functional Block Diagram
PGOOD
AVIN
PVIN
UVLO
Comparator
AGND
Vref_UV
Voltage
Reference
BOOT
Charge
Vref_OV
BOOT
UVLO
OVLO
Comparator
Error
Amplifier
FB
Current
Sense
BOOT
PWM
Comparator
PWM Latch
SS/TRK
ENSW
6
COMP
Q
R
Q
SW
Slope
Compensation
Maximum
Clamp
ILIM
S
Logic
Enable
Switcher
Current
Sense
Current
Limit
ILIM
Reference
Current
Limit
RT/SYNC
Oscillator
with
SYNC
PGND
VLDOIN
VDDQSNS
VTTREF
Shutdown
VTT
VTTSNS
Shutdown
ENLDO
Enable LDO
VTTGND
PAD
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7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54116-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is
compared through external resistors on the FB pin to an internal voltage reference by an error amplifier which
drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier
output is compared to the high-side power switch current. When the power switch current reaches the COMP
signal level the high-side power switch is turned off and the low-side power switch is turned on. The COMP pin
voltage will increase and decrease as the output current increases and decreases. The device implements a
current limit by clamping the internal COMP signal.
An internal ramp is used to provide slope compensation to prevent sub-harmonic oscillations. The peak inductor
current limit is constant over the full duty cycle range.
7.3.2 Bootstrap Voltage (BOOT) and Low Dropout Operation
The TPS54116-Q1 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT
and SW pins to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor
should be 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the
stable characteristics over temperature and voltage.
To improve dropout, the TPS54116-Q1 is designed to operate at 100% duty cycle as long as the BOOT-SW
voltage is greater than 2.2 V. The high-side MOSFET is turned off using an UVLO circuit, allowing for the lowside MOSFET to conduct, when the BOOT-SW voltage drops below 2.2 V. Because the supply current sourced
from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to
refresh the capacitor, thus the effective duty of the switching regulator is high.
7.3.3 Error Amplifier
The TPS54116-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the FB
voltage to the lower of the SS/TRK pin voltage or the internal 0.6-V voltage reference. The transconductance
(gmEA) of the error amplifier is 260 µA/V during normal operation. During soft-start, the gmEA is reduced to 90
µA/V. The frequency compensation components are added to the COMP pin to ground.
When operating at current limit the COMP pin voltage is clamped to a maximum level to improve response when
the load current decreases. When FB is greater than the internal voltage reference or SS/TRK the COMP pin
voltage is clamped to a minimum level and the devices enters a high-side skip mode.
7.3.4 Voltage Reference and Adjusting the Output Voltage
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit. The FB voltage is regulated to the voltage reference. The output voltage
is set with a resistor divider from the output node to the FB pin. It is recommended to use divider resistors with
1% tolerance or better. Start with a 10.0 kΩ for the bottom resistor RFBB and use the Equation 1 to calculate
RFBT. The maximum recommend resistance value for the bottom resistor is 100 kΩ.
vertical spacer
RFBT
§V
RFBB u ¨ OUT
© VREF
·
1¸
¹
(1)
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Feature Description (continued)
TPS54116-Q1
VOUT
RFBT
FB
+
RFBB
0.6 V
Figure 40. Voltage Divider Circuit
7.3.5 Enable and Adjusting Undervoltage Lockout
The TPS54116-Q1 is enabled when the AVIN pin voltage exceeds 2.7 V and is disabled when it falls below 2.65
V. If an application requires a higher under-voltage lockout (UVLO) or more hysteresis, use the ENSW or ENLDO
pins as shown in Figure 41 to adjust the input voltage UVLO by using two external resistors. The EN pin has an
internal pull-up current source (Ip) of 1.7 µA that provides the default condition of the TPS54116-Q1 operating
when the EN pin floats. Once the EN pin voltage exceeds 1.2 V, an additional 2.7 μA hysteresis current (Ih) is
added. When the EN pin is pulled below 1.17 V, the 2.7 μA is removed. This additional current facilitates input
voltage hysteresis. It is recommended to use the EN resistors to set the UVLO falling threshold (VSTOP) at 2.65V
or higher. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply
variations. Equation 2 can be used to calculate the top resistor in the EN divider and Equation 3 is used to
calculate the bottom resistor.
The ENSW and ENLDO can also be tied in parallel. Calculations can be done the same but with the increased
EN current of Ip = 3.4 µA and Ih = 5.1 µA.
TPS54116-Q1
AVIN
Ip
Ih
RENT
+
ENLDO
or
ENSW
RENB
Figure 41. Adjustable Under Voltage Lock Out
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Feature Description (continued)
RENT
§V
·
VSTART u ¨ ENFALLING ¸ VSTOP
© VENRISING ¹
§
·
V
Ip u ¨ 1 ENFALLING ¸ Ih
VENRISING ¹
©
(2)
vertical spacer
RENB
RENT u VENFALLING
VSTOP
VENFALLING
RENT u Ip
Ih
(3)
Where:
• Ih = 2.7 µA
• Ip = 1.7 µA
• VENRISING = 1.2 V
• VENFALLING = 1.17 V
7.3.6 Soft Start and Tracking
The TPS54116-Q1 regulates to the lower of the SS/TRK pin and the internal reference voltage. A capacitor on
the SS/TRK pin to ground implements a soft start time. Before the SS pin reaches the voltage threshold VSSTHR
of 0.15 V, the charge current is about 47 μA. The TPS54116-Q1 internal pull-up current source of 2.4 μA charges
the external soft start capacitor after the SS pin voltage exceeds VSSTHR. Equation 4 calculates the required soft
start capacitor value where tSS is the desired soft start time for the output voltage to reach 90% its final value in
ms and CSS is the required capacitance in nF.
vertical spacer
CSS nF 5.3 u t SS ms
(4)
If during normal operation, AVIN goes below the UVLO, ENSW pin pulled below 1.17 V, or a thermal shutdown
event occurs, the TPS54116-Q1 stops switching. When the AVIN goes above UVLO, ENSW is released or pulled
high, or a thermal shutdown is exited, then SS/TRK is discharged to below 5 mV before reinitiating a powering up
sequence. The FB voltage will follow the SS/TRK pin voltage with a 60 mV offset up to 90% of the internal
voltage reference. When the SS/TRK voltage is greater than 90% of the internal reference voltage the offset
increases as the effective system reference transitions from the SS/TRK voltage to the internal voltage reference.
When the COMP pin voltage is clamped by the maximum COMP clamp in an overload condition the soft-start pin
is discharged to near the FB voltage. When the overload condition is removed, the soft-start circuit controls the
recovery from the fault output level to the nominal regulation voltage. At the beginning of recovery a spike in the
output voltage may occur as the COMP voltage transitions to the value determined by the loop.
7.3.7 Start-up into Pre-Biased Output
The TPS54116-Q1 features monotonic startup into pre-biased output. The low-side MOSFET turns on for a very
short time period every cycle before the output voltage reaches the pre-biased voltage. This ensures the BOOTSW cap has enough charge to turn on the high-side MOSFET when the output voltage reaches the pre-biased
voltage. The low-side MOSFET reverse current protection provides another layer of protection but it should not
be reached due to the implemented prebias function.
7.3.8 Power Good
The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the FB
pin is between 94% and 106% of the internal voltage reference, the PGOOD pin is de-asserted and the pin
floats. A pull up resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 6 V or less is
recommended. The PGOOD is in a defined state once the AVIN input voltage is greater than 1.3 V but with
reduced current sinking capability.
The PGOOD pin is pulled low when the FB is lower than 91% or greater than 109% of the nominal internal
reference voltage. The PGOOD is also pulled low if AVIN falls below its UVLO, ENSW pin is pulled low or the
TPS54116-Q1 enters thermal shutdown.
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Feature Description (continued)
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TRK, ENSW and
PGOOD pins. The sequential method can be implemented using an open-drain or collector output of a power on
reset pin of another device. An example sequential method is shown in Figure 42. PGOOD is connected to the
EN pin on the next power supply, which will enable the second power supply once the first supply reaches
regulation.
TPS54116-Q1
2nd DC/DC
PGOOD
ENSW
EN
SS/TRK
SS
CSS
PGOOD
CSS
Figure 42. Sequential Startup Example
7.3.10 Constant Switching Frequency and Timing Resistor (RT/SYNC)
The switching frequency of the TPS54116-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz by
placing a maximum of 620 kΩ and minimum of 22 kΩ, respectively, on the RT/SYNC pin. Alternatively the
RT/SYNC pin can be tied above the high threshold or below the low threshold to use an internal RT resistor to
set the switching frequency to 420 kHz. The RT/SYNC is typically 0.5 V and the current through the resistor sets
the switching frequency. To determine the timing resistance for a given switching frequency, refer to the curve in
Figure 16 and Figure 17 or use Equation 5. For a given RT resistor the nominal switching frequency can be
calculated with Equation 6. To reduce the solution size one would typically set the switching frequency as high as
possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should
be considered. The minimum controllable on time is typically 60 ns at 2-A load current and 100 ns at no load,
and will limit the maximum operating input voltage or minimum output voltage.
72540
R T k:
1.033
fSW kHz
(5)
fSW kHz
50740
R T k:
0.968
(6)
The RT/SYNC pin can also be used to synchronize the converter to an external system clock. When using the
internal RT resistor, the TPS54116-Q1 cannot be synchronized to an external clock. The synchronization
frequency range is 100 kHz to 2500 kHz. The rising edge of SW will be synchronized to the rising edge of
RT/SYNC. To implement the synchronization feature in a system connect a square wave to the RT/SYNC pin
with on-time at least 10 ns. The square wave amplitude at this pin must transition lower than 0.35 V and higher
than 2.2 V.
See Figure 43 for synchronizing to a high impedance system clock. See Figure 44 and Figure 45 for
synchronizing to a low impedance system clock. A tri-state buffer with its output directly connected to the
RT/SYNC pin is the recommended method to accomodate a wide range of external clock frequencies and duty
cycles. Alternatively an AC blocking capacitor circuit can be used when synchronizing to frequencies greater than
800 kHz and with clock signals with duty cycle near 50%. When using an AC coupling capacitor to interface with
an external clock, RT/SYNC is not actively pulled low by the external clock. As a result the TPS54116-Q1 begins
its transition back to RT mode while the external clock is low. When connecting the RT/SYNC pin to the external
clock source, it is important to minimize routing connected to the RT/SYNC pin as much as possible to minimize
noise sensitivity when operating in RT mode.
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Feature Description (continued)
TPS54116-Q1
RT/SYNC
Oscillator
RRT
Figure 43. Synchronizing to a High Impedance System Clock
TPS54116-Q1
OE
RT/SYNC
Oscillator
RRT
Figure 44. Interfacing to the RT/SYNC Pin with Buffer
TPS54116-Q1
RT/SYNC
Oscillator
1k
22 pF
RRT
Figure 45. Interfacing to the RT/SYNC Pin with RC
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Feature Description (continued)
7.3.11 Buck Overcurrent Protection
The TPS54116-Q1 implements current mode control which uses the COMP pin voltage to turn off the high-side
MOSFET and turn on the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and the
COMP pin voltage are compared, when the peak switch current intersects the COMP voltage the high-side
switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond
by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This
clamp functions as a high-side switch current limit.
A resistor placed from ILIM to AGND sets the peak current limit of the buck converter in the TPS54116-Q1. A
100 kΩ resistor sets it to the maximum value and a 200 kΩ resistor sets it to the minimum value. Any resistor
within this range can be used. Figure 12 shows the relationship between peak current limit and ILIM resistor. To
determine the resistor value for a target current limit use Equation 7.
vertical spacer
RILIM
420 u Ilimit
0.75
(7)
The TPS54116-Q1 also implements low-side current protection by detecting the voltage over the low-side
MOSFET. When the converter sinks current through the low-side MOSFET is more than 4.5 A, the control circuit
will turn the low-side MOSFET off immediately for the rest of the clock cycle. Under this condition, both the highside and low-side are off until the start of the next cycle.
7.3.12 Overvoltage Transient Protection
The TPS54116-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the FB pin voltage to OVTP threshold which is 109% of the
internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high-side MOSFET is
disabled preventing current from flowing to the output and minimizing output overshoot. The output voltage can
overshoot the 109% threshold as the current in the inductor discharges to 0 A. When the FB voltage drops lower
than the OVTP threshold the high-side MOSFET is allowed to turn on the next clock cycle.
7.3.13 VTT Sink and Source Regulator
The TPS54116-Q1 integrates a high-performance, low-dropout (LDO) linear regulator (VTT) that has ultimate fast
response to track ½ VDDQSNS within 40 mV at all conditions, and its current capability is 1.5 A peak current for
both sink and source directions. Two 10-µF (or greater) ceramic capacitor(s) need to be attached close to the
VTT pin for stable operation. X5R grade or better is recommended. To achieve tight regulation with minimum
effect of trace resistance, the remote sensing terminal, VTTSNS, should be connected to the positive terminal of
the output capacitor(s) as a separate trace from the high current path from the VTT pin.
The device has a dedicated pin, VLDOIN, for VTT power supply to minimize the LDO power dissipation on user
application. The minimum VLDOIN voltage is 0.45 V above the ½ VDDQSNS voltage.
7.3.14 VTTREF
The VTTREF pin has a 10 mA sink and source current capability, and regulates to within 49% to 51% of
VDDQSNS. A 0.22-µF ceramic capacitor needs to be attached close to the VTTREF terminal for stable
operation. X5R grade or better is recommended.
7.3.15 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C.
The thermal shutdown has a hysteresis of 16°C. When the junction temperature exceeds thermal trip threshold,
thermal shutdown forces the device to stop switching and discharges both VTT and VTTREF. When the die
temperature decreases below 159°C, the device reinitiates the power-up sequence by discharging the SS/TRK
pin.
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7.4 Device Functional Modes
The enable pins and an AVIN UVLO are used to control turn on and turn off of the TPS54116-Q1. The device
becomes active when V(AVIN) exceeds the 2.7 V typical UVLO and when either V(ENSW) or V(ENLDO) exceeds 1.20
V typical. The ENSW pin is used to control the turn on and turn off of the buck converter. The ENLDO pin is used
to control the turn on and turn off of the VTTREF and VTT outputs of the termination regulator. The ENSW and
ENLDO pins both have an internal current source to enable their respective outputs when left floating. Both
ENSW and ENLDO need to be pulled low to put the device into a low quiescent current state.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54116-Q1 is a fully integrated power solution for DDR2, DDR3 and DDR3L memory supplying VDDQ,
VTTREF and VTT as shown in Figure 46. It can also be used to power LPDDR2, LPDDR3 and DDR4 memory
but an additional power supply is required for VDD1 or VPP as shown in Figure 47. The TPS54116-Q1 can
supply 4 A for VDDQ and 1 A for VTT. The sourcing current for VTT comes from VDDQ and must be included as
part of the total VDDQ load current. Use the following design procedure to select component values for the
TPS54116-Q1. This procedure illustrates the design of a high-frequency switching regulator using ceramic output
capacitors. Alternatively the WEBENCH® software can be used to generate a complete design. The
WEBENCH® software uses an interactive design procedure and accesses a comprehensive database of
components when generating a design. This section presents a simplified discussion of the design process.
VDDQ
5.0 V or 3.3 V
TPS54116-Q1
VTTREF
VTT
Copyright © 2016, Texas Instruments Incorporated
Figure 46. DDR2, DDR3 and DDR3L Application Block Diagram
VDDQ
5.0 V or 3.3 V
TPS54116-Q1
VTTREF
VTT
TPS57112-Q1
or other DC/DC
VPP or
VDD1
Copyright © 2016, Texas Instruments Incorporated
Figure 47. LPDDR2, LPDDR3 and DDR4 Application Block Diagram
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8.2 Typical Application
VIN
L1
R1
45.3k
C1
47µF
C2
0.1µF
C3
10µF
C4
1µF
VDDQ
680nH
C8
10µF
C12
47µF
C13
47µF
C17
180pF
C14
47µF
R14
15.0k
C10
0.1µF
R15
10.0k
U1
TPS54116QRTWRQ1
3
21
22
R2
30.1k
R5
100k
R3
100k
C5
3300pF
R6
20.5k
AVIN
PVIN
PVIN
8
LDOIN
4
ENSW
5
ENLDO
6
13
BOOT
SW
SW
SW
VDDQSNS
VTT
SS/TRK
COMP
15
FB
18
RT/SYNC
9
VTTSNS
VTTREF
12
AGND
14
PGND
PGND
19
20
VTTGND
10
PAD
25
ILIM
16
7
11
PGOOD
17
2
1
23
24
VTT
C15
10µF
VTTREF
C16
10µF
C11
0.22µF
NT1
Net-Tie
C7
180pF
C9
C6
1800pF
R6
OSC IN
R7
26.7k
22pF
1.00k
AGND
PGND
Figure 48. 3.3-V or 5-V Input, 2.1 MHz fsw, DDR3 Schematic
8.2.1 Design Requirements
Table 1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input Voltage
5 V nominal, 2.95 V to 5.25 V
Output Voltage
1.5 V
Maximum Output Current (VDDQ)
4A
Maximum Output Current (VTT)
1A
Output Voltage Ripple (VDDQ)
0.5% of VOUT
Transient Response 1 A to 3 A load step
ΔVOUT = 4 %
Start Input Voltage (rising VIN)
2.9 V
Stop Input Voltage (falling VIN)
2.6 V
8.2.2 Detailed Design Procedure
8.2.2.1 Switching Frequency
The first step is to decide on a switching frequency for the regulator. The buck converter is capable of running
from 100 kHz to 2.5 MHz. Typically the highest switching frequency possible is desired because it will produce
the smallest solution size. A high switching frequency allows for lower valued inductors and smaller output
capacitors compared to a power supply that switches at a lower frequency. Additionally in applications with EMI
requirements, such as automotive, choosing a switching frequency of 2.1 MHz is desired to keep the switching
noise above the medium wave band or AM band. They main trade off made with selecting a higher switching
frequency is extra switching power loss, which hurt the converter’s efficiency.
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The maximum switching frequency for a given application is limited by the minimum on-time of the converter and
is estimated with Equation 8. For this application with the maximum minimum on-time of 125 ns at no load and
5.25 V maximum input voltage the maximum switching frequency is 2.28 MHz. A switching frequency of 2.1 MHz
is selected to stay above the AM band. Equation 9 calculates R14 to be 26.8 kΩ. A standard 1% 26.7 kΩ value
was chosen in the design.
VOUT
1
fSW max
u
tonmin VIN max
(8)
R T k:
72540
fSW kHz
1.033
(9)
8.2.2.2 Output Inductor Selection
To calculate the value of the output inductor, use Equation 10. KIND is a ratio that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.
Additionally the inductor current ripple is used as part of the PWM control system. Choosing small inductor ripple
currents can degrade the transient response performance or introduce jitter in the duty cycle. In general, the
inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority
of applications giving a peak to peak ripple current range of 0.4 A to 1.2 A. It is recommended to always keep the
peak to peak ripple current above 0.4 A because with a current mode control the inductor current ramp is used in
the PWM control system.
For this design example, KIND = 0.3 is used and the inductor value is calculated to be 0.43 μH. The next standard
value 0.68 µH is selected. It is important that the RMS current and saturation current ratings of the inductor not
be exceeded. The RMS and peak inductor current can be found from Equation 12 and Equation 13. For this
design, the RMS inductor current is 4.0 A and the peak inductor current is 4.4 A. The chosen inductor is a WE
744373240068. It has a saturation current rating of 10.0 A (20% inductance loss) and a RMS current rating of 5.5
A (40 °C. temperature rise). The series resistance is 16.0 mΩ typical.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the steady-state peak inductor current.
Additionally if a hard short on the output occurs in a fault condition the peak inductor current can exceed the
current limit and may reach up to 10 A. The peak current limit in this scenario is only limited by the minimum ontime of the TPS54116-Q1 and the parasitic DC voltage drops in the circuit. The peak current during a hard short
will vary with the switching frequency and only exceeds the current limit when using the TPS54116-Q1 with
higher switching frequencies like 2.1 MHz. To protect the inductor in a hard output short the inductor should be
rated for this current.
Vinmax - Vout
Vout
´
L1 =
Io ´ Kind
Vinmax ´ ¦ sw
(10)
vertical spacer
Iripple =
Vinmax - Vout
Vout
´
L1
Vinmax ´ ¦ sw
(11)
vertical spacer
ILrms =
Io 2 +
æ Vo ´ (Vinmax - Vo) ö
1
´ ç
÷
12
è Vinmax ´ L1 ´ ¦ sw ø
2
(12)
vertical spacer
ILpeak = Iout +
26
Iripple
2
(13)
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8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria and is often the most stringent. The
output capacitor needs to supply the increased load current until the regulator responds to the load step. The
regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no
load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change
in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must
be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the
specified range. At higher switching frequencies the fastest response time is about 4 µs. Equation 14 shows the
minimum output capacitance necessary, where ΔIOUT is the change in output current, tresponse is the regulators
response time and ΔVOUT is the allowable change in the output voltage. The minimum of 2/fsw or 4 µs should be
used for the response time in the output capacitance calculation. It is important to realize the response to a
transient load also depends on the loop compensation and slew rate of the transient load. This calculation
assumes the loop compensation is designed for the output filter with the equations later on in this procedure.
For this example, the transient load response is specified as a 4% change in VOUT for a load step of 2 A.
Therefore, ΔIOUT is 2 A and ΔVOUT = 0.04 × 1.5 = 60 mV. Using these numbers with a 4 µs response time gives a
minimum capacitance of 133 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be considered for load step response.
Equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 7.5 mV. Under this requirement,
Equation 15 yields 6.3 µF.
vertical spacer
Co ! tresponse u
'Iout
'Vout
(14)
vertical spacer
Co >
1
´
8 ´ ¦ sw
1
Voripple
Iripple
Where:
•
ΔIOUT is the change in output current
•
fsw is the regulators switching frequency
•
ΔVOUT is the allowable change in the output voltage
(15)
vertical spacer
Equation 16 calculates the maximum combined ESR the output capacitors can have to meet the output voltage
ripple specification and this shows the ESR should be less than 10 mΩ. In this case ceramic capacitors will be
used and the combined ESR of the ceramic capacitors in parallel is much less than 10 mΩ. Capacitors also
generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An
output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets
specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 17 can be used to calculate
the RMS ripple current the output capacitor needs to support. For this application, Equation 17 yields 220 mA.
Ceramic capacitors used in this design will have a ripple current rating much higher than 220 mA.
Voripple
Resr <
Iripple
(16)
vertical spacer
Icorm s =
Vout ´ (Vinm ax - Vout)
12 ´ Vinm ax ´ L1 ´ ¦ sw
(17)
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The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. For this application example, three 47 μF 10 V 1210
X7R ceramic capacitors each with 8 mΩ of ESR at the fsw are used. The estimated capacitance after derating
shown on the capcaitor manufacturer's website with 1.5 V DC bias is 51.4 µF each. With 3 parallel capacitors the
total output capacitance is 154 µF and the ESR is 2.7 mΩ.
8.2.2.4 Input Capacitor
The TPS54116-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF
of effective capacitance placed across the PVIN and PGND pins and in some applications a bulk capacitance.
The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
RMS input current of the TPS54116-Q1. The RMS input current can be calculated using Equation 18. An input
decoupling capacitor of 1 µF must also be placed at the AVIN pin to ensure a stable input voltage to the internal
control circuits.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 47 µF 1210 X7R, one 10 µF 0603 X7R and one 0.1 μF 0603 X7R
10 V capacitors in parallel have been selected for the PVIN to PGND pins. Additionally one 1 µF 0603 X5R 10 V
capacitor is selected for the AVIN pin. The 0.1 µF at the PVIN pin is used to better bypass the higher frequency
content when the high-side MOSFET switches on and off. Based on the capacitor manufacturer's website, the
total input capacitance derates to 34 µF at the nominal input voltage of 5 V. The input capacitance value
determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 19.
Using the design example values, Ioutmax = 4 A, Cin = 34 μF, fSW = 2.1 MHz, yields an input voltage ripple of 14
mV and a rms input ripple current of 1.9 A.
Icirms = Iout ´
Vout
´
Vinmin
(Vinmin
- Vout )
Vinmin
vertical spacer
Ioutmax ´ 0.25
DVin =
Cin ´ ¦ sw
(18)
(19)
8.2.2.5 Soft Start Capacitor
The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54116-Q1 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The soft-start capacitor value can be calculated using Equation 20. For the example circuit, the soft-start time is
not too critical since the output capacitor value of 3 x 47 µF does not require much current to charge to 1.5 V.
With the higher switching frequency used in this example a faster start-up time improves the start up behavior.
Near the beginning of the start up time when the output voltage is low the minimum on-time of the converter is
too large to regulate the output causing additional ripple on the output. A faster start-up time will reduce the time
the converter spends in this region. The example circuit is designed for a soft-start time of 0.6 ms which requires
a 3300 pF capacitor.
CSS nF
28
5.3 u t SS ms
(20)
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8.2.2.6 Undervoltage Lock Out Set Point
The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the ENSW and ENLDO
pin of the TPS54116. Each pin can have its own resistor divider if different thresholds are needed for the VTT
LDO and the buck converter. If only one threshold is needed only one resistor divider is needed and the pins can
be connected in parallel. If connected in parallel the pull up current and hysteresis current should be increased to
3.4 µA and 5.1 µA respectively as shown in the electrical specifications. The UVLO has two thresholds, one for
power-up when the input voltage is rising, and one for power-down or brown outs when the input voltage is
falling.
For the example design, the supply should turn on and start switching once the input voltage increases above
2.9 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below
2.6 V (UVLO stop). The EN pins are also connected in parallel so the higher pull up current and hysteresis
current is used. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. A 45.3
kΩ between PVIN and the EN pins (R1) and a 30.1 kΩ between the EN pins and ground (R2) are used
producing a start voltage of 2.85 V and stop voltage of 2.47 V. The 2.47 V stop voltage is below the 2.65 V AVIN
UVLO so with this application example the TPS54116-Q1 will turn off due to the AVIN UVLO.
8.2.2.7 Bootstrap Capacitor
A 0.1 μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
8.2.2.8 Power Good Pullup
A 100 kΩ resistor is used to pull up the power good signal to VIN when FB conditions are met.
8.2.2.9 ILIM Resistor
The recommended peak current limit is calculated with Equation 21 using ILpeak from Equation 13. This
calculation includes 10% margin for load transients and an additional 1.5 A for the tolerance of the peak current
limit. In this application a 100 kΩ resistor is placed from ILIM to AGND to set the peak current limit to its
maximum value. For applications requiring a different peak current limit Equation 7 is used to calculate the ILIM
resistor.
vertical spacer
Ilimit ILpeak u 1.1 1.5A
(21)
8.2.2.10 Output Voltage and Feedback Resistors Selection
For the example design, 10.0 kΩ was selected for R7. Using Equation 22, R5 is calculated as 15.0 kΩ which is a
standard 1% resistor.
vertical spacer
RFBT
§V
RFBB u ¨ OUT
© VREF
·
1¸
¹
(22)
8.2.2.11 Compensation
There are several methods used to compensate DC - DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency
used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low
ESR output capacitors. Use the WEBENCH software for more accurate loop compensation. These tools include
a more comprehensive model of the control loop.
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To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 23 and
Equation 24. For Cout, use a derated value of 154 μF. Use equations Equation 25 and Equation 26, to estimate
a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
2.8 kHz and fzmod is 388 kHz. Equation 25 is the geometric mean of the modulator pole and the esr zero and
Equation 26 is the mean of modulator pole and one half the switching frequency or 250 kHz, whichever is larger.
For the 2.1 MHz switching frequency application 250 kHz is used so Equation 25 yields 33 kHz and Equation 26
gives 52 kHz. Use the lower value of Equation 25 or Equation 26 for an initial crossover frequency. Next, the
compensation components are calculated. A resistor-in-series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout
(23)
1
¦ z mod =
2 ´ p ´ Resr × Cout
(24)
fco =
f p mod ´ f z mod
fco =
f p mod ´
(25)
f sw
2
(26)
To determine the compensation resistor, R6, use Equation 27. Assume the power stage transconductance,
gmps, is 16 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
1.5 V, 0.6 V and 260 μA/V, respectively. R6 is calculated to be 19 kΩ and the closest standard value 19.1 kΩ.
Use Equation 28 to set the compensation zero to the modulator pole frequency. Equation 28 yields 3020 pF for
compensating capacitor C6 and the closest standard value is 3300 pF.
§ 2 u S u fCO u COUT · §
·
VOUT
RCOMP ¨
¸u¨
¸
gmPS
©
¹ © VREF u gmEA ¹
(27)
1
CCOMP
2 u S u RCOMP u fPMOD
(28)
A compensation pole is implemented using an additional capacitor C7 in parallel with the series combination of
R6 and C6. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal.
Use the larger value of Equation 29 and Equation 30 to calculate the C7, to set the compensation pole. C7 is
calculated to 21 pF or 8 pF and the closest standard value is 22 pF.
COUT u RESR
CHF
RCOMP
(29)
CHF
1
S u RCOMP u fSW
(30)
Type III compensation is used by adding the feed forward capacitor (C17) in parallel with the upper feedback
resistor. This increases the crossover and adds phase boost above what is normally possible from Type II
compensation. It places an additional zero/pole pair. This zero and pole pair is not independent. Once the zero
location is chosen, the pole is fixed as well. The zero is placed at the intended crossover frequency by
calculating the value of C17 with Equation 31. The calculated value is 216 pF and the closest standard value is
220 pF.
1
CFF
3 u S u RFBT u fCO
(31)
The initial compensation based on these calculations is R6 = 19.1 kΩ, C6 = 3300 pF, C7 = 22 pF and C17 = 220
pF. These values yield a stable design but after testing the real circuit these values were changed to optimize
performance. The final values used in the schematic are R6 = 20.5 kΩ, C6 = 1800 pF, C7 = 180 pF and C17 =
180 pF.
8.2.2.12 LDOIN Capacitor
Depending on the trace impedance between the LDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the LDOIN input capacitor. Use a 10-µF (or greater) and
X5R grade (or better) ceramic capacitor to supply this transient charge.
30
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8.2.2.13 VTTREF Capacitor
Add a ceramic capacitor, with a value 0.22 µF and X5R grade (or better), placed close to the VTTREF terminal
for stable operation.
8.2.2.14 VTT Capacitor
For stable operation, two 10-µF (or greater) and X5R (or better) grade ceramic capacitor(s) need to be attached
close to the VTT terminal. This capacitor is recommended to minimize any additional equivalent series resistance
(ESR) and/or equivalent series inductance (ESL) of ground trace between the PGND terminal and the VTT
capacitor(s).
8.2.3 Application Curves
100
0.30
90
0.25
0.20
Load Regulation (%)
80
60
50
40
30
20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
10
-0.25
VIN = 5V
0
0.0
0.5
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
-0.30
0.0
4.0
Figure 49. VDD Output Efficiency
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
4.0
D039
Figure 50. VDD Output Load Regulation, VIN = 5 V
0.25
60
180
0.20
50
150
40
120
30
90
20
60
0.15
0.10
0.05
Gain (dB)
Line Regulation (%)
0.5
D037
0.00
-0.05
-0.10
-0.15
10
30
0
0
-10
-30
-20
-60
-30
-90
-40
-0.20
-50
-0.25
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
6.0
-60
100 200
500 1000
D041
Figure 51. VDD Output Line Regulation, IOUT = 2 A
10000
Frequency (Hz)
Phase (Degree)
Efficiency (%)
70
-120
Gain (dB)
Phase (Deg) -150
-180
100000
500000
D043
Figure 52. VDD Output Loop Response
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EN = 2 V / div
EN = 2 V / div
SS = 1 V / div
VTT = 1 V / div
VDD = 1 V / div
VDD = 1 V / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 1 msec / div
Figure 53. VDD Start-Up Relative to Enable
Time = 1 msec / div
Figure 54. VTT and VDD Start-Up Relative to Enable
EN = 2 V / div
VIN = 5 V / div
SS = 1 V / div
SS = 1 V / div
VDD = 1 V / div
VDD = 1 V / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 1 msec / div
Figure 55. VDD Start-Up Relative to VIN
Time = 1 msec / div
Figure 56. VDD Shutdown Relative to Enable
VIN = 5 V / div
EN = 2 V / div
SS = 1 V / div
VTT = 1 V / div
VDD = 1 V / div
VDD = 1 V / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 1 msec / div
Figure 57. VTT and VDD Shutdown Relative to Enable
32
Time = 1 msec / div
Figure 58. VDD Shutdown Relative to VIN
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VTT = 20 mV / div (ac coupled)
VDD = 10 mV / div (ac coupled)
SW = 2 V / div
SW = 2 V / div
Time = 500 nsec / div
Figure 60. VTTOutput Ripple
Time = 500 nsec / div
Figure 59. VDD Output Ripple
VIN = 100 mV / div (ac coupled)
VDD = 50 mV / div (ac coupled)
IOUT = 1A / div
SW = 2 V / div
Load step 1 A to 3 A, slew rate 500 mA / µsec
Time = 200 µsec / div
Figure 62. VDD Output Transient Response
Time = 500 nsec / div
Figure 61. Input Ripple
VTT = 20 mV / div (ac coupled)
CLK = 2 V / div
Time = 100 µsec / div
Figure 63. VTT Output Transient Response
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9 Power Supply Recommendations
The TPS54116-Q1 is designed to be powered by a well regulated dc voltage between 2.95 and 6 V. The
TPS54116-Q1 is a buck converter so the input supply voltage must be greater than the desired output voltage to
regulate the output voltage to the desired value. If the input supply voltage is not high enough the output voltage
will begin to drop. Input supply current must be appropriate for the desired output current.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Guidelines are as follows. See Figure 64 for a PCB layout example.
•
•
•
•
•
•
•
•
•
•
•
•
•
The input bypass capacitor for PVIN to PGND should be placed as close as possible to the TPS54116-Q1
with short and wide connections to minimize parasitic inductance.
The input bypass capacitor for AVIN should be placed as close as possible to the TPS54116-Q1 with a short
return to the AGND pin. This capacitor and pin should also be tied to the input voltage before the PVIN
bypass capacitors to limit the switching noise from PVIN.
The output capacitor for VTT to VTTGND should be placed as close as possible to the TPS54116-Q1 with
short and wide connections to minimize parasitic inductance and resistance. Too much parasitic inductance
and resistance can affect the stability of the high performance VTT LDO.
The VTTSNS pin should be connected tothe VTT output capacitors as a seperate trace from the high current
VTT power trace. If sensing the voltage at the pont of the load is required, it is recommended to also attach
the output capacitors at that point while still minimizing parasitic inductance and resistance.
The input bypass capacitor for LDOIN to VTTGND should be placed as close as possible to the TPS54116Q1 with short and wide connections to minimize parasitic inductance. This capacitor is used to supply the
transient current to the VTT output.
The VDDQSNS pin should be routed as a separate trace from the high current VDDQ trace and connect near
the point of regulation for VDDQ.
The top of the FB resistor divider should be routed as a separate trace from the high current VDDQ trace and
connect near the the point of regulation for VDDQ.
The analog control circuits should have a return path to the quiet AGND and not overlap with the noisey
PGND. Sensitive pins containing analog control circuits are RT/SYNC, SS/TRK, COMP, FB, ILIM, and
VTTREF. It is important to minimize the length of the traces connected to the RT/SYNC, COMP, FB and ILIM
pins.
The PGND pins, AGND and VTTGND pin should be tied directly to the power pad under the IC to provide a
low impedance connection between the pins.
The BOOT capacitor should connect directly between the BOOT and SW pins.
The SW pin should be routed to the output inductor with a short and wide trace to minimize capacitive
coupling.
The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under
the IC. For operation at full rated load, the top side ground area and bottom side ground area along with any
additional internal ground planes must provide adequate heat dissipating area. For best thermal performance
minimize cuts in the bottom side ground copper.
Additional vias can be used to connect the top side ground area to the internal planes near the input and
output capacitors for the buck converter and VTT LDO.
The additional external components can be placed approximately as shown. It may be possible to obtain
acceptable performance with alternate PCB layouts, however this layout has been shown to produce good
results and is meant as a guideline.
34
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10.2 Layout Example
GND
VTT
C
VTT
C
VTT
C
LDOIN
VTTSNS
VTT
LDOIN
VDDQSNS
11
10
9
8
7
R
ENB
PGOOD
ENLDO
4
ENSW
3
AVIN
R
ENB
5
14
6
AGND
VTTGND
13
THERMAL PAD
SS/ TRK
17
2
BOOT
RT/ SYNC
18
1
SW
R
ENT
R
ENT
R
PG
CIN
COMP
16
C
CP
FB
15
R
FBB
C
HF
R
CP
ILIM
12
R
ILIM
R
FBT
VTTREF
C
REF
C
FF
VREF
C
BT
20
21
22
23
24
PGND
PGND
PVIN
PVIN
SW
SW
R
T
19
C
SS
SW
CIN
VOUT
L
CIN
COUT
GND
COUT
COUT
COUT
GND
VIN
Figure 64. PCB Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54116QRTWRQ1
ACTIVE
WQFN
RTW
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54116Q
A2
TPS54116QRTWTQ1
ACTIVE
WQFN
RTW
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54116Q
A2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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