TPS5420
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SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013
2-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER
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FEATURES
APPLICATIONS
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Wide Input Voltage Range: 5.5 V to 36 V
Up to 2-A Continuous (3-A Peak) Output
Current
High Efficiency up to 95% Enabled by 110-mΩ
Integrated MOSFET Switch
Wide Output Voltage Range: Adjustable Down
to 1.22 V with 1.5% Initial Accuracy
Internal Compensation Minimizes External
Parts Count
Fixed 500-kHz Switching Frequency for Small
Filter Size
Improved Line Regulation and Transient
Response by Input Voltage Feed Forward
System Protected by Over Current Limiting,
Over Voltage Protection and Thermal
Shutdown
–40°C to 125°C Operating Junction
Temperature Range
Available in Small 8-Pin SOIC Package
Consumer: Set-top Box, DVD, LCD Displays
Industrial and Car Audio Power Supplies
Battery Chargers, High Power LED Supply
12-V/24-V Distributed Power Systems
DESCRIPTION
The TPS5420 is a high-output-current PWM
converter that integrates a low resistance high side
N-channel MOSFET. Included on the substrate with
the listed features is a high performance voltage error
amplifier that provides tight voltage regulation
accuracy under transient conditions; an undervoltagelockout circuit to prevent start-up until the input
voltage reaches 5.5 V; an internally set slow-start
circuit to limit inrush currents; and a voltage feedforward circuit to improve the transient response.
Using the ENA pin, shutdown supply current is
reduced to 18 μA typically. Other features include an
active-high enable, overcurrent limiting, overvoltage
protection and thermal shutdown. To reduce design
complexity and external component count, the
TPS5420 feedback loop is internally compensated.
The TPS5420 device is available in an easy to use 8pin SOIC package. TI provides evaluation modules
and the Designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.
Efficiency vs Output Current
Simplified Schematic
100
VIN
PH
VIN
VOUT
95
TPS5420
BOOT
NC
ENA VSENSE
GND
90
Efficiency − %
NC
85
80
VI = 12 V
75
70
65
60
55
50
0
0.5
1.5
2.5
1
2
IO - Output Current - A
3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
TPS5420
SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
(2)
TJ
INPUT VOLTAGE
OUTPUT VOLTAGE
PACKAGE (1)
PART NUMBER
–40°C to 125°C
5.5 V to 36 V
Adjustable to 1.22 V
SOIC (D) (2)
TPS5420D
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The D package is available taped and reeled. Add an R suffix to the device type (i.e., TPS5420DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE
VIN
–0.3 to 40
BOOT
–0.3 to 50
–0.6 to 40 (3)
PH (steady-state)
VI
Input voltage range
UNIT
(3)
EN
–0.3 to 7
VSENSE
–0.3 to 3
BOOT-PH
V
10
PH (transient < 10 ns)
–1.2
IO
Source current
PH
Ilkg
Leakage current
PH
10
μA
TJ
Operating virtual junction temperature range
–40 to 150
°C
Tstg
Storage temperature
–65 to 150
°C
(1)
(2)
(3)
Internally Limited
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
THERMAL INFORMATION
TPS5420
THERMAL METRIC (1) (2) (3)
D (8 PINS)
(4)
θJA
Junction-to-ambient thermal resistance (custom board)
θJA
Junction-to-ambient thermal resistance (standard board)
ψJT
Junction-to-top characterization parameter
5.7
ψJB
Junction-to-board characterization parameter
47.0
θJC(top)
Junction-to-case(top) thermal resistance
45.0
θJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
θJB
Junction-to-board thermal resistance
47.8
(1)
(2)
(3)
(4)
2
UNITS
75
105.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Maximum power dissipation may be limited by overcurrent protection
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
Test boards conditions:
(a) 3 in x 3 in, 2 layers, thickness: 0.062 inch.
(b) 2 oz. copper traces located on the top and bottom of the PCB.
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VI
Input voltage range, VIN
5.5
36
V
TJ
Operating junction temperature
–40
125
°C
TYP
MAX
UNIT
3
4.4
mA
18
50
μA
Start threshold voltage, UVLO
5.3
5.5
Hysteresis voltage, UVLO
330
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 5.5 V to 36 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SUPPLY VOLTAGE (VIN PIN)
IQ
Quiescent current
VSENSE = 2 V, Not switching, PH pin
open
Shutdown, ENA = 0 V
UNDERVOLTAGE LOCK OUT (UVLO)
V
mV
VOLTAGE REFERENCE
Voltage reference accuracy
TJ = 25°C
1.202
1.221
1.239
IO = 0 A – 2 A
1.196
1.221
1.245
400
500
600
kHz
150
200
ns
87%
89%
1.3
V
V
OSCILLATOR
Internally set free-running frequency
Minimum controllable on time
Maximum duty cycle
ENABLE (ENA PIN)
Start threshold voltage, ENA
Stop threshold voltage, ENA
0.5
Hysteresis voltage, ENA
V
450
Internal slow-start time (0 ~ 100%)
6.6
8
mV
10
ms
CURRENT LIMIT
Current limit
Current limit hiccup time
3
4
5
A
13
16
20
ms
135
162
°C
14
°C
THERMAL SHUTDOWN
Thermal shutdown trip point
Thermal shutdown hysteresis
OUTPUT MOSFET
rDS(on)
High side power MOSFET switch
VIN = 5.5 V
150
VIN = 10 V - 36 V
110
230
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PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
BOOT
1
8
PH
NC
2
7
VIN
NC
3
6
GND
VSENSE
4
5
ENA
TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
NO.
BOOT
1
NC
2, 3
Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin.
Not connected internally.
VSENSE
4
Feedback voltage for the regulator. Connect to output voltage divider.
ENA
5
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND
6
Ground.
VIN
7
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic
capacitor.
PH
8
Source of the high side power MOSFET. Connected to external inductor and diode.
4
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TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
OPERATING QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
530
f − Oscillator Frequency − kHz
510
500
490
480
470
460
-50
180
VI = 12 V
170
Minimum Controllable On Time − ns
IQ − Operating Quiescent Current − mA
3.5
520
3.25
3
2.75
2.5
-25
0
50
25
75
100
-50
125
-25
0
25
50
75
100
160
150
140
130
120
-50
125
-25
0
50
25
o
TJ − Junction Temperature − C
o
TJ − Junction Temperature − C
75
100
Figure 2.
Figure 3.
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
ON STATE RESISTANCE
vs
JUNCTION TEMPERATURE
INTERNAL SLOW START TIME
vs
JUNCTION TEMPERATURE
180
9
VI = 12 V
1.22
1.215
tSS − Internal Slow Start Time − ms
rDS(on) − On-State Resistance − mW
170
1.225
125
o
TJ − Junction Temperature − C
Figure 1.
1.23
Vref − Voltage Reference − V
MINIMUM CONTROLLABLE ON TIME
vs
JUNCTION TEMPERATURE
160
150
140
130
120
110
100
8.5
8
7.5
90
1.21
-50
-25
0
50
25
75
100
125
80
-50
-25
o
TJ − Junction Temperature − C
0
25
50
75
100
-50
-25
0
50
25
75
100
125
o
TJ − Junction Temperature − C
Figure 5.
Figure 6.
SHUTDOWN QUIESCENT CURRENT
vs
INPUT VOLTAGE
MINIMUM CONTROLLABLE DUTY RATIO
vs
JUNCTION TEMPERATURE
8
ENA = 0 V
o
TJ = 125 C
20
Minimum Duty Ratio − %
ISD − Shutdown Current − mA
7
TJ − Junction Temperature − C
Figure 4.
25
125
o
TJ = 27oC
15
10
7.5
7.5
7.25
o
TJ = -40 C
5
7
0
5
10
15
20
25
30
35
40
-50
VI − Input Voltage − V
-25
0
25
50
75
100
125
o
TJ − Junction Temperature − C
Figure 7.
Figure 8.
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
1.221 V Bandgap
Reference
UVLO
VREF
SHDN
Slow Start
Boot
Regulator
BOOT
HICCUP
5 µA
ENABLE
ENA
SHDN
SHDN
VSENSE
Z1
Thermal
Protection
NC
SHDN
VIN
Ramp
Generator
NC
SHDN
VSENSE
HICCUP
PWM
Comparator
Overcurrent
Protection
Oscillator
OVP
Z2
Feed Forward
Gain = 25
SHDN
GND
Error
Amplifier
SHDN
SHDN
Gate Drive
Control
112.5% VREF
Gate
Driver
SHDN
BOOT
PH
VOUT
DETAILED DESCRIPTION
Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.
Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V disables the regulator and activate the shutdown mode. The
quiescent current of the TPS5420 in shutdown mode is typically 18 μA.
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its
final value linearly. The internal slow start time is 8 ms typically.
6
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Undervoltage Lockout (UVLO)
The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the
internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start
threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates
until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
Output Feedback (VSENSE)
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
Internal Compensation
The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 uses
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See the Internal Compensation Network in the applications
section for more details.
Voltage Feed Forward
The internal voltage feed forward provides a constant DC power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e.
VIN
Feed Forward Gain =
Ramppk-pk
(1)
The typical feed forward gain of TPS5420 is 25.
Pulse-Width-Modulation (PWM) Control
The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the
PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.
Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.
Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting scheme is called cycle-by-cycle current
limiting.
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side
MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under
control of the slow start circuit.
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Overvoltage Protection
The TPS5420 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from
output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage
and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side
MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side
MOSFET will be enabled again.
Thermal Shutdown
The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
PCB Layout
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this
is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 μF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device
and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground
area under the device as shown in Figure 9.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may
need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the
output capacitor is not desired.
If the grounding scheme shown is used via a connection to a different layer to route to the ENA pin.
8
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PH
BOOT
CAPACITOR
OUTPUT
INDUCTOR
RESISTOR
DIVIDER
VOUT
BOOT
PH
NC
VIN
NC
GND
VSENSE
ENA
OUTPUT
FILTER
CAPACITOR
Route feedback
trace under the output
filter capacitor or on
the other layer.
CATCH
DIODE
INPUT
INPUT
BULK
BYPASS
CAPACITOR FILTER
Vin
TOPSIDE GROUND AREA
VIA to Ground Plane
Signal VIA
Figure 9. Design Layout
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0.050
SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013
0.026
0.220
0.080
All dimensions in inches
Figure 10. TPS5420 Land Pattern
Application Circuits
Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output
current at a nominal output voltage of 5 V.
U1
TPS5420D
10 V - 35 V
7
VIN
ENA
C1
4.7 mF
C4
4.7 mF
VIN
5 ENA
2 NC
3 NC
6 GND
BOOT
1
C2
0.01 mF
TP5
PH 8
VSNS 4
L1
33 mH
5V
VOUT
D1
B340A
+
C3
100 mF
(See Note A)
R1
10 kW
R2
3.24 kW
A.
C3 = Tantalum AVX TPSD107M010R0080
Figure 11. Application Circuit, 10-V — 35 V to 5-V
10
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Design Procedure
The following design procedure can be used to select component values for the TPS5420. Alternately, the
Designer Software may be used to generate a complete design. The Designer Software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
To
•
•
•
•
•
•
begin the design process, a few parameters must be determined. The designer must know the following:
Input voltage range
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
Design Parameters
For this design example, use the following as the input parameters:
(1)
DESIGN PARAMETER (1)
EXAMPLE VALUE
Input voltage range
10 V to 36 V
Output voltage
5V
Input ripple voltage
300 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating frequency
500 kHz
As an additional constraint, the design is set up to be small size and low component height.
Switching Frequency
The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.
Input Capacitors
The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor is 10 μF. A high quality ceramic type X5R or X7R is
required. For some applications, a smaller value decoupling capacitor may be used, if the input voltage and
current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple. For this design, two 4.7 μF capacitors, C1 and C4 are used to allow for smaller 1812 case size
to be used while maintaining a 50 V rating.
This input ripple voltage can be approximated by Equation 2 :
IOUT(MAX) x 0.25
+ IOUT(MAX) x ESRMAX
DVIN =
CBULK x ƒSW
(
)
(2)
Where IOUT(MAX) is the maximum load current, f SW is the switching frequency, CI is the input capacitor value and
ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this is approximated by
Equation 3:
I
OUT(MAX)
I
+
CIN
2
(3)
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In this example, the calculated input ripple voltage is 118 mV, and the RMS ripple current is 1.0 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors
are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actual
measured input ripple voltage may be larger than the calculated value due to the output impedance of the input
voltage source and parasitics associated with the layout.
CAUTION
The maximum ratings for voltage and current are not to be exceeded under any
circumstance.
Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located within
approximately 2 inches from the input voltage source. The value for this capacitor is not critical but it should be
rated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripple
voltage is acceptable.
Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internally
compensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:
LMIN =
(
VOUT x VIN(MAX) - VOUT
)
VIN(max) x KIND x IOUT x FSW x 0.8
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the peak to
peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current,
and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using
the TPS5420, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages is obtained when paired with the
proper output capacitor, the peak switch current is below the current limit set point, and low load currents can be
sourced before discontinuous operation.
For this design example, use KIND = 0.2, and the minimum inductor value is 27 μH. The standard value used in
this design is 33 μH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:
I
L(RMS)
+
Ǹ
I2
1
)
OUT(MAX) 12
ǒ
V
V
OUT
ǒVIN(MAX) * VOUTǓ
L
IN(MAX)
OUT
F
SW
0.8
Ǔ
2
(5)
and the peak inductor current can be determined using Equation 6:
(
)
VOUT x VIN(MAX) - VOUT
IL(PK) = IOUT(MAX) +
1.6 x VIN(MAX) x LOUT x FSW
(6)
For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The chosen
inductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 μH. It has a saturation current rating of
2.2 A and a RMS current rating of 2.7 A, which meets the requirements. Inductor values for use with the
TPS5420 are in the range of 10 μH to 100 μH.
12
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Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, it is recommended to keep the closed loop crossover frequency in the range
3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design
example, the intended closed loop crossover frequency is between 2590 Hz and 24 kHz, and below the ESR
zero of the output capacitor. Under these conditions, the closed loop crossover frequency is related to the LC
corner frequency as:
f CO +
f LC
2
85 VOUT
(7)
and the desired output capacitor value for the output filter to:
1
C OUT +
3357 L OUT f CO V OUT
(8)
For a desired crossover of 18 kHz and a 33-μH inductor, the calculated value for the output capacitor is 100 μF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:
1
ESR MAX +
2p C OUT f CO
(9)
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:
VPP(MAX) =
(
)
ESRMAX x VOUT x VIN(MAX) - VOUT
NC x VIN(MAX) x LOUT x FSW x 0.8
(10)
Where:
ΔVPP is the desired peak-to-peak output ripple.
NC is the number of parallel output capacitors.
FSW is the switching frequency.
The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is
zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and
54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:
ICOUT(RMS) =
1
Ö12
x
[
(
VOUT x VIN(MAX) - VOUT
)
VIN(MAX) x LOUT - FSW x 0.8 x NC
]
(11)
Where:
NC is the number of output capacitors in parallel.
FSW is the switching frequency.
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For this design example, a single 100-μF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is a AVX
TPSD107M010R0080, rated at 10 V with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This
capacitor results in a peak-to-peak output ripple of 26 mV using equation 10. An additional small 0.1-μF ceramic
bypass capacitor may also used, but is not included in this design.
Other capacitor types can be used with the TPS5420, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R1 1.221
R2 +
V
* 1.221
OUT
(12)
For any TPS5420 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.
Boot Capacitor
The boot capacitor should be 0.01 μF.
Catch Diode
The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak-to-peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode
parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating the
power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of
3 A, and a forward voltage drop of 0.5 V.
Additional Circuits
Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar to
those given for the design example, with a larger value output inductor and a lower closed loop crossover
frequency.
10 V - 21 V
VIN
ENA
C1
10 mF
U1
TPS5420D
7
5
2
3
6
VIN
BOOT
C2
0.01 mF
TP5
L1
27 mH
5V
1
VOUT
ENA
PH
NC
NC
VSNS
8
4
D1
B340A
+
C3
100 mF
(See Note A)
R1
10 kW
GND
R2
3.24 kW
A.
C3 = Tantalum AVX TPSD107M010R0080
Figure 12. 10-V — 21-V Input to 5-V Output Application Circuit
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Circuit Using Ceramic Output Filter Capacitors
Figure 13 shows an application circuit using all ceramic capacitors for the input and output filters which generates
a 3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design example,
except for the selection of the output filter capacitor values and the design of the additional compensation
components required to stabilize the circuit.
VIN 10-24 V
7
VIN
C1
4.7 mF
EN
5
2
U1
TPS5420D
VIN
ENA
BOOT
NC
L1
18 mH
C2
0.01 mF
PH
3.3 V
1
VOUT
8
D1
MRBS340
3
NC
VSNS 4
6
GND PwPd
9
C3
47 mF
R1
10 kW
C7
0.1 mF
C4
150 pF
C4
47 mF
R2
5.9 kW
C6
1800 pF
R3
549 W
Figure 13. Ceramic Output Filter Capacitors Circuit
Output Filter Component Selection
Using Equation 11, the minimum inductor value is 17.9 μH. A value of 18 μH is chosen for this design.
When using ceramic output filer capacitors, the recommended LC resonant frequency should be no more than
7 kHz. Since the output inductor is already selected at 18 μH, this limits the minimum output capacitor value to:
1
CO (MIN) ³
2
(2p x 7000) x LO
(13)
The minimum capacitor value is calculated to be 29 μF. For this circuit a larger value of capacitor yields better
transient response. Two 47 μF output capacitors are used for C3 and C4. It is important to note that the actual
capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to
3.3 V, minimizing this effect.
External Compensation Network
When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this
circuit, the external components are R3, C5, C6, and C7. To determine the value of these components, first
calculate the LC resonant frequency of the output filter:
1
FLC =
2p Ö LO x CO (EFF)
(14)
For this example the effective resonant frequency is calculated as 4109 Hz
The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the
overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole
and zero locations are given by the following equations:
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Fp1 = 500000 x
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VO
FLC
(15)
Fz1 = 0.7 x FLC
(16)
Fz2 = 2.5 x FLC
(17)
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated usingEquation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 426 Hz, Fz1 = 2708 Hz
and Fz2 = 8898 Hz, the values of R3, C6 and C7 are determined using Equation 18, Equation 19, and
Equation 20:
1
C7 =
2p x Fp1 x (R1 || R2)
(18)
1
2p x Fz1 x C7
1
C6 =
2p x Fz2 x R1
R3 =
(19)
(20)
For this design, using the closest standard values, C7 is 0.1 μF, R3 is 590 Ω, and C6 is 1800 pF. C5 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C5 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5420 or other wide voltage range devices, see
SLVA237 Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors
ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX + 0.87
ǒǒVINMIN * I OMAX
Ǔ
Ǔ ǒ
0.230 ) VD * I OMAX
Ǔ
RL * VD
(21)
Where:
VINMIN = minimum input voltage
IOMAX = maximum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN + 0.12
ǒǒVINMAX * I OMIN
Ǔ
Ǔ ǒ
0.110 ) VD * I OMIN
Ǔ
RL * VD
(22)
Where:
VINMAX = maximum input voltage
IOMIN = minimum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
checked to assure proper functionality.
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Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the TPS5420. These
designs are based on certain assumptions, and always select output capacitors within a limited range of ESR
values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the
TPS5420. Equation 23 gives the nominal frequency response of the internal voltage-mode type III compensation
network:
s
s
1)
1)
2p Fz1
2p Fz2
H(s) +
s
s
s
s
1)
1)
1)
2p Fp1
2p Fp2
2p Fp3
2p Fp0
(23)
ǒ
ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ ǒ
Ǔ
Ǔ ǒ
Ǔ
Where
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed forward gain and output filter characteristics,
the closed loop transfer function can be derived.
Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction Loss: Pcon = IOUT 2 x RDS(on) x VOUT / VIN
Switching Loss: Psw = VIN x IOUT x 0.01
Quiescent Current Loss: Pq = VIN x 0.01
Total Loss: Ptot = Pcon + Psw + Pq
Given TA => Estimated Junction Temperature: TJ = TA + Rth x Ptot
Given TJMAX = 125°C => Estimated Maximum Ambient Temperature: TAMAX = TJMAX – Rth x Ptot
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PERFORMANCE GRAPHS
The performance graphs in Figure 14 - Figure 20 are applicable to the circuit in Figure 11. TA = 25°C. unless
otherwise specified.
100
VI = 10.8 V
0.2
0.2
Output Regulation - %
90
85
VI = 18 V
VI = 19.8 V
80
Output Regulation - %
IO = 2 A
VI = 15 V
Efficiency - %
0.3
VI = 12 V
95
0.1
0
-0.1
-0.2
0
0.5
1
1.5
2
IO - Output Current - A
2.5
Figure 14. Efficiency vs. Output
Current
VIN = 100 mV/Div (AC Coupled)
PH = 5 V/Div
t - Time - 1 ms / Div
Figure 17. Input Voltage Ripple
and PH Node, IO = 3 A
3
0.1
IO = 0 A
0
-0.1
IO = 1 A
-0.2
-0.3
75
18
0.3
-0.3
0
0.5
1
1.5
2
2.5
3
IO - Output Current - A
0.5
1
1.5
2
2.5
3
VI - Input Voltage - V
Figure 15. Output Regulation %
vs. Output Current
VOUT = 20 mV/Div (AC Coupled)
Figure 16. Input Regulation % vs.
Input Voltage
VOUT = 50 mV/Div (AC Coupled)
IOUT = 500 mA/Div
PH = 5 V/Div
t - Time = 200 μs/Div
t - Time - 1 ms / Div
Figure 18. Output Voltage Ripple
and PH Node, IO = 3 A
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Figure 19. Transient Response,
Io Step 0.5 to 1.5 A
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VIN = 10 V/Div
ENA = 2 V/Div
VOUT = 2 V/Div
VOUT = 2 V/Div
t - Time = 5 ms/Div
t - Time = 5 ms/Div
Figure 20. Startup Waveform, VIN and VOUT
Figure 21. Startup Waveform, ENA and VOUT
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REVISION HISTORY
Changes from Original (April 2006) to Revision A
•
Added Note 3 to the ABSOLUTE MAXIMUM RATINGS table ............................................................................................. 2
Changes from Revision A (August 2006) to Revision B
•
20
Page
Replaced the DISSIPATION RATINGS with the THERMAL INFORMATION table ............................................................. 2
Changes from Revision D (January 2013) to Revision E
•
Page
Changed From: KIND = 0.2, and the minimum inductor value is 31 μH To: KIND = 0.2, and the minimum inductor
value is 27 μH ..................................................................................................................................................................... 12
Changes from Revision C (October 2007) to Revision D
•
Page
Added the Circuit Using Ceramic Output Filter Capacitors section .................................................................................... 15
Changes from Revision B (November 2006) to Revision C
•
Page
Page
Deleted SWIFT from the data sheet Title, Features, and Description .................................................................................. 1
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS5420D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS5420
TPS5420DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS5420
TPS5420DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS5420
TPS5420DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS5420
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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