TPS5420EVM-175

User's Guide SLVU163 – April 2006 TPS5420EVM-175 Regulator Evaluation Module 1 2 3 4 Contents Introduction .................................................................................................................. 1 Test Setup and Results .................................................................................................... 3 Board Layout ................................................................................................................ 8 Schematic and Bill of Materials .......................................................................................... 11 List of Figures 1 Measured Efficiency, TPS5420 ........................................................................................... 2 Load Regulation ............................................................................................................. 4 3 Line Regulation .............................................................................................................. 5 4 Load Transient Response, TPS5420 ..................................................................................... 5 5 Measured Loop Response, TPS5420, VIN = 25 V ..................................................................... 6 6 Measured Output Voltage Ripple, TPS5420 ............................................................................ 6 7 Input Voltage Ripple, TPS5420 ........................................................................................... 7 8 Power Up, VOUT Relative to VIN ........................................................................................ Start-Up Waveform, VOUT Relative to ENA ........................................................................... Top-Side Layout ............................................................................................................. Bottom-Side Layout (Looking From Top Side) ........................................................................ Top-Side Assembly........................................................................................................ TPS5420EVM-175 Schematic ........................................................................................... 7 9 10 11 12 13 4 8 9 10 11 12 List of Tables 1 1 Input Voltage and Output Current Summary ............................................................................ 2 2 TPS5420EVM-175 Performance Specification Summary ............................................................. 2 3 Output Voltages Available ................................................................................................. 3 4 EVM Connectors and Test Points ........................................................................................ 3 5 TPS5420EVM-175 Bill of Materials ..................................................................................... 13 Introduction This user's guide contains background information for the TPS5420 as well as support documentation for the TPS5420EVM-175 evaluation module (HPA175). Also included are the performance specifications, the schematic, and the bill of materials for the TPS5420EVM-175. PowerPAD is a trademark of Texas Instruments. SLVU163 – April 2006 Submit Documentation Feedback TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 1 Introduction 1.1 www.ti.com Background The TPS5420 dc/dc converter is designed to provide up to a 2-A continuous, 3-A peak output from an input voltage source of 5.5 V to 36 V. Rated input voltage and output current range for the evaluation module is given in Table 1. This evaluation module is designed to demonstrate the small printed-circuitboard areas that may be achieved when designing with the TPS5420 regulator and does not reflect the high input voltages that may be used when designing with this part. The switching frequency is internally set at a nominal 500 kHz. The high-side MOSFET is incorporated inside the TPS5420 package along with the gate drive circuitry. The low drain-to-source on resistance of the MOSFET allows the TPS5420 to achieve high efficiencies and helps to keep the junction temperature low at high output currents. The compensation components are provided internal to the integrated circuit (IC), whereas an external divider allows for an adjustable output voltage. Additionally, the TPS5420 provides an enable input. The absolute maximum input voltage is 36 V. Table 1. Input Voltage and Output Current Summary 1.2 EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE TPS5420EVM-175 VIN = 10 V to 36 V 0 A to 2 A Performance Specification Summary A summary of the TPS5420EVM-175 performance specifications is provided in Table 2. Specifications are given for an input voltage of VIN = 12 V and an output voltage of 5 V, unless otherwise specified. The TPS5420EVM-175 is designed and tested for VIN = 10 V to 36 V. The ambient temperature is 25°C for all measurements, unless otherwise noted. Maximum input voltage for the TPS5420EVM-175 is 36 V. Table 2. TPS5420EVM-175 Performance Specification Summary SPECIFICATION TEST CONDITIONS VIN voltage range MIN Output voltage set point VIN = 10 V to 36 V Line regulation IO = 1 A, VIN = 3 V - 6 V Load regulation VIN = 25 V, IO = 0 A to 2.5 A Voltage change IO = 0.75 A to 2.25 A 36 0 UNIT V V 2.5 A ±0.11% ±0.1% -40 mV 200 μs IO = 2.25 A to 0.75 A +40 mV 200 μs Loop bandwidth VIN = 25 V 25.0 kHz Phase margin VIN = 25 V 55 Input ripple voltage IO = 3 A Recovery time Voltage change Recovery time Output ripple voltage Output rise time Operating frequency Maximum efficiency 2 MAX 5.0 Output current range Load transient response TYP 10 VIN = 10 V, VO = 5 V, IO = 0.75 A TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 275 ° 300 mVpp 32 mVpp 7 ms 500 kHz 93.2% SLVU163 – April 2006 Submit Documentation Feedback Test Setup and Results www.ti.com 1.3 Modifications The TPS5420EVM-175 is designed to demonstrate the small size that can be attained when designing with the TPS5420. A few changes can be made to this module. 1.3.1 Output Voltage Set Point To change the output voltage of the EVM, it is necessary to change the value of resistor R2. Changing the value of R2 can change the output voltage above 1.25 V. The value of R2 for a specific output voltage can be calculated using Equation 1. 1.221 V R2 + 10 kW V * 1.221 V O (1) Table 3 lists the R2 values for some common output voltages. Note that VIN must be in a range so that the minimum on-time is greater than 200 ns, and the maximum duty cycle is less than 87%. The values given in Table 3 are standard values, not the exact value calculated using Equation 1. Table 3. Output Voltages Available 1.3.2 Output Voltage (V) R2 Value (kΩ) 1.8 21.5 2.5 9.53 3.3 5.90 5 3.24 Input Voltage Range The EVM is designed to operate from a 10-V to 36-V input voltage range. The TPS5420 is specified to operate over an input voltage range of 5.5 V to 36 V. 2 Test Setup and Results This section describes how to properly connect, set up, and use the TPS5420EVM-175 evaluation module. The section also includes test results typical for the TPS5420EVM-175 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up. 2.1 Input / Output Connections The TPS5420EVM-175 is provided with input/output connectors and test points as shown in Table 4. A power supply capable of supplying 2 A should be connected to J1 through a pair of 20 AWG wires. The load should be connected to J3 through a pair of 20 AWG wires. The maximum load current capability should be 2 A. Wire lengths should be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP3 is used to monitor the output voltage with TP4 as the ground reference. Table 4. EVM Connectors and Test Points Reference Designator Function J1 VIN, 10 V to 36 V J2 OUT, 5 V at 2 A maximum JP1 2-pin header for enable. Connect EN to ground to disable, open to enable. TP1 VIN test point at VIN connector TP2 GND test point at VIN TP3 Output voltage test point at OUT connector TP4 GND test point at OUT connector TP5 Test point between voltage divider network and R3. Used for loop response measurements. TP6 PH test point SLVU163 – April 2006 Submit Documentation Feedback TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 3 Test Setup and Results 2.2 www.ti.com Efficiency The TPS5420EVM-175 efficiency peaks at load current of about 0.75 A, and then decreases as the load current increases towards full load. Figure 1 shows the efficiency for theTPS5420EVM-175 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs. EFFICIENCY vs OUTPUT CURRENT 100 VIN = 20 V Efficiency - % 95 VIN = 10 V VIN = 15 V VIN = 25 V 90 85 VIN = 30 V VIN = 36 V 80 75 1.5 1 0.5 IO - Output Current - A 0 2 Figure 1. Measured Efficiency, TPS5420 2.3 Output Voltage Regulation The output voltage load regulation of the TPS5420EVM-175 is shown in Figure 2; the output voltage line regulation is shown in Figure 3. Measurements are given for an ambient temperature of 25°C. LOAD REGULATION vs OUTPUT CURRENT 0.30 Output Regulation - % 0.20 0.10 0 -0.10 -0.20 -0.30 0 0.5 1 1.5 IO - Output Current - A 2 Figure 2. Load Regulation 4 TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated SLVU163 – April 2006 Submit Documentation Feedback Test Setup and Results www.ti.com LINE REGULATION vs INPUT VOLTAGE 0.30 Output Regulation - % 0.20 IO = 1 A 0.10 IO = 0 A 0 IO = 2 A -0.10 -0.20 -0.30 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VI - Input Voltage - A Figure 3. Line Regulation 2.4 Load Transients The TPS5420EVM-175 response to load transients is shown in Figure 4. The current step is from 25% to 75% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. VOUT = 50 mV/Div (AC Coupled) IOUT = 500 mA/Div t - Time = 200 μs/Div Figure 4. Load Transient Response, TPS5420 SLVU163 – April 2006 Submit Documentation Feedback TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 5 Test Setup and Results 2.5 www.ti.com Loop Characteristics The TPS5420EVM-175 loop-response characteristics are shown in Figure 5 . Gain and phase plots are shown for VIN voltage of 25 V and a 1-A load current. MEASURED LOOP RESPONSE 70 210 60 180 150 50 Phase Gain - dB 90 30 Gain 20 60 10 30 0 0 -10 -30 -20 -60 -30 10 100 1k 10 k f - Frequency - Hz 100 k Phase - Deg 120 40 -90 1M Figure 5. Measured Loop Response, TPS5420, VIN = 25 V 2.6 Output Voltage Ripple The TPS5420EVM-175 output voltage ripple is shown in Figure 6. The input voltage is VIN = 25 V for the TPS5420. Output current is the rated full load of 2 A. Voltage is measured directly across output capacitors. VO = 10 mV/div (ac Coupled) PH = 10 mV/div Time = 1 ms/div Figure 6. Measured Output Voltage Ripple, TPS5420 6 TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated SLVU163 – April 2006 Submit Documentation Feedback Test Setup and Results www.ti.com 2.7 Input Voltage Ripple The TPS5420EVM-175 input voltage ripple is shown in Figure 7. The input voltage is VIN = 10 V for the TPS5420. Output current for each device is at full rated load of 2 A. VO = 100 mV/div (ac Coupled) PH = 10 V/div Time = 1 ms/div Figure 7. Input Voltage Ripple, TPS5420 2.8 Powering Up The TPS5420EVM-175 start-up waveforms are shown in Figure 8 and Figure 9. In Figure 8 the top trace shows VIN whereas the bottom trace shows VOUT. VIN increases from 0 V toward 25 V. When the input voltage reaches the internally set UVLO threshold voltage of 5.3 V, the slow-start sequence begins. The internal reference begins to ramp up linearly at the internally set slow-start rate towards 1.221 V, and the output ramps up toward the set voltage of 5 V. The output may be inhibited by using a jumper at JP1 to tie ENA to GND. When the jumper is removed, ENA is released and the slow-start sequence begins as shown in Figure 9. The top trace shows the ENA signal and the bottom trace shows VOUT. When the ENA voltage reaches the enable-threshold voltage of 1.06 V, the start-up sequence begins as described above. VIN = 10 V/Div VOUT = 2 V/Div t - Time = 5 ms/Div Figure 8. Power Up, VOUT Relative to VIN SLVU163 – April 2006 Submit Documentation Feedback TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 7 Board Layout www.ti.com ENA = 2 V/Div VOUT = 2 V/Div t - Time = 5 ms/Div Figure 9. Start-Up Waveform, VOUT Relative to ENA 3 Board Layout This section provides a description of the TPS5420EVM-175 board layout and layer illustrations. 3.1 Layout The board layout for the TPS5420EVM-175 is shown in Figure 10 through Figure 12. The top-side layer of the TPS5420EVM-175 is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper. The top layer contains the main power traces for VIN, OUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS5420 and a large area filled with ground. The bottom layer contains ground and some signal routing. The top and bottom and internal ground traces are connected with multiple vias placed around the board including four vias directly under the TPS5420 device to provide a thermal path from the PowerPAD™ land to ground. The input decoupling capacitors (C1 and C4) and bootstrap capacitor (C3) are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, adjacent to the output capacitor C3. 8 TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated SLVU163 – April 2006 Submit Documentation Feedback Board Layout www.ti.com Figure 10. Top-Side Layout SLVU163 – April 2006 Submit Documentation Feedback TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 9 Board Layout www.ti.com Figure 11. Bottom-Side Layout (Looking From Top Side) 10 TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated SLVU163 – April 2006 Submit Documentation Feedback Schematic and Bill of Materials www.ti.com Figure 12. Top-Side Assembly 4 Schematic and Bill of Materials The TPS5420EVM-175 schematic and bill of materials are presented in this section. SLVU163 – April 2006 Submit Documentation Feedback TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 11 Schematic and Bill of Materials 4.1 www.ti.com Schematic + The schematic for the TPS5420EVM-175 is shown in Figure 13. Figure 13. TPS5420EVM-175 Schematic 12 TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated SLVU163 – April 2006 Submit Documentation Feedback Schematic and Bill of Materials www.ti.com 4.2 Bill of Materials The bill of materials for the TPS5420EVM-175 is given by Table 5. Table 5. TPS5420EVM-175 Bill of Materials Count Size Part Number MFR 2 C1, C4 REF DES 4.7 μF Value Capacitor, Ceramic, 50V, X7R, 20% 1812 C4532X5R1H475MT TDK 1 C2 0.01 μF Capacitor, Ceramic, 50V, X7R, 10% 0603 C1608X7R1H103K TDK 1 C3 100 μF Capacitor, Tantalum, 10V, 20% 7343(D) TPSD107M010R0080 AVX 1 D1 Diode, Schottky, 3A, 40V SMA B340A Diodes Inc 2 J1, J2 Terminal Block, 2 pin, 6A, 3,5mm 0.27 x 0.25 ED1514 OST 1 JP1 Header, 2-pin, 100mil spacing, (36-pin strip) 0.100 x 2 PTC36SAAN Sullins 1 L1 33 μH Inductor, SMT, 2.2A, 75milliohm 0.484 x 0.484 MSS1260-333 Coilcraft 1 R1 10.0 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R2 3.24 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R3 0 Resistor, Chip, 1/16W, 1% 0603 Std Std 4 TP1, TP3, TP5, TP6 Test Point, Red, Thru Hole Color Keyed 0.100 x 0.100 5000 Keystone 2 TP2, TP4 Test Point, Black, Thru Hole Color Keyed 0.100 x 0.100 5001 Keystone 1 U1 IC, Switching Step-Down Regulator, 36V, 2A SO8 TPS5420D TI 1 – PCB, 1.95 In x 1.95 In x 0.062 In HPA175 Any 1 – Shunt, 100-mil, Black 929950-00 3M SLVU163 – April 2006 Submit Documentation Feedback Description 0.100 TPS5420EVM-175 Regulator Evaluation Module Copyright © 2006, Texas Instruments Incorporated 13 EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. 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