TPS54225TPWPRQ1

TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com TM 4.5V to 18V Input, 2-A Synchronous Step-Down SWIFT Converter Check for Samples: TPS54225-Q1 FEATURES 1 • • 23 • • • • • • • • • • • • Qualified for Automotive Applications D-CAP2™ Mode Enables Fast Transient Response Low Output Ripple and Allows Ceramic Output Capacitor Wide VCC Input Voltage Range: 4.5 V to 18 V Wide VIN Input Voltage Range: 2 V to 18 V Output Voltage Range: 0.76 V to 5.5 V Highly Efficient Integrated FET’s Optimized for Lower Duty Cycle Applications - 160 mΩ (High Side) and 110 mΩ (Low Side) High Efficiency, less than 10 μA at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start Pre-Biased Soft Start 700-kHz Switching Frequency (fSW) Cycle-By-Cycle Overcurrent Limit Power Good Output APPLICATIONS DESCRIPTION The TPS54225-Q1 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54225-Q1 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54225-Q1 uses the D-CAP2™ mode control which provides a fast transient response with no external compensation components. The TPS54225-Q1 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54225-Q1 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C. • Wide Range of Applications for Low Voltage System – Digital TV Power Supply – High Definition Blu-ray Disc™ Players – Networking Home Terminal – Digital Set Top Box (STB) space VOUT (50 mV/div) IOUT (1 A/div) 100 ms/div 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2, PowerPAD are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA PACKAGE –40°C to 105°C (1) (2) (3) (2) (3) PowerPAD™ (HTSSOP) – PWP (14 Pins) ORDERABLE PART NUMBER TOP-SIDE MARKING TPS54225TPWPRQ1 54225Q1 Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. All package options have Cu NIPDAU lead/ball finish. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 20 V VBST –0.3 to 26 V VBST (vs SW1, SW2) –0.3 to 6.5 V VFB, VO, SS, PG –0.3 to 6.5 V –2 to 20 V VIN, VCC, EN VI Input voltage range SW1, SW2 –3 to 20 V VREG5 –0.3 to 6.5 V PGND1, PGND2 –0.3 to 0.3 V SW1, SW2 (10 ns transient) VO Output voltage range Vdiff Voltage from GND to POWERPAD ESD rating Electrostatic discharge –0.2 to 0.2 V Human Body Model (HBM) 2 kV Charged Device Model (CDM) 1 kV TJ Operating junction temperature –40 to 150 °C Tstg Storage temperature –55 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS54225-Q1 THERMAL METRIC (1) PWP UNITS 14 PINS θJA Junction-to-ambient thermal resistance 55.6 θJCtop Junction-to-case (top) thermal resistance 51.3 θJB Junction-to-board thermal resistance 26.4 ψJT Junction-to-top characterization parameter 1.8 ψJB Junction-to-board characterization parameter 20.6 θJCbot Junction-to-case (bottom) thermal resistance 4.3 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply input voltage range 4.5 18 V VIN Power input voltage range 2 18 V VBST –0.1 24 VBST (vs SW1, SW2) –0.1 5.7 SS, PG –0.1 5.7 EN –0.1 18 VO, VFB –0.1 5.5 SW1, SW2 –1.8 18 VI Input voltage range –3 18 PGND1, PGND2 –0.1 0.1 SW1, SW2 (10 ns transient) V VO Output voltage range VREG5 –0.1 5.7 V IO Output current range IVREG5 0 10 mA TA Operating free-air temperature –40 105 °C TJ Operating junction temperature –40 125 °C TYP MAX UNIT ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VCC, VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SUPPLY CURRENT IVCC Operating - non-switching supply current VCC current, TA = 25°C, EN = 5 V, VFB = 0.8 V 800 1200 μA IVCCSDN Shutdown supply current VCC current, TA = 25°C, EN = 0 V 1.8 10 μA LOGIC THRESHOLD VENH EN high-level input voltage EN VENL EN low-level input voltage EN 2 V 0.4 V VFB VOLTAGE AND DISCHARGE RESISTANCE VFB Threshold voltage TA = 25°C, VO = 1.05 V 757 TA = 0°C to 85°C, VO = 1.05 V (1) 753 777 TA = -40°C to 85°C, VO = 1.05 V (1) 751 780 IVFB Input current VFB = 0.8 V, TA = 25°C RDischg VO discharge resistance EN = 0 V, VO = 0.5 V, TA = 25°C 765 773 mV 0 ±0.1 μA 50 100 Ω 5.5 5.7 V 20 mV 100 mV VREG5 OUTPUT VVREG5 Output voltage TA = 25°C, 6 V < VCC < 18 V, 0 < IVREG5 < 5 mA VLN5 Line regulation 6 V < VCC < 18 V, IVREG5 = 5 mA VLD5 Load regulation 0 mA < IVREG5 < 5 mA IVREG5 Output current VCC = 6 V, VREG5 = 4 V, TA = 25°C RDS(on)h High side switch resistance RDS(on)l Low side switch resistance 5.3 70 mA 25°C, VBST - SW1, SW2 = 5.5 V 160 mΩ 25°C 110 mΩ MOSFET CURRENT LIMIT Iocl Current limit LOUT = 2.2µH (1) 2.5 3.1 4.5 A THERMAL SHUTDOWN TSDN (1) Thermal shutdown threshold Shutdown temperature Hysteresis (1) (1) 150 25 °C Specified by Design (not production tested). Copyright © 2011, Texas Instruments Incorporated 3 TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VCC, VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ON-TIME TIMER CONTROL tON On time VIN = 12 V, VO = 1.05 V 145 tOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns 2.6 ns SOFT START ISSC Charge current VSS = 0 V 1.4 2 ISSD Discharge current VSS = 0.5 V 0.1 0.2 VFB rising (good) 85 90 μA mA POWER GOOD VTHPG Threshold IPG Sink current VFB falling (fault) PG = 0.5 V 95 85 2.5 5 115 120 % mA OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold tOVPDEL Output OVP prop delay VUVP Output UVP trip threshold tUVPDEL Output UVP delay tUVPEN Output UVP enable delay OVP detect 125 UVP detect 65 Hysteresis 70 75 10 0.25 Relative to soft-start time % μs 5 % ms x 1.7 UVLO UVLO 4 UVLO threshold Wake up VREG5 voltage 3.55 3.8 4.05 Hysteresis VREG5 voltage 0.23 0.35 0.47 V Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com DEVICE INFORMATION PWP PACKAGE (TOP VIEW) 1 VO 2 VFB 3 VREG5 VCC 14 VIN 13 VBST 12 SW2 11 POWER PAD 4 SS 5 GND 6 PG PGND2 9 7 EN PGND1 8 SW1 10 PIN FUNCTIONS PIN NAME NO. DESCRIPTION VO 1 Connect to output of converter. This pin is used for On-Time Adjustment. VFB 2 Converter feedback input. Connect with feedback resistor divider. VREG5 3 5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND. SS 4 Soft-start control. A external capacitor should be connected to GND. GND 5 Signal ground pin PG 6 Open drain power good output EN 7 Enable control input PGND1, PGND2 SW1, SW2 8, 9 10, 11 Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC. Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparators. VBST 12 Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin. VIN 13 Power input and connected to high side NFET drain VCC 14 Supply input for 5 V internal linear regulator for the control circuitry PowerPAD™ Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND. Copyright © 2011, Texas Instruments Incorporated 5 TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com Functional Block Diagram -30% UV 14 VO VIN VIN OV 1 VCC 13 +20% VREG5 12 Control logic VBST Ref SS 1 shot SW VFB SGND 10 XCON VREG5 VREG5 Ceramic Capacitor 3 1mF VO 11 2 SS 9 4 8 SW Softstart ZC SS PGND 5 PGND PGND GND SW OCP SGND PG Ref 6 PGND VCC -10% UV VREG5 EN 7 EN Logic OV UVLO UVLO Protection Logic TSD REF Ref OVERVIEW The TPS54225-Q1 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM Operation The main control loop of the TPS54225-Q1 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one 6 Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 www.ti.com SLVSAV9 – JUNE 2011 shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control. PWM Frequency and Adaptive On-Time Control TPS54225-Q1 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54225-Q1 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage. The actual frequency may vary from 700 kHz depending on the off time, which is ended when the fed back portion of the output voltage falls to the VFBthreshold voltage. Soft Start and Pre-Biased Soft Start The soft start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 2 μA. C6(nF) • Vref C6(nF) • 0.765 Tss(ms) = − = − Iss(µA) 2 (1) A unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. Power Good The power good function is activated after soft start has finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is within –10% of the target value, internal comparators detect power good state and the power good signal becomes high. Rpg resister value, which is connected between PG and VREG5, is required from 20 kΩ to 150 kΩ. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 10 ms internal delay. Output Discharge Control The TPS54225-Q1 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. Current Protection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time, and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current Iout. If the measured voltage is above the voltage proportional to the current limit, then the device constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time. The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. Copyright © 2011, Texas Instruments Incorporated 7 TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com There are some important considerations for this type of over-current protection. The load current one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output under-voltage protection circuit to be activated. When the over current condition is removed, the output voltage will return to the regulated value. This protection is non-latching. Over/Undervoltage Protection The TPS54225-Q1 detects over and undervoltage conditions by monitoring the feedback voltage (VFB). This function is enabled after approximately 1.7 times the soft-start time.When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 250 μs, the device latches off both internal top and bottom MOSFET. UVLO Protection Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS54225-Q1 is shut off. This is protection is non-latching. Thermal Shutdown Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 150°C), the TPS54225-Q1 shuts off. This protection is non-latching. 8 Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS VCC TEMPERATURE vs JUNCTION TEMPERATURE VCC SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 1200 8 IVCCSDN - Shutdown Current - mA IVCC Supply Current - mA 1000 800 600 400 200 0 -50 0 50 100 TJ - Junction Temperature - °C 6 4 2 0 -50 150 0 50 100 TJ - Junction Temperature - °C Figure 1. Figure 2. EN CURRENT vs EN VOLTAGE 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT 100 150 1.1 VOUT - Output Voltage - V EN Input Current - mA 80 60 40 1.075 VI = 18 V 1.05 VI = 12 V VI = 5.5 V 1.025 20 0 0 5 10 15 EN Input Voltage - V Figure 3. Copyright © 2011, Texas Instruments Incorporated 20 1 0 0.5 1 1.5 Iout - Output Current - A 2 Figure 4. 9 TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE 1.05-V, 0-A TO 2-A-LOAD TRANSIENT RESPONSE 1.1 VOUT - Output Voltage - V VOUT - 50 mV/div 1.075 IO = 0 A 1.05 IO = 1 A IOUT - 2 A/div 1.025 100 ms/div 1 0 5 10 15 VIN - Input Voltage - V 20 Figure 5. Figure 6. START-UP WAVEFORM EFFICIENCY vs OUTPUT CURRENT 100 VO = 3.3 V EN - 10 V/div 90 VO = 2.5 V Efficiency - % 80 VOUT - 0.5 V/div VO = 1.8 V 70 60 PG - 5 V/div 50 400 ms/div Figure 7. 10 40 0 0.5 1 1.5 IOUT - Output Current - A 2 Figure 8. Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 900 fsw - Switching Frequency - kHz fsw - Switching Frequency - kHz 900 800 VO = 1.8 V 700 600 VO = 3.3 V 800 VO = 1.8 V 700 VO = 3.3 V 600 500 500 0 5 10 15 VIN - Input Voltage - V 20 0 0.5 1 1.5 IO - Output Current - A Figure 9. Figure 10. VOLTAGE RIPPLE AT OUTPUT VOLTAGE RIPPLE AT INPUT 2 VO = 1.05 V VO = 1.05 V VIN - 50 mV/div VO - 10 mV/div SW - 5 V/div Figure 11. Copyright © 2011, Texas Instruments Incorporated SW - 5 V/div Figure 12. 11 TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com DESIGN GUIDE Step By Step Design Procedure To • • • • • begin the design process, the following application parameters must be known: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple VIN 4.5 to 18V U1 TPS542225PWP 14 13 1 2 4 7 VCC SW1 VIN SW2 VO VBST VFB PG SS VREG5 EN PGND1 5 GND 10 VOUT 1.05V, 2A 11 12 6 3 8 PGND2 9 PwPd 15 Figure 13. Schematic Diagram Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1% tolerance or better divider resistors. Start by using Equation 2 and Equation 3 to calculate VOUT. To improve efficiency at light loads consider using larger value resistors, too high of resistance is more susceptible to noise and voltage errors from the VFB input current is more noticeable. For output voltage from 0.76 V to 2.5 V: R1 VOUT = 0.765 • 1 + − R2 ( ) (2) For output voltage over 2.5 V: R1 VOUT = (0.763 + 0.0017 • VOUT) • 1 + − R2 ( ) (3) Where: VOUT_SET = Target VOUT voltage Output Filter Selection The output filter used with the TPS54225-Q1 is an LC circuit. This LC filter has double pole at: FP = 12 1 2p LOUT ´ COUT (4) Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54225-Q1. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 1. Table 1. Recommended Component Values OUTPUT VOLTAGE (V) R1 (kΩ) R2 (kΩ) 1 6.81 1.05 1.2 (1) C4 (pF) (1) L1 (µH) C8 + C9 (µF) 22.1 2.2 22 - 68 8.25 22.1 2.2 22 - 68 12.7 22.1 2.2 22 - 68 1.8 30.1 22.1 10 - 47 3.3 22 - 68 2.5 49.9 22.1 10 - 47 3.3 22 - 68 3.3 73.2 22.1 10 - 47 3.3 22 - 68 5 121 22.1 10 - 47 4.7 22 - 68 Optional For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor (C4) in parallel with R1. The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 5, Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS current of Equation 7. VOUT VIN (max) - VOUT •  Ilp - p = V L •f IN (max) O SW Ilp - p Ilpeak = IO +  2 − 1 Ilp - p2 ILo(RMS) = IO2 + − 12 √ (5) (6) (7) For this design example, the calculated peak current is 2.23 A and the calculated RMS current is 2.01 A. The inductor used is a TDK SPM6530-2R2M100 with a peak current rating of 11.5 A and an RMS current rating of 11 A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54225-Q1 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 8 to determine the required RMS current rating for the output capacitor. VOUT • (VIN - VOUT) ICO(RMS) =− − √12 • VIN • LO • fSW (8) For this design two TDK C3216X5R0J226M 22 µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.271 A and each output capacitor is rated for 4 A. Input Capacitor Selection The TPS54225-Q1 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The capacitor voltage rating needs to be greater than the maximum input voltage. Copyright © 2011, Texas Instruments Incorporated 13 TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com Bootstrap Capacitor Selection A 0.1 µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommended to use a ceramic capacitor. VREG5 Capacitor Selection A 1.0 µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommended to use a ceramic capacitor. THERMAL INFORMATION This PowerPAD™ package incorporates an exposed thermal pad that is designed to be connected to an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating abilities, refer to Technical Breif, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004. The exposed thermal pad dimensions for this package are shown in the following illustration. 8 14 Thermal Pad 2.46 ° 7 1 2.31 Figure 14. Thermal Pad Dimensions 14 Copyright © 2011, Texas Instruments Incorporated TPS54225-Q1 SLVSAV9 – JUNE 2011 www.ti.com LAYOUT CONSIDERATIONS 1. Keep the input switching current loop as small as possible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device. 3. Keep analog and non-switching components away from switching components. 4. Make a single point connection from the signal ground to power ground. 5. Do not allow switching current to flow under the device. 6. Keep the pattern lines for VIN and PGND broad. 7. Exposed pad of device must be connected to PGND with solder. 8. VREG5 capacitor should be placed near the device, and connected PGND. 9. Output capacitor should be connected to a broad pattern of the PGND. 10. Voltage feedback loop should be as short as possible, and preferably with ground shield. 11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND. 12. Providing sufficient via is preferable for VIN, SW and PGND connection. 13. PCB pattern for VIN, SW, and PGND should be as broad as possible. 14. If VIN and VCC is shorted, VIN and VCC patterns need to be connected with broad pattern lines. 15. VIN Capacitor should be placed as near as possible to the device. Additional Thermal Vias FEEDBACK RESISTORS VCC INPUT BYPASS CAPACITOR VCC VCC VOUT BIAS CAP VFB VIN VREG5 VBST SS SW1 GND Connection to POWER GROUND on internal or bottom layer SLOW START CAP ANALOG GROUND TRACE PG EN VIN VIN INPUT BYPASS CAPACITOR SW2 PGND1 EXPOSED POWERPAD AREA BOOST CAPACITOR OUTPUT INDUCTOR PGND2 VOUT OUTPUT FILTER CAPACITOR Additional Thermal Vias To Enable Control POWER GROUND VIA to Ground Plane Etch on Bottom Layer or Under Component Figure 15. TPS54225-Q1 Layout Copyright © 2011, Texas Instruments Incorporated 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54225TPWPRQ1 ACTIVE HTSSOP PWP 14 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 54225Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of