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TPS54228
SLVSAU1E – MAY 2011 – REVISED AUGUST 2016
TPS54228 4.5-V to 18-V Input, 2-A Synchronous Step-Down Converter With Eco-Mode™
1 Features
3 Description
•
The TPS54228 device is an adaptive on-time DCAP2™ mode synchronous buck converter. The
TPS54228 enables system designers to complete the
suite of various end-equipment power bus regulators
with a cost effective, low component count, low
standby current solution. The main control loop for
the TPS54228 uses the D-CAP2™ mode control that
provides a fast transient response with no external
compensation components. The adaptive on-time
control supports seamless transition between PWM
mode at higher load conditions and Eco-Mode™
operation at light loads. Eco-Mode™ allows the
TPS54228 to maintain high efficiency during lighter
load conditions. The TPS54228 also has a proprietary
circuit that enables the device to adopt to both low
equivalent series resistance (ESR) output capacitors,
such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors. The device operates from 4.5-V
to 18-V VIN input. The output voltage can be
programmed between 0.76 V and 7 V. The device
also features an adjustable soft start time. The
TPS54228 is available in 8-pin SO , 8-pin SOIC, and
10-pin VSON packages, and is designed to operate
over the ambient temperature range of –40°C to
85°C.
1
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 7 V
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 155 mΩ (High-Side) and 108 mΩ (Low-Side)
High Efficiency, Less than 10 µA at Shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Prebiased Soft Start
700-kHz Switching Frequency (fSW)
Cycle-by-Cycle Overcurrent Limit
Auto-Skip Eco-Mode™ for High Efficiency at Light
Load
2 Applications
•
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminals
– Digital Set Top Boxes (STB)
Device Information(1)
PART NUMBER
TPS54228
PACKAGE
BODY SIZE (NOM)
HSOP (8)
4.89 mm × 3.90 mm
SOIC (8)
4.89 mm × 3.90 mm
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
TPS54228
TPS54228 Transient Response
Vout (50 mV/div)
Iout (1 A/div)
Copyright © 2016, Texas Instruments Incorporated
t - Time - 100 ms
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54228
SLVSAU1E – MAY 2011 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 8
Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 15
10.3 Thermal Considerations ........................................ 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table, see POA at the end of the data sheet........................................................................... 3
Changes from Revision C (March 2012) to Revision D
Page
•
Added the 10-pin DRC package to the data sheet ................................................................................................................ 1
•
Added the DRC package to the Device Information section .................................................................................................. 3
•
Added Figure 20 ................................................................................................................................................................... 16
Changes from Revision B (December 2011) to Revision C
•
Removed SWIFT™ from the data sheet title.......................................................................................................................... 1
Changes from Revision A (October 2011) to Revision B
•
2
Page
Added the 8-pin D package to the data sheet ....................................................................................................................... 1
Changes from Original (May 2011) to Revision A
•
Page
Page
Added REN - EN pin resistance to GND to the LOGIC THRESHOLD section of the ELECTRICAL
CHARACTERISTICS table ..................................................................................................................................................... 5
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SLVSAU1E – MAY 2011 – REVISED AUGUST 2016
5 Pin Configuration and Functions
DDA, D Package
8-Pin HSOP, SOIC
Top View
EN
1
VFB
2
DRC Package
10-Pin VSON
Top View
8
VIN
7
VBST
EN
1
10
VIN
VFB
2
9
VIN
VREG5
3
8
VBST
SS
4
7
SW
GND
5
6
SW
Thermal Pad
VREG5
3
6
SW
SS
4
5
GND
Not to scale
Thermal Pad
Not to scale
Pin Functions
PIN
NAME
I/O
DESCRIPTION
HSOP, SOIC
VSON
EN
1
1
I
Enable input control. EN is active high and must be pulled up to enable the
device.
VFB
2
2
I
Converter feedback input. Connect to output voltage with feedback resistor
divider.
VREG5
3
3
O
5.5-V power supply output. A capacitor (typical 1 µF) must be connected to
GND. VREG5 is not active when EN is low.
SS
4
4
I
Soft-start control. An external capacitor must be connected to GND.
GND
5
—
—
Ground pin. Power ground return for switching circuit. Connect sensitive SS and
VFB returns to GND at a single point.
GND
—
5
—
Ground pin. Connect sensitive SS and VFB returns to GND at a single point.
SW
6
6, 7
O
Switch node connection between high-side NFET and low-side NFET.
VBST
7
8
I
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor
between VBST and SW pins. An internal diode is connected between VREG5
and VBST.
VIN
8
9, 10
I
Input voltage supply pin.
Back side (1)
—
—
Thermal pad of the package. Must be soldered to achieve appropriate
dissipation. Must be connected to GND.
—
Back side
—
Thermal pad of the package. PGND power ground return of internal low-side
FET. Must be soldered to achieve appropriate dissipation.
Exposed
Thermal
Pad
(1)
DDA package only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
VIN, EN
–0.3
20
VBST
–0.3
26
VBST (transient, 10 ns)
–0.3
28
VBST (vs SW)
–0.3
6.5
VFB, SS
–0.3
6.5
SW
–2
20
SW (transient, 10 ns)
–3
22
VREG5
–0.3
6.5
GND
–0.3
0.3
UNIT
V
V
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range and VIN = 12 V (unless otherwise noted)
MIN
VIN
VI
Supply input voltage
Input voltage
VBST
–0.1
24
VBST (transient, 10 ns)
–0.1
27
VBST(vs SW)
–0.1
5.7
SS
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
GND
Output voltage, VREG5
IO
Output current, IVREG5
IOUT
Operating output current (1)
TA
Operating free-air temperature
(1)
4
MAX
18
SW (transient, 10 ns)
VO
NOM
4.5
UNIT
V
V
–3
21
–0.1
0.1
–0.1
5.7
V
0
10
mA
–40
2
A
85
°C
D package, VOUT > 5 V (see Figure 9 for temperature derating)
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6.4 Thermal Information
TPS54228
THERMAL METRIC (1)
DDA (SO)
D (SOIC)
DRC (VSON)
8 PINS
8 PINS
10 PINS
UNITS
RθJA
Junction-to-ambient thermal resistance
45.3
114.4
43.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.8
60.8
55.4
°C/W
RθJB
Junction-to-board thermal resistance
16.2
55.7
18.9
°C/W
ψJT
Junction-to-top characterization parameter
6.6
17.4
0.7
°C/W
ψJB
Junction-to-board characterization parameter
16
55.1
19.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.5
—
5.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range and VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating, non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
800
1200
µA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
5
10
µA
LOGIC THRESHOLD
VEN
REN
EN high-level input voltage
EN
EN low-level input voltage
EN
EN pin resistance to GND
VEN = 12 V
1.6
220
V
440
0.6
V
880
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
IVFB
VFB threshold voltage
VFB input current
TA = 25°C, VO = 1.05 V, IO = 10 mA,
Eco-Mode™ operation
770
TA = 25°C, VO = 1.05 V,
continuous mode operation
749
VFB = 0.8 V, TA = 25°C
mV
765
781
mV
0
±0.1
µA
5.5
5.7
V
25
mV
100
mV
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VLN5
Line regulation
6 V < VIN < 18 V, IVREG5 = 5 mA
VLD5
Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
Output current
VIN = 6 V, VREG5 = 4 V, TA = 25°C
5.2
60
mA
MOSFET
RDS(on)
High side switch resistance
Low side switch resistance
Iocl
Current limit
DDA and D packages 25°C, VBST – SW = 5.5 V
155
DRC package, 25°C, VBST – SW = 5.5 V
165
25°C
108
DDA and DRC packages, L out = 2.2 µH (1)
D package, L out = 2.2 µH
(1)
2.5
2.3
Shutdown temperature (1)
mΩ
3.3
4.7
A
3
4.5
A
165
TSDN
Thermal shutdown threshold
tON
On time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
260
310
ns
Soft-start charge current
VSS = 1 V
1.4
2
2.6
µA
Soft-start discharge current
VSS = 0.5 V
0.1
0.2
Wake up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.13
0.32
0.48
ISS
UVLO
(1)
Undervoltage lockout threshold
Hysteresis (1)
°C
35
ns
mA
V
Not production tested.
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6.6 Typical Characteristics
VIN = 12 V and TA = 25 °C (unless otherwise noted)
14
1000
12
Ivccsdn - Shutdown Current - mA
1200
ICC - Supply Current - mA
SS = 7 V
800
SS = open
600
400
200
10
VIN = 12 V
8
6
4
2
0
-50
0
50
100
TJ - Junction Temperature - °C
0
-50
150
0
Figure 1. VIN Current vs Junction Temperature
50
100
TJ - Junction Temperature - °C
Figure 2. VIN Shutdown Current vs
Junction Temperature
1.1
100
VIN = 18 V
90
VOUT - Output Voltage - V
80
EN - Input Current - mA
150
70
60
50
40
30
VI = 18 V
1.075
VI = 12 V
1.05
VI = 5 V
1.025
20
10
1
0
0
2
4
6
8
10
12
14
EN - Input Voltage - V
16
18
0
20
0.5
1
IOUT - Output Current - A
1.5
2
Figure 4. 1.05-V Output Voltage vs Output Current
Figure 3. EN Current vs EN Voltage
1.07
900
IO = 1 A
IO = 10 mA
fsw - Switching Frequency - kHz
850
VO - Output Voltage - V
1.06
IO = 1 A
1.05
1.04
800
VO = 3.3 V
VO = 2.5 V
VO = 1.8 V
750
VO = 1.5 V
700
650
600
VO = 5 V
VO = 1.05 V
550
VO = 1.2 V
500
450
400
1.03
0
5
10
VI - Input Voltage - V
15
20
Figure 5. 1.05-V Output Voltage vs Input Voltage
6
0
5
10
VI - Input Voltage - V
15
20
Figure 6. Switching Frequency vs Input Voltage
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Typical Characteristics (continued)
VIN = 12 V and TA = 25 °C (unless otherwise noted)
800
0.780
VO = 1.8 V
VI = 12 V
700
VO = 1.05 V
VFBTH - Vfb Voltage - V
fsw - Switching Frequency - kHz
0.775
600
500
VO = 3.3 V
400
300
0.770
0.765
0.760
200
0.755
100
0
0.01
0.1
1
IO - Output Current - A
10
0.750
-50
Figure 7. Switching Frequency vs Output Current
150
3.0
DDA package
D package
DRC package
2.5
Power Dissipation (W)
2.0
Output Current (A)
50
100
o
TJ - Junction Temperature - C
Figure 8. Vfb Voltage vs Junction Temperature
2.5
1.5
1.0
VOUT = 0.76 to 5 V
VOUT = 6.0 V
VOUT = 7.0 V
0.5
0.0
0
0
20
40
60
Ambient Temperature (°C)
80
2.0
1.5
1.0
0.5
100
0.0
20
G000
Figure 9. D Package Output Current
vs Ambient Temperature
40
60
80
Ambient Temperature (°C)
100
G001
Figure 10. Power Dissipation vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The TPS54228 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of lowESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
EN
EN
1
VIN
Logic
VIN
8
VREG5
Control Logic
Ref
+
SS
+ PWM
7
1 shot
VFB
SW
VO
6
-
2
VBST
XCON
ON
VREG5
VREG5
Ceramic
Capacitor
3
SGND
SS
SS
4
5
Softstart
+
ZC
-
PGND
SGND
SW
GND
PGND
+
OCP
-
SW
PGND
VIN
UVLO
VREG5
UVLO
REF
TSD
Protection
Logic
Ref
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7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS54228 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
8
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Feature Description (continued)
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS54228 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54228 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time, one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Auto-Skip Eco-Mode™ Control
The TPS54228 is designed with Auto-Skip Eco-Mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1
(VIN - VOUT )×VOUT
1
×
I OUT ( LL ) =
2 × L × fsw
VIN
(1)
7.3.4 Soft Start and Prebiased Soft Start
The soft-start function is adjustable. When the EN pin becomes high, 2-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start-up.
The equation for the slow start time is Equation 2. VFB voltage is 0.765 V and SS pin source current is 2 µA.
t
SS
(ms) =
C6(nF) x V
x 1.1 C6(nF) x 0.765 x 1.1
REF
=
I (mA)
2
SS
(2)
The TPS54228 contains a unique circuit to prevent current from being pulled from the output during start-up if the
output is prebiased. When the soft start commands a voltage higher than the prebias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal
mode operation.
7.3.5 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current, IOUT. The TPS54228 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
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Feature Description (continued)
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the overcurrent condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of overcurrent protection. The load current one half of the
peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the overcurrent condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.
7.3.6 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54228 is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
TPS54228 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS54228 can operate in their normal switching modes. Normal continuous conduction mode (CCM) occurs
when the minimum switch current is above 0 A. In CCM, the TPS54228 operates at a quasi-fixed frequency of
700 kHz.
7.4.2 Standby Operation
When the TPS54228 is operating in either normal CCM or forced CCM, it may be placed in standby by asserting
the EN pin low.
10
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SLVSAU1E – MAY 2011 – REVISED AUGUST 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54228 is typically used as step-down converters, which convert a voltage to a lower voltage, 4.5 V to
18 V. WEBENCH™ software is available to aid in the design and analysis of circuits.
8.2 Typical Application
U1
TPS54228
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Example Design Schematic
8.2.1 Design Requirements
Table 1 shows the parameters for this design example.
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage
4.5 V to 18 V
Output voltage
1.05 V
Output current
2A
Output voltage ripple
20 mVpp
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads, consider using larger value resistors. High resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ
ö
R1÷
V
= 0.765 x çç1 +
÷
OUT
çè
R2 ÷ø
(3)
8.2.2.2 Output Filter Selection
The output filter used with the TPS54228 is an LC circuit. This LC filter has double pole at:
F =
P
2p L
1
x COUT
OUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54228. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a
–40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces
the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The
inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is
located below the high frequency zero but close enough that the phase boost provided be the high frequency
zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended
in Table 2.
Table 2. Recommended Component Values
OUTPUT VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
C4 (pF) (1)
L1 (µH)
C8 + C9 (µF)
(1)
1
6.81
22.1
—
1.5 to 2.2
22 to 68
1.05
8.25
22.1
—
1.5 to 2.2
22 to 68
1.2
12.7
22.1
—
2.2
22 to 68
1.5
21.5
22.1
—
2.2
22 to 68
1.8
30.1
22.1
5 to 22
3.3
22 to 68
2.5
49.9
22.1
5 to 22
3.3
22 to 68
3.3
73.2
22.1
5 to 22
3.3
22 to 68
5
124
22.1
5 to 22
4.7
22 to 68
6.5
165
22.1
5 to 22
4.7
22 to 68
Optional
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feedforward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current, and the RMS or heating current rating must be greater than the calculated RMS current.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
- VOUT
V
V
OUT x IN(max)
I
=
IPP
V
L x f
IN(max)
O
SW
I
=I +
Ipeak
O
=
I
Lo(RMS)
12
(5)
I
lpp
2
I
2
O
(6)
+
1
2
I
12 IPP
(7)
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For this design example, the calculated peak current is 2.311 A and the calculated RMS current is 2.008 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54228 is intended for use
with ceramic or other low-ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(8)
For this design, two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.18 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS54228 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 8 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating must be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends using a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. TI
recommends using a ceramic capacitor.
8.2.3 Application Curves
EN (10 V/div)
Vout (50 mV/div)
VREG5 (5 V/div)
Iout (1 A/div)
Vout (0.5 V/div)
t - Time - 100 ms
t - Time - 1 ms
Figure 12. 1.05-V, Load Transient Response
Figure 13. Start-Up Wave Form
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100
100
VO = 3.3 V
VO = 2.5 V
90
VO = 3.3 V
90
80
VO = 2.5 V
70
VO = 1.8 V
Efficiency - %
Efficiency - %
80
70
60
60
50
VO = 1.8 V
40
30
20
50
10
40
0
0.5
1
IO - Output Current - A
1.5
2
0
0.001
0.01
IO - Output Current - A
0.1
Figure 15. Light Load Efficiency vs Output Current
Figure 14. Efficiency vs Output Current
VO = 1.05 V
Vo (10 mV/div)
VO = 50 mV / div (-950 mV dc offset)
SW = 10 V / div
SW (5 V/div)
Time = 1 µsec / div
t - Time - 400 ns
Figure 16. Voltage Ripple at Output (IO = 2 A)
Figure 17. DCM Voltage Ripple at
Output (IO = 30 mA)
VO = 1.05 V
VIN (50 mV/div)
SW (5 V/div)
t - Time - 400 ns
Figure 18. Voltage Ripple at Input (IO = 2 A)
9 Power Supply Recommendations
The TPS54228 is designed to operate from input supply voltage in the range of 4.5 V to 18 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 65%. Using that criteria, the minimum recommended input voltage is VO / 0.65.
14
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10 Layout
10.1 Layout Guidelines
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder (DDA package only).
8. VREG5 capacitor must be placed near the device, and connected PGND.
9. Output capacitor must be connected to a broad pattern of the PGND.
10. Voltage feedback loop must be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider, which is connected to the VFB pin, must be tied to SGND.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND must be as broad as possible.
14. VIN capacitor mus be placed as near as possible to the device.
10.2 Layout Examples
VIN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
BIAS
CAP
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
EN
VIN
VFB
VBST
VREG5
SW
SS
GND
BOOST
CAPACITOR
SLOW
START
CAP
Connection to
POWER GROUND
on internal or
bottom layer
ANALOG
GROUND
TRACE
EXPOSED
THERMAL PAD
AREA (DDA Package Only)
OUTPUT
INDUCTOR
VOUT
OUTPUT
FILTER
CAPACITOR
POWER GROUND
VIA to Ground Plane
Figure 19. PCB Layout
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Layout Examples (continued)
VIN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
EN
VIN
HIGH FREQUENCY
BYPASS
VIN CAPACITOR
VFB
VIN
VREG5
BIAS
CAP
SLOW
START
CAP
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VBST
SS
SW
GND
SW
BOOST
CAPACITOR
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
EXPOSED
THERMAL PAD
AREA
Connection to
POWER GROUND
on internal or
bottom layer
VOUT
POWER GROUND
VIA to Ground Plane
Figure 20. DRC Package PCB Layout
10.3 Thermal Considerations
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed-circuit board (PCB). After soldering, the PCB
can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly
to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached
to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SMLA004).
Figure 21 shows the exposed thermal pad dimensions for this package.
Figure 21. Thermal Pad Dimensions
16
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SLVSAU1E – MAY 2011 – REVISED AUGUST 2016
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package (SLMA002)
• PowerPAD™ Made Easy (SLMA004)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP2, Eco-Mode, WEBENCH, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
TPS54228D
Active
Production
SOIC (D) | 8
75 | TUBE
Yes
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228D.A
Active
Production
SOIC (D) | 8
75 | TUBE
Yes
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228D.B
Active
Production
SOIC (D) | 8
75 | TUBE
Yes
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DDA
Active
Production
SO PowerPAD
(DDA) | 8
75 | TUBE
Yes
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54228
TPS54228DDA.A
Active
Production
SO PowerPAD
(DDA) | 8
75 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54228
TPS54228DDA.B
Active
Production
SO PowerPAD
(DDA) | 8
75 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54228
TPS54228DDAR
Active
Production
SO PowerPAD
(DDA) | 8
2500 | LARGE T&R
Yes
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54228
TPS54228DDAR.A
Active
Production
SO PowerPAD
(DDA) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54228
TPS54228DDAR.B
Active
Production
SO PowerPAD
(DDA) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
54228
TPS54228DR
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DR.A
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DR.B
Active
Production
SOIC (D) | 8
2500 | LARGE T&R
Yes
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DRCR
Active
Production
VSON (DRC) | 10
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DRCR.A
Active
Production
VSON (DRC) | 10
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DRCR.B
Active
Production
VSON (DRC) | 10
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DRCT
Active
Production
VSON (DRC) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DRCT.A
Active
Production
VSON (DRC) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
54228
TPS54228DRCT.B
Active
Production
VSON (DRC) | 10
250 | SMALL T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
54228
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS54228DDAR
SO
PowerPAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TPS54228DR
SOIC
D
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TPS54228DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS54228DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54228DDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
TPS54228DR
SOIC
D
8
2500
364.0
364.0
27.0
TPS54228DRCR
VSON
DRC
10
3000
335.0
335.0
25.0
TPS54228DRCT
VSON
DRC
10
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS54228D
D
SOIC
8
75
517
7.87
635
4.25
TPS54228D.A
D
SOIC
8
75
517
7.87
635
4.25
TPS54228D.B
D
SOIC
8
75
517
7.87
635
4.25
TPS54228DDA
DDA
HSOIC
8
75
517
7.87
635
4.25
TPS54228DDA.A
DDA
HSOIC
8
75
517
7.87
635
4.25
TPS54228DDA.B
DDA
HSOIC
8
75
517
7.87
635
4.25
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DDA 8
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
A
SEATING PLANE
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
8X
B
4.0
3.8
NOTE 4
0.51
0.31
0.25
1.7 MAX
C A B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
3.4
2.8
0.25
GAGE PLANE
9
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.71
2.11
TYPICAL
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
9
SYMM
(1.3)
TYP
(3.4)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
( 0.2) TYP
VIA
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
9
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3 x 3, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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