TPS54231DG4

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 TPS54231 2-A, 28-V Input, Step-Down DC-DC Converter With Eco-mode™ 1 Features 3 Description • • • The TPS54231 device is a 2-V, 2-A non-synchronous buck converter that integrates a low RDS(on) high-side MOSFET. To increase efficiency at light loads, a pulse skipping Eco-mode™ feature is automatically activated. Furthermore, the 1-μA shutdown supply current allows the device to be used in battery powered applications. Current mode control with internal slope compensation simplifies the external compensation calculations and reduces component count while allowing the use of ceramic output capacitors. A resistor divider programs the hysteresis of the input undervoltage lockout. An overvoltage transient protection circuit limits voltage overshoots during startup and transient conditions. A cycle-bycycle current limit scheme, frequency fold back and thermal shutdown protect the device and the load in the event of an overload condition. The TPS54231 device is available in an 8-pin SOIC package that has been internally optimized to improve thermal performance. 1 • • • • • • • • • 3.5- to 28-V Input Voltage Range Adjustable Output Voltage Down to 0.8 V Integrated 80-mΩ High-Side MOSFET Supports up to 2 A Continuous Output Current High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ Fixed 570-kHz Switching Frequency Typical 1-μA Shutdown Quiescent Current Adjustable Slow-Start Limits Inrush Currents Programmable UVLO Threshold Overvoltage Transient Protection Cycle-by-Cycle Current Limit, Frequency Fold Back and Thermal Shutdown Protection Available in Easy-to-Use SOIC8 Package Supported by WEBENCH® Software Tool (www.TI.com/WEBENCH) Device Information(1) 2 Applications • • • Consumer Applications such as Set-Top Boxes, CPE Equipment, LCD Displays, Peripherals, and Battery Chargers Industrial and Car Audio Power Supplies 5-V, 12-V and 24-V Distributed Power Systems PART NUMBER TPS54231 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic Ren1 Efficiency EN VIN Ren2 VIN CI 100 90 TPS54231 80 CBOOT BOOT 70 VOUT PH SS COMP D1 CO RO1 C1 CSS C2 R3 Efficiency - % LO 60 50 40 VI = 12 V VI = 18 V VI = 24 V VI = 28 V VI = 5 V 30 VSENSE GND 20 RO2 10 0 0.01 VO = 3.3 V 0.1 1 10 IL - Load Current - A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 5 5 5 5 6 6 7 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application .................................................. 14 10 Power Supply Recommendations ..................... 24 11 Layout................................................................... 24 11.1 11.2 11.3 11.4 Layout Guidelines ................................................. Layout Example .................................................... Estimated Circuit Area .......................................... Electromagnetic Interference (EMI) Considerations ......................................................... 24 25 25 25 12 Device and Documentation Support ................. 26 12.1 12.2 12.3 12.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 13 Mechanical, Packaging, and Orderable Information ........................................................... 26 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2012) to Revision D • Page Added Handling Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1 Changes from Revision B (February 2012) to Revision C Page • Added 5.3 to the MAX column of the ELEC CHAR table, section CURRENT LIMIT ............................................................ 6 • Deleted Maximum Power Dissipation versus Junction Temperature graph......................................................................... 23 Changes from Revision A (March 2010) to Revision B Page • Removed SWIFT™ from the data sheet title.......................................................................................................................... 1 • Deleted Features Item: For SWIFT™ Documentation, See the TI Website at http://www.ti.com/swift.................................. 1 2 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 Changes from Original (October 2008) to Revision A Page • Changed the ABSOLUTE MAXIMUM RATINGS table, Input Voltage - EN pin max value From: 5V to 6V.......................... 5 • Added a new table to the Description - For additional design needs................................................................................... 14 • Changed Equation 9 for calculating ILPP ............................................................................................................................... 16 • Added new Equation 10 for calculating IL(RMS) ...................................................................................................................... 16 • Changed Equation 11 for calculating IL(PK) ........................................................................................................................... 16 • Added peak-to-peak output voltage ripple descriptive text following Equation 13 ............................................................... 17 • Changed Equation 14 for calculating IOUT(RMS) ..................................................................................................................... 17 • Changed Equation 16 for calculating FPO ............................................................................................................................. 18 • Changed Equation 25 for calculating RZ .............................................................................................................................. 19 • Changed Equation 28 for calculating RZ .............................................................................................................................. 19 • Changed Equation 29 and Equation 30 for calculating CZ and CP, respectively.................................................................. 20 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 3 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 6 Pin Configuration and Functions D Package 8-Pin SOIC Top View BOOT 1 8 PH VIN 2 7 GND EN 3 6 COMP SS 4 5 VSENSE Pin Functions PIN DESCRIPTION I/O NO. NAME 1 BOOT O A 0.1-μF bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this capacitor falls below the minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed. 2 VIN I This pin is the 3.5- to 28-V input supply voltage. 3 EN I This pin is the enable pin. To disable, pull below 1.25 V. Float this pin to enable. Programming the input undervoltage lockout with two resistors is recommended. 4 SS I This pin is slow-start pin. An external capacitor connected to this pin sets the output rise time. 5 VSENSE I This pin is the inverting node of the transconductance (gm) error amplifier. 6 COMP O This pin is the error-amplifier output and input to the PWM comparator. Connect frequency compensation components to this pin. 7 GND — Ground pin 8 PH O The PH pin is the source of the internal high-side power MOSFET. 4 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Input voltage MIN MAX VIN –0.3 30 EN –0.3 6 BOOT 38 VSENSE –0.3 3 COMP –0.3 3 SS –0.3 3 BOOT-PH Output voltage Source current Sink current V 8 PH –0.6 30 V PH (10 ns transient from ground to negative peak) –5 EN 100 μA BOOT 100 mA VSENSE 10 μA PH 6 A VIN 6 A COMP 100 SS 200 Operating junction temperature, TJ (1) UNIT –40 μA 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) Electrostatic discharge (1) (2) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) MIN MAX UNIT –65 150 °C –2 2 kV –500 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TJ MAX UNIT Operating Input Voltage on (VIN pin) 3.5 28 V Operating junction temperature –40 150 °C 7.4 Thermal Information THERMAL METRIC (1) D 8 PINS RθJA Junction-to-ambient thermal resistance 116.3 RθJC(top) Junction-to-case (top) thermal resistance 53.7 RθJB Junction-to-board thermal resistance 57.1 ψJT Junction-to-top characterization parameter 12.9 ψJB Junction-to-board characterization parameter 56.5 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 5 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 7.5 Electrical Characteristics TJ = –40°C to 150°C, VIN = 3.5 to 28 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Internal undervoltage lockout threshold Rising and falling Shutdown supply current EN = 0V, VIN = 12V, –40°C to 85°C 3.5 V 1 4 μA 75 110 μA 1.25 1.35 Operating – non switching supply current VSENSE = 0.85 V ENABLE AND UVLO (EN PIN) Enable threshold Rising and falling Input current Enable threshold – 50 mV -1 μA V Input current Enable threshold + 50 mV -4 μA VOLTAGE REFERENCE Voltage reference 0.772 0.8 0.828 BOOT-PH = 3 V, VIN = 3.5 V 115 200 BOOT-PH = 6 V, VIN = 12 V 80 150 V HIGH-SIDE MOSFET On resistance mΩ ERROR AMPLIFIER Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V Error amplifier DC gain (1) VSENSE = 0.8 V 800 μmhos V/V Error amplifier unity gain bandwidth (1) 5 pF capacitance from COMP to GND pins 2.7 MHz Error amplifier source/sink current V(COMP) = 1 V, 100-mV overdrive ±7 μA Switch current to COMP transconductance VIN = 12 V 9 A/V 100 mA 92 PULSE SKIPPING ECO-MODE Pulse skipping Eco-mode™ switch current threshold CURRENT LIMIT Current limit threshold VIN = 12 V 2.3 3.5 5.3 A THERMAL SHUTDOWN Thermal Shutdown 165 °C SLOW START (SS PIN) (1) Charge current V(SS) = 0.4 V 2 μA SS to VSENSE matching V(SS) = 0.4 V 10 mV Specified by design. 7.6 Switching Characteristics TJ = –40°C to 150°C, VIN = 3.5 to 28 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 400 570 740 kHz 105 130 ns SWITCHING FREQUENCY (1) 6 TPS54231 device switching frequency VIN = 12 V Minimum controllable on time VIN = 12 V, 25°C Maximum controllable duty ratio (1) BOOT-PH = 6 V 90% 93% Specified by design. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 7.7 Typical Characteristics 4 110 VIN = 12 V 105 TJ = 150°C EN = 0 V Isd - Shutdown Current - mA Rdson - On Resistance - mW 100 95 90 85 80 75 3 2 TJ = 25°C 1 TJ = -40°C 70 65 60 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 3 150 8 13 18 VI - Input Voltage - V 23 28 Figure 2. Shutdown Quiescent Current vs Input Voltage Figure 1. ON Resistance vs Junction Temperature 590 0.8240 VIN = 12 V 0.8180 Vref - Voltage Reference - V fsw - Oscillator Frequency - kHz 585 580 575 570 565 560 0.8060 0.8000 0.7940 0.7880 0.7820 555 550 -50 0.8120 -25 0 25 50 75 100 125 0.7760 -50 150 -25 0 TJ - Junction Temperature - °C 125 150 Figure 4. Voltage Reference vs Junction Temperature Figure 3. Switching Frequency vs Junction Temperature 7.50 140 VIN = 12 V VIN = 12 V 7.25 Minimum Controllable Duty Ratio - % Tonmin - Minimum Controllable On Time - ns 25 50 75 100 TJ - Junction Temperature - °C 130 120 110 100 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 5. Minimum Controllable ON Time vs Junction Temperature 7 6.75 6.50 6.25 6 5.75 5.50 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 6. Minimum Controllable Duty Ratio vs Junction Temperature Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 7 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com Typical Characteristics (continued) 4 2 1.90 -50 8 Current Limit Threshold - A ISS - Slow Start Charge Current - mA 2.10 TJ = 25°C TJ = -40°C 3.5 TJ = 150°C 3 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C 3 13 18 VI - Input Voltage - V Figure 7. SS Charge Current vs Junction Temperature Figure 8. Current-Limit Threshold vs Input Voltage Submit Documentation Feedback 8 23 28 Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 8 Detailed Description 8.1 Overview The TPS54231 device is a 28-V, 2-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant-frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54231 device has a pre-set switching frequency of 570 kHz. The TPS54231 device requires a minimum input voltage of 3.5 V for normal operation. The EN pin has an internal pullup current source that can be used to adjust the input-voltage undervoltage lockout (UVLO) with two external resistors. In addition, the pullup current provides a default condition when the EN pin is floating for the device to operate. The operating current is 75 μA (typical) when not switching and under no load. When the device is disabled, the supply current is 1 μA (typical). The integrated 80-mΩ high-side MOSFET allows for high-efficiency power-supply designs with continuous output currents up to 2 A. The TPS54231 device reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns the high-side MOSFET off when the voltage falls below a preset threshold of 2.1 V (typical). The output voltage can be stepped down to as low as the reference voltage. By adding an external capacitor, the slow-start time of the TPS54231 device can be adjustable which enables flexible output filter selection. To improve the efficiency at light load conditions, the TPS54231 device enters a special pulse skipping Ecomode when the peak inductor current drops below 100 mA (typical). The frequency foldback reduces the switching frequency during startup and overcurrent conditions to help control the inductor current. The thermal shut down provides the additional protection under fault conditions. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 9 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 8.2 Functional Block Diagram EN VIN 165 C Thermal Shutdown 1 mA 3 mA Shutdown Shutdown Logic 1.25 V Enable Threshold Enable Comparator Boot Charge ™ ECO-MODE Minimum Clamp Boot UVLO BOOT 2.1V Error Amplifier VSENSE 2 mA PWM Comparator Gate Drive Logic gm = 92 mA/V DC gain = 800 V/V BW = 2.7 MHz Voltage Reference SS 2 kW 0.8 V S Shutdown PWM Latch 9 A/V Current Sense R 80 mW Q S Slope Compensation PH Discharge Logic VSENSE Frequency Shift Oscillator GND COMP Maximum Clamp 8.3 Feature Description 8.3.1 Fixed-Frequency PWM Control The TPS54231 device uses a fixed-frequency, peak-current mode control. The internal switching frequency of the TPS54231 device is fixed at 570 kHz. 8.3.2 Voltage Reference (Vref) The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by scaling the output of a temperature-stable bandgap circuit. The typical voltage reference is designed at 0.8 V. 8.3.3 Bootstrap Voltage (BOOT) The TPS54231 device has an integrated boot regulator and requires a 0.1-μF ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R- or X5R-grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54231 device is designed to operate at 100% duty cycle as long as the BOOT-to-PH pin voltage is greater than 2.1 V (typical). 8.3.4 Enable and Adjustable Input Undervoltage Lockout (VIN UVLO) The EN pin has an internal pullup current-source that provides the default condition of the device while operating when the EN pin floats. 10 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 Feature Description (continued) The TPS54231 device is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. Using an external VIN UVLO to add hysteresis is recommended unless the VIN voltage is greater than (VOUT + 2 V). To adjust the VIN UVLO with hysteresis, use the external circuitry connected to the EN pin as shown in Figure 9. When the EN pin voltage exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate the resistor values required for the desired VIN UVLO threshold voltages. The VSTOP threshold should always be greater than 3.5 V. VIN Ren1 1 mA 3 mA + EN Ren2 1.25 V - Figure 9. Adjustable Input Undervoltage Lockout Ren1 = VSTART - VSTOP 3 mA where • • VSTART is the input start threshold voltage VSTOP is the input stop threshold voltage (1) VEN Ren2 = VSTART - VEN + 1 mA Ren1 where • VEN is the enable threshold voltage of 1.25 V (2) 8.3.5 Programmable Slow Start Using SS Pin Programming the slow-start time externally is highly recommended because no slow-start time is implemented internally. The TPS54231 device effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the reference voltage of the power supply that is fed into the error amplifier and regulates the output accordingly. A capacitor (CSS) on the SS pin to ground implements a slow-start time. The TPS54231 device has an internal pullup current-source of 2 μA that charges the external slow-start capacitor. Use Equation 3 to calculate the for the slow-start time (10% to 90%). CSS (nF ) ´ Vref (V ) TSS (ms ) = ISS (mA ) where • • Vref = 0.8 V ISS = 2 μA (3) The slow-start time should be set between 1 ms to 10 ms to ensure good startup behavior. The value of the slow-start capacitor should not exceed 27 nF. During normal operation, the TPS54231 device stops switching If during normal operation, the input voltage drops below the VIN UVLO threshold, the EN pin is pulled below 1.25 V, or a thermal shutdown event occurs. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 11 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com Feature Description (continued) 8.3.6 Error Amplifier The TPS54231 device has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation components are connected between the COMP pin and ground. 8.3.7 Slope Compensation To prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS54231 device adds a built-in slope compensation which is a compensating ramp to the switch-current signal. 8.3.8 Current-Mode Compensation Design To simplify design efforts using the TPS54231 device, the typical designs for common applications are listed in Table 1. For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when performing the stability analysis because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases. See the Detailed Design Procedure section for the detailed guidelines or use the WEBENCH Software tool (www.TI.com/WEBENCH). Table 1. Typical Designs (Refer to the Simplified Schematic) VIN (V) VOUT (V) ƒSW (kHz) Lo (μH) Co RO1 (kΩ) RO2 (kΩ) C2 (pF) C1 (pF) R3 (kΩ) 12 5 570 15 Ceramic 33 μF 10 1.91 47 1800 21 12 3.3 570 10 Ceramic 47μF 10 3.24 47 4700 21 12 1.8 570 6.8 Ceramic 100 μF 10 8.06 47 4700 21 12 0.9 570 4.7 Ceramic 100 μF, ×2 10 80.6 47 4700 21 12 5 570 15 Aluminum 330 μF, 160 mΩ 10 1.91 47 220 40.2 12 3.3 570 10 Aluminum 470 μF, 160 mΩ 10 3.24 47 220 21 12 1.8 570 6.8 SP 100 μF, 15 mΩ 10 8.06 47 4700 40.2 12 0.9 570 4.7 SP 220 μF, 12 mΩ 10 80.6 47 4700 40.2 8.3.9 Overcurrent Protection and Frequency Shift The TPS54231 device implements current mode control that uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. During each cycle the switch current and the COMP pin voltage are compared. When the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output current. The TPS54231 device provides robust protection during short circuits. Overcurrent runaway in possible in the output inductor during a short circuit at the output. The TPS54231 device solves this issue by increasing the off time during short-circuit conditions by lowering the switching frequency. The switching frequency is divided by 1, 2, 4, and 8 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The relationship between the switching frequency and the VSENSE pin voltage is listed in Table 2. Table 2. Switching Frequency Conditions SWITCHING FREQUENCY 12 VSENSE PIN VOLTAGE 570 kHz VSENSE ≥ 0.6 V 570 kHz / 2 0.6 V > VSENSE ≥ 0.4 V 570 kHz / 4 0.4 V > VSENSE ≥ 0.2 V 570 kHz / 8 0.2 V > VSENSE Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 8.3.10 Overvoltage Transient Protection The TPS54231 device incorporates an overvoltage transient-protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% × Vref, the high-side MOSFET is forced off. When the VSENSE pin voltage falls below 107% × Vref, the high-side MOSFET is enabled again. 8.3.11 Thermal Shutdown The device implements an internal thermal shutdown to protect the device if the junction temperature exceeds 165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. When the die temperature decreases below 165°C, the device reinitiates the power-up sequence. 8.4 Device Functional Modes 8.4.1 Eco-mode™ The TPS54231 device is designed to operate in pulse skipping Eco-mode at light load currents to boost light load efficiency. When the peak inductor current is lower than 100 mA (typical), the COMP pin voltage falls to 0.5 V (typical) and the device enters Eco-mode . When the device is in Eco-mode, the COMP pin voltage is clamped at 0.5 V internally which prevents the high-side integrated MOSFET from switching. The peak inductor current must rise above 100 mA for the COMP pin voltage to rise above 0.5 V and exit Eco-mode. Because the integrated current comparator catches the peak inductor current only, the average load current entering Eco-mode varies with the applications and external output filters. 8.4.2 Operation With VIN < 3.5 V The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device becomes active when the VIN pin passes the UVLO threshold. Switching begins when the slow-start sequence is initiated. 8.4.3 Operation With EN Control The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the device becomes active. Switching is enabled, and the slow-start sequence is initiated. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 13 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS54231 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 28 V to a lower voltage. WEBENCH software is available to aid in the design and analysis of circuits. For additional design needs, see the following devices: PARAMETER TPS54231 TPS54232 TPS54233 TPS54331 IO(max) 2A 2A 2A 3A TPS54332 3.5 A Input voltage range 3.5 to 28 V 3.5 to 28 V 3.5 to 28 V 3.5 to 28 V 3.5 to 28 V Switching frequency (typ) 570 kHz 1000 kHz 285 kHz 570 kHz 1000 kHz Switch current limit (min) 2.3 A 2.3 A 2.3 A 3.5 A 4.2 A Pin and Package 8SOIC 8SOIC 8SOIC 8SOIC 8SO PowerPAD™ 9.2 Typical Application L1 10 mH C4 0.1 mF C1 4.7 mF C2 4.7 mF C3 0.01 mF C8 47 mF R1 332 kW R2 68.1 kW C9 47 mF R6 3.24 kW C6 1000 pF C5 0.015 mF R3 29.4 kW R5 10.2 kW C7 47 pF Figure 10. Typical Application Schematic 9.2.1 Design Requirements For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters 14 DESIGN PARAMETER EXAMPLE VALUE Input voltage range 7 to 28 V Output voltage 3.3 V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 2A Operating Frequency 570 kHz Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 9.2.2 Detailed Design Procedure The following design procedure can be used to select component values for the TPS54231 device. Alternately, the WEBENCH Software can be used to generate a complete design. The WEBENCH Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. 9.2.2.1 Switching Frequency The switching frequency for the TPS54231 device is fixed at 570 kHz. 9.2.2.2 Output Voltage Set Point The output voltage of the TPS54231 device is externally adjustable using a resistor divider network. As shown in Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 4 and Equation 5. R5 ´ VREF R6 = VOUT - VREF (4) é R5 ù VOUT = VREF ´ ê +1ú ë R6 û (5) Select a value of R5 to be approximately 10 kΩ. Slightly increasing or decreasing the value of R5 can result in closer output-voltage matching when using standard value resistors. In this design, R4 = 10.2 kΩ and R = 3.24 kΩ, resulting in a 3.31-V output voltage. The 0-Ω resistor R4 is provided as a convenient location to break the control loop for stability testing. 9.2.2.3 Input Capacitors The TPS54231 device requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value can be used as long as all other requirements are met; however a value of 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be required, especially if the TPS54231 device circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design two 4.7-μF capacitors are used for the input decoupling capacitor. The capacitors are X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ, and the current rating is 3 A. Additionally, a small 0.01-μF capacitor is included for high frequency filtering. Use Equation 6 to calculate the input ripple voltage. IOUT(MAX) ´ 0.25 DVIN = + IOUT(MAX) ´ ESRMAX CBULK ´ fSW ( ) where • • • • IOUT(MAX) is the maximum load current ƒSW is the switching frequency CBULK is the bulk capacitor value ESRMAX is the maximum series resistance of the bulk capacitor (6) The maximum RMS ripple current must also be checked. For worst case conditions, use Equation 7 to calculate the maximum-RMS input ripple current, ICIN(RMS). IOUT(MAX) ICIN(RMS) = (7) 2 In this case, the input ripple voltage is 113 mV and the RMS ripple current is 1 A. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 15 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com NOTE The actual input voltage ripple is greatly affected by parasitics associated with the layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is listed in Table 3 and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be VIN(MAX) plus ΔVIN / 2. The selected bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both providing ample margin. The maximum ratings for voltage and current must not be exceeded under any circumstance. 9.2.2.4 Output Filter Components Two components need to be selected for the output filter, L1 and C2. Because the TPS54231 device is an externally compensated device, a wide range of filter component types and values can be supported. 9.2.2.4.1 Inductor Selection To calculate the minimum value of the output inductor, use Equation 8. LMIN = VOUT(MAX) ´ (VIN(MAX) - VOUT ) VIN(MAX) ´ KIND ´ IOUT ´ ƒSW where • KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current (8) In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher ESR output capacitors, KIND = 0.2 yields better results. For this design example, use KIND = 0.3 and the minimum inductor value is calculated as 8.5 μH. For this design, a large value was selected: 10 μH. For the output filter inductor, do not exceed the RMS current and saturation current ratings. Use Equation 9 to calculate the inductor ripple current (ILPP). ILPP = ( VOUT × VIN(MAX) - VOUT ) VIN(MAX) × LOUT ´ ƒSW ´ 0.8 (9) Use Equation 10 to calculate the RMS inductor current. IL(RMS) = I2 OUT(MAX) + 1 × I2LPP 12 (10) Use Equation 11 to calculate the peak inductor current. I IL(PK) = IOUT(MAX) + LPP 2 (11) For this design, the RMS inductor current is 2.008 A and the peak inductor current is 2.32 A. The selected inductor is a Coilcraft MSS1038-103NL, 10 μH. This inductor has a saturation current rating of 3.04 A and an RMS current rating of 2.90 A, which meets these requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors will have lower AC current and result in lower output voltage ripple, while smaller inductor values will increase AC current and output voltage ripple. In general, inductor values for use with the TPS54231 device are in the range of 6.8 μH to 47μH. 16 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 9.2.2.4.2 Capacitor Selection The important design factors for the output capacitor are DC voltage rating, ripple current rating, and equivalent series resistance (ESR). The DC voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. In general, keeping the closed-loop crossover frequency at less than 1/5 of the switching frequency is desired. With high switching frequencies such as the 570-kHz frequency of this design, internal circuit limitations of the TPS54231 device limit the practical maximum crossover frequency to about 25 kHz. In general, the closed-loop crossover frequency should be higher than the corner frequency determined by the load impedance and the output capacitor. Use Equation 12 to calculate the limits of the minimum capacitor value for the output filter. CO(MIN) = 1/ (2 ´ p ´ RO ´ FCO(MAX) ) where • • RO is the output load impedance (VO / IO) FCO(MAX) is the desired crossover frequency (12) For a desired maximum crossover of 25 kHz the minimum value for the output capacitor is approximately 3.6 μF. This value may not satisfy the output ripple voltage requirement. Use Equation 13 to estimate the output ripple voltage. é (D - 0.5) ù + RESR ú VOPP = ILPP ê ë 4 ´ ƒSW ´ CO û where • • • D = Duty cycle (VOUT / VIN) CO = Output Capacitance RESR = Equivalent series resistance of the output capacitors (13) The peak-to-peak output voltage ripple consists of two terms. The first term is because of the AC ripple current (ILPP) charging and discharging the output capacitance in each switching cycle and the second term is because of the AC ripple current in the ESR of the output capacitor. These two terms could be out of phase and may add or subtract depending on the duty cycle. The required capacitance and ESR of the output filter capacitor must be selected to meet the allowable output ripple voltage requirement as specified in the initial design parameters. Use Equation 14 to calculate the maximum RMS ripple current in the output capacitor. 1 ICOUT(RMS ) = × ILPP 12 (14) For this design example, two 47-μF ceramic output capacitors are selected for C8 and C9. These capacitors are TDK C3216X5R0J476M, rated at 6.3 V with a maximum ESR of 2 mΩ and a ripple current rating in excess of 3 A. The calculated total RMS ripple current is 184 mA (92 mA each) and the maximum total ESR required is 56 mΩ. These output capacitors exceed the requirements by a wide margin and result in a reliable, highperformance design. NOTE The actual capacitance in circuit may be less than the catalog value when the output is operating at the desired output of 3.3 V. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus half of the ripple voltage. Any derating amount must also be included. Other capacitor types work well with the TPS54231 device, depending on the needs of the application. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 17 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 9.2.2.5 Compensation Components The external compensation used with the TPS54231 device allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported. A Type II compensation scheme is recommended for the TPS54231 device. The compensation components are selected to set the desired closed-loop crossover frequency and phase margin for output filter components. The Type II compensation has the following characteristics: a DC gain component, a low frequency pole, and a mid frequency zero-pole pair. The required compensation components are a resistor, RZ, in series with a capacitor, RZ, from the COMP pin to ground and a capacitor, CP, in parallel with RZ and CZ from the COMP pin to ground. Use Equation 15 to calculate the DC gain. Vggm ´ VREF GDC = VO where • • Vggm = 800 VREF = 0.8 V (15) Use Equation 16 to calculate the low-frequency pole. FPO = 1/ (2 ´ p ´ ROA ´ CZ ) (16) Use Equation 17 to calculate the mid-frequency zero. FZ1 = 1/ (2 ´ p ´ R Z ´ CZ ) (17) Use Equation 18 to calculate the mid-frequency pole. FP1 = 1/ (2 ´ p ´ R Z ´ CP ) (18) The first step is to select the closed-loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency. However, for the TPS54231 device, not exceeding 25 kHz for the maximum closed-loop crossover frequency is recommended. The second step is to calculate the required gain and phase boost of the crossover network. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 19: Gain = - 20 log (2 ´ p ´ RSENSE ´ FCO ´ CO ) + 3 where • • • RSENSE = 1 Ω / 9 FCO = Closed-loop crossover frequency CO = Output capacitance (19) Use Equation 20 to calculate the phase loss. PL = a tan (2 ´ p ´ FCO ´ RESR ´ CO ) - a tan (2 ´ p ´ FCO ´ R O ´ C O ) - 10 where • • RESR = Equivalent series resistance of the output capacitor RO = VO / IO (20) Now that the phase loss is known, the required amount of phase boost to meet the phase margin requirement can be determined. Use Equation 21 to calculate the required phase boost. PB = (PM - 90 deg ) + PL where • • 18 PM = the desired phase margin PL = the phase loss calculated in Equation 20 Submit Documentation Feedback (21) Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 A zero-pole pair of the compensation network will be placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined by Equation 22. Use Equation 23 and Equation 24 to calculate the resultant zero and pole frequencies. ö æ PB k = tanç + 45 deg ÷ ø è 2 FZ 1 = (22) FCO k (23) FP1 = FCO ´ k (24) The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Because of the relationships of the pole and zero frequencies, use Equation 25 to calculate the value of RZ. 2 × p × FCO × VO × CO × ROA × 0.91 RZ = GMCOMP × Vggm × VREF where • • • • • • • VO = Output voltage CO = Output capacitance FCO = Desired crossover frequency ROA = 8.696 MΩ GMCOMP = 9 A/V Vggm = 800 VREF = 0.8 V (25) With the value of RZ known, use Equation 26 and Equation 27 to calculate the values of CZ and CP. CZ = CP = 1 2 ´ p ´ FZ 1 ´ Rz (26) 1 2 ´ p ´ FP1 ´ Rz (27) For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied which occurs in a DC-DC converter. The actual output capacitance may be as low as 41 μF. The combined ESR is approximately 0.002 Ω. The desired crossover frequency is 25 kHz. Using Equation 19 and Equation 20, the output stage gain and phase loss are equivalent as: Gain = 5.9 dB PL = –93.8 degrees For 60 degrees of phase margin, Equation 21 requires 63.9 degrees of phase boost. Use Equation 22, Equation 23, and Equation 24 to calculate the zero and pole frequencies of the following values: FZ1 = 5798 Hz FP1 = 107.8 kHz Use Equation 25 to calculate the value of RZ. Rz = 2 ´ p ´ 25000 ´ 3.3 ´ 41 ´ 10-6 ´ 8.696 ´ 106 × 0.91 = 29.2 × 103 W 9 ´ 800 ´ 0.8 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 (28) 19 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com With the value of RZ set to the standard value of 29.4 kΩ, the values of Cz and CP can be calculated using Equation 26 and Equation 27. 1 Cz = = 934 pF 2 ´ p ´ 5798 ´ 29400 (29) 1 Cp = = 50 pF 2 ´ p ´ 107800 ´ 29400 (30) Referring to Figure 10 and using standard values for R3, C6, and C7, the calculated values are as follows: R3 = 29.4 kΩ C6 = 1000 pF C7 = 47 pF Figure 16 shows the measured overall loop response for the circuit. The actual closed-loop crossover frequency is higher than intended at about 25 kHz which is primarily because of variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall, the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of line and load variability. 9.2.2.6 Bootstrap Capacitor Every TPS54231 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The bootstrap capacitor is located between the PH pin and BOOT pin. The bootstrap capacitor should be a highquality ceramic type with X7R or X5R grade dielectric for temperature stability. 9.2.2.7 Catch Diode The TPS54231 device is designed to operate using an external catch diode between the PH and GND pins. The selected diode must meet the absolute maximum ratings for the application. The Reverse voltage must be higher than the maximum voltage at the PH pin, which is VIN(MAX) + 0.5 V. The peak current must be greater than IOUT(MAX) plus on half the peak-to-peak inductor current. The forward-voltage drop should be small for higher efficiencies. The catch diode conduction time is (typically) longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the selected device is capable of dissipating the power losses. For this design, a Diodes, Inc. B240A is selected, with a reverse voltage of 40 V, forward current of 2 A, and a forward voltage drop of 0.5 V. 9.2.2.8 Output Voltage Limitations Because of the internal design of the TPS54231 device, any given input voltage has both upper and lower output voltage limits. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is with Equation 31. VO(MAX) = 0.91 × ((V IN(MIN) ) - IO(MAX) × RDS(on)max + VD ) - (I O(MAX) × RL ) - VD where • • • • VIN(MIN) = Minimum input voltage IO(MAX) = Maximum load current VD = Catch diode forward voltage RL = Output inductor series resistance (31) The equation assumes the maximum ON resistance for the internal high-side FET. The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns at 25°C junction temperature. 20 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 Use Equation 32 to calculate the approximate minimum output voltage for a given input voltage and minimum load current. VO(MIN) = 0.096 × ((V IN(MAX) ) - IO(MIN) × RDS(on)min + VD ) - (I O(MIN) × RL ) - VD where • • • • VIN(MAX) = Maximum input voltage IO(MIN) = Minimum load current VD = Catch diode forward voltage RL = Output inductor series resistance (32) The normal ON resistance for the high-side FET in Equation 32 is assumed. Equation 32 accounts for worst case variation of operating-frequency set point. Any design operating near the operational limits of the device should be carefully checked to ensure proper functionality. 9.2.2.9 Power Dissipation Estimate The following formulas show how to estimate the device power dissipation under continuous-conduction mode (CCM) operations. These formulas should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse-skipping Eco-mode. The device power dissipation includes: 1. Conduction loss: Pcon = IOUT2 × RDS(on) × VOUT / VIN where • • • • IOUT is the output current (A) RDS(on) is the on-resistance of the high-side MOSFET (Ω) VOUT is the output voltage (V) VIN is the input voltage (V) 2. Switching loss: Psw = 0.5 × 10-9 × VIN2 × IOUT × ƒSW where • ƒSW is the switching frequency (Hz) 3. Gate charge loss: Pgc = 22.8 × 10-9 × ƒSW 4. Quiescent current loss: Pq = 0.075 × 10-3 × VIN Therefore: Ptot = Pcon + Psw + Pgc + Pq where • Ptot is the total device power dissipation (W) For given TA : TJ = TA + Rth × Ptot where • • • TJ is the junction temperature (°C) TA is the ambient temperature (°C) Rth is the thermal resistance of the package (°C/W) For given TJMAX = 150°C: TAMAX = TJMAX– Rth × Ptot where • • TAMAX is maximum ambient temperature (°C) TJMAX is maximum junction temperature (°C) Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 21 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 9.2.3 Application Curves 100 100 90 90 80 80 Efficiency - % VIN = 28 V 60 70 Efficiency - % VIN = 15 V 70 VIN = 7 V VIN = 24 V 50 40 60 VIN = 7 V VIN = 24 V 50 40 30 30 20 20 10 10 0 0 0 0.25 0.5 0.75 1 1.25 IO - Output Current - A 1.5 1.75 0 2 0.02 0.04 0.06 0.08 0.1 0.12 0.14 IO - Output Current - A 0.16 0.18 0.2 Figure 12. Low Current Efficiency Figure 11. Efficiency 0.2 0.15 0.15 0.1 IO = 0 A IO = 1 A 0.1 Output Regulation - % Output Regulation - % VIN = 28 V VIN = 15 V VIN = 7 V VIN = 15 V 0.05 VIN = 24 V 0 VIN = 28 V -0.05 0.05 IO = 2 A 0 -0.05 -0.1 -0.1 0 0.25 0.5 0.75 1 1.25 IO - Output Current - A 1.5 1.75 5 2 10 15 20 VI - Input Voltage - V 25 30 Figure 14. Line Regulation Figure 13. Load Regulation 60 50 160 Gain 40 110 Phase Gain - dB 30 Load Current 60 20 10 10 0 -10 Phase - deg. Vout -40 -20 -30 10 Figure 15. Transient Response 22 Submit Documentation Feedback 100 1k 10k 100k f - Frequency - Hz -90 1M Figure 16. Loop Response Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 Vout Vin PI PI Figure 17. Output Ripple Figure 18. Input Ripple Figure 19. Startup Figure 20. Startup Relative to Enable Vin Vout 1.25 Vout VO - Output Voltage - V 1.15 1.05 IO = 1 A 0.95 IO = 2 A PH 0.85 0.75 3 Figure 21. Eco-mode 8 13 18 VI - Input Volatage - V 23 28 Figure 22. Typical Minimum Output Voltage vs Input Voltage Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 23 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 30 VO - Output Voltage - V 25 20 IO = 1 A 15 IO = 2 A 10 5 0 3 8 13 18 VI - Input Voltage - V 23 28 Figure 23. Typical Maximum Output Voltage vs Input Voltage 10 Power Supply Recommendations The device is designed to operate from an input-voltage supply range between 3.5 V and 28 V. This input supply should be well regulated. If the input supply is located more than a few inches from the converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice. 11 Layout 11.1 Layout Guidelines The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the anode of the catch diode. Figure 24 shows a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. The source of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top-side ground area must provide adequate heat dissipating area. The TPS54231 device uses a fused lead frame so that the GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of internal or back-side ground plane available, and the top-side ground area can be connected to these areas using multiple vias under or adjacent to the device to help dissipate heat. The additional external components can be placed approximately as shown. Obtain acceptable performance with alternate layout schemes may be possible, however this layout has been shown to produce good results and is intended as a guideline. 24 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 TPS54231 www.ti.com SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 11.2 Layout Example OUTPUT FILTER CAPACITOR TOPSIDE GROUND AREA Route BOOT CAPACITOR trace on other layer to provide wide path for topside ground Vout Feedback Trace OUTPUT INDUCTOR CATCH DIODE PH INPUT BYPASS CAPACITOR BOOT Vin UVLO RESISTOR DIVIDER VIN GND EN COMP SS VSENSE SLOW START CAPACITOR Thermal VIA BOOT CAPACITOR PH COMPENSATION NETWORK RESISTOR DIVIDER Signal VIA Figure 24. TPS54231 device Board Layout 11.3 Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 10 is 0.68 in2. This area does not include test points or connectors. 11.4 Electromagnetic Interference (EMI) Considerations As EMI becomes a rising concern in more and more applications, the internal design of the TPS54231 device takes measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used to lower the parasitics effects. To achieve the best EMI performance, external component selection and board layout are equally important. Follow the steps listed in the Detailed Design Procedure section to prevent potential EMI issues. Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 25 TPS54231 SLUS851D – OCTOBER 2008 – REVISED OCTOBER 2014 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support For the WEBENCH Software Tool, go to www.TI.com/WEBENCH. 12.2 Trademarks Eco-mode, SWIFT, PowerPAD are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54231 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54231D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 54231 TPS54231DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 54231 TPS54231DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 54231 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of