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TPS54232
SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
TPS54232 2-A, 28-V, 1-MHz, Step-Down DC-DC Converter With Eco-Mode™
1 Features
3 Description
•
•
•
The TPS54232 is a 28-V, nonsynchronous buck
converter that integrates a low RDS(on) high-side
MOSFET. To increase efficiency at light loads, a
pulse-skipping Eco-Mode feature is automatically
activated. Furthermore, the 1-μA shutdown supply
current allows the device to be used in batterypowered applications. Current mode control with
internal slope compensation simplifies the external
compensation calculations and reduces component
count while allowing the use of ceramic output
capacitors. A resistor divider programs the hysteresis
of the input undervoltage lockout. An overvoltage
transient protection circuit limits voltage overshoots
during startup and transient conditions. A cycle-bycycle current limit scheme, frequency fold back, and
thermal shutdown protect the device and the load in
the event of an overload condition. The TPS54232 is
available in an 8-pin SOIC package.
1
•
•
•
•
•
•
•
•
•
3.5-V to 28-V Input Voltage Range
Adjustable Output Voltage Down to 0.8 V
Integrated 80-mΩ High-Side MOSFET Supports
up to 2-A Continuous Output Current
High Efficiency at Light Loads with a PulseSkipping Eco-Mode™
Fixed 1-MHz Switching Frequency
Typical 1-μA Shutdown Quiescent Current
Adjustable Slow-Start Limits Inrush Currents
Programmable UVLO Threshold
Overvoltage Transient Protection
Cycle-by-Cycle Current Limit, Frequency Fold
Back and Thermal Shutdown Protection
Available in 8-Pin SOIC Package
Supported by WEBENCH® Software Tool
(http://www.ti.com/lsds/ti/analog/webench/overvie
w.page)
•
•
PART NUMBER
TPS54232
2 Applications
•
Device Information(1)
Consumer Applications such as Set-Top Boxes,
CPE Equipment, LCD Displays, Peripherals, and
Battery Chargers
Industrial and Car Audio Power Supplies
5-V, 12-V, and 24-V Distributed Power Systems
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm x 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
Efficiency
Ren1
EN
VIN
Ren2
VIN
CI
100
VO = 3.3 V
95
TPS54232
VI = 5 V
CBOOT
LO
VOUT
PH
SS
COMP
D1
CO
RO1
C1
CSS
C2
R3
Efficiency - %
BOOT
90
85
VI = 12 V
80
75
VI = 15 V
70
VSENSE
65
GND
RO2
60
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
IO - Output Current - A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54232
SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
6
6
7
7
8
Absolute Maximum Ratings .....................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1
11.2
11.3
11.4
Layout Guidelines .................................................
Layout Example ....................................................
Estimated Circuit Area ..........................................
Electromagnetic Interference (EMI)
Considerations .........................................................
24
24
25
25
12 Device And Documentation Support................. 26
12.1 Trademarks ........................................................... 26
12.2 Electrostatic Discharge Caution ............................ 26
12.3 Glossary ................................................................ 26
13 Mechanical, Packaging, And Orderable
Information ........................................................... 26
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2013) to Revision D
Page
•
Changed the data sheet to the new standard format ............................................................................................................. 1
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Added the Thermal Information table ..................................................................................................................................... 6
•
Deleted Package Dissipation Ratings table............................................................................................................................ 7
•
Changed Equation 7............................................................................................................................................................. 15
•
Changed Equation 32........................................................................................................................................................... 20
•
Changed Equation 33........................................................................................................................................................... 20
Changes from Revision B (February 2011) to Revision C
Page
•
Removed Swift™ from the data sheet title ............................................................................................................................. 1
•
Changed text From: "Where NC is the number of output capacitors in parallel." To: ":Where CO is the number of
output capacitors in parallel." Following Equation 13 ........................................................................................................... 17
•
Changed Equation 26........................................................................................................................................................... 18
•
Changed Equation 29........................................................................................................................................................... 19
•
Changed: Switching loss: Paw = 0.5 x 10-9 x VIN2 x IOUT x Few To: Switching loss: Psw = 0.5 x 10-9 x VIN2 x IOUT x
Fsw ...................................................................................................................................................................................... 21
•
Changed: Gate charge loss: P.C. = 22.8 x 10-9 x Few To: Gate charge loss: Pgc. = 22.8 x 10-9 x Fsw ............................ 21
•
Deleted graph "Maximum Power Dissipation vs Junction Temperature" from the Supplemental Application Curves......... 22
2
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SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
Changes from Revision A (March 2010) to Revision B
Page
•
Deleted feature Item: For SWIFT™ Documentation, See the TI Website at www.ti.com/swift.............................................. 1
•
Changed Figure 14 x-axis From: IO - Output Current - mA To: IO - Output Current - A....................................................... 22
Changes from Original (November 2008) to Revision A
Page
•
Changed Changed the ABSOLUTE MAXIMUM RATINGS table, Input Voltage - EN pin max value From: 5V to 6V .......... 5
•
Added a new table to the Description - For additional design needs................................................................................... 14
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TPS54232
SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
www.ti.com
6 Pin Configuration and Functions
D PACKAGE
(TOP VIEW)
BOOT
1
8
PH
VIN
2
7
GND
EN
3
6
COMP
SS
4
5
VSENSE
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
A 0.1-μF bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor falls below
the minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed.
VIN
2
I
Input supply voltage, 3.5 V to 28 V.
EN
3
I
Enable pin. Pull below 1.25 V to disable. Float to enable. Programming the input undervoltage lockout with
two resistors is recommended.
SS
4
I
Slow start pin. An external capacitor connected to this pin sets the output rise time.
VSENSE
5
I
Inverting node of the gm error amplifier.
COMP
6
O
Error amplifier output, and input to the PWM comparator. Connect frequency compensation components to
this pin.
GND
7
-
Ground.
PH
8
O
The source of the internal high-side power MOSFET.
4
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SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Input Voltage
MIN
MAX
VIN
–0.3
30
EN
–0.3
BOOT
Source Current
Sink Current
VSENSE
–0.3
3
COMP
–0.3
3
SS
–0.3
3
8
8
–0.6
30
PH
V
V
PH (10 ns transient from ground to negative peak)
–5
EN
100
μA
BOOT
100
mA
VSENSE
10
μA
PH
6
A
VIN
6
A
COMP
100
SS
200
Operating Junction Temperature, TJ
(1)
6
38
BOOT-PH
Output Voltage
UNIT
–40
μA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
MIN
MAX
UNIT
–65
150
°C
–2
2
kV
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TJ
MAX
UNIT
Operating Input Voltage on (VIN pin)
3.5
28
V
Operating junction temperature
–40
150
°C
7.4 Thermal Information
TPS54232
THERMAL METRIC (1)
D
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
116.3
RθJC(top)
Junction-to-case (top) thermal resistance
53.7
RθJB
Junction-to-board thermal resistance
57.1
ψJT
Junction-to-top characterization parameter
12.9
ψJB
Junction-to-board characterization parameter
56.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
-
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
7.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted)
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold
Rising and Falling
Shutdown supply current
EN = 0V, VIN = 12V, –40°C to 85°C
3.5
V
1
4
μA
Operating – non switching supply current
VSENSE = 0.85 V
85
120
μA
Enable threshold
Rising and Falling
1.25
1.35
Input current
Enable threshold – 50 mV
-1
μA
Input current
Enable threshold + 50 mV
-4
μA
ENABLE AND UVLO (EN PIN)
V
VOLTAGE REFERENCE
Voltage reference
0.772
0.8
0.828
BOOT-PH = 3 V, VIN = 3.5 V
115
200
BOOT-PH = 6 V, VIN = 12 V
80
150
V
HIGH-SIDE MOSFET
On resistance
mΩ
ERROR AMPLIFIER
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
Error amplifier DC gain (1)
VSENSE = 0.8 V
800
μmhos
V/V
Error amplifier unity gain bandwidth (1)
5 pF capacitance from COMP to GND pins
2.7
MHz
Error amplifier source/sink current
V(COMP) = 1.0 V, 100 mV overdrive
±7
μA
Switch current to COMP transconductance
VIN = 12 V
10
A/V
100
mA
4.9
A
165
°C
92
PULSE-SKIPPING ECO-MODE
Pulse-skipping Eco-Mode switch current threshold
CURRENT LIMIT
Current limit threshold
VIN = 12 V
2.3
THERMAL SHUTDOWN
Thermal Shutdown
SLOW START (SS PIN)
Charge current
V(SS) = 0.4 V
2
μA
SS to VSENSE matching
V(SS) = 0.4 V
10
mV
(1)
Specified by design
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS54232 Switching Frequency
VIN = 12V, 25°C
Minimum controllable on time
VIN = 12V, 25°C
Maximum controllable duty ratio (1)
BOOT-PH = 6 V
(1)
MIN
TYP
MAX
UNIT
800
1000
1200
kHz
110
135
ns
90%
93%
Specified by design
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7.7 Typical Characteristics
110
6
VIN = 12 V
EN = 0 V
105
Isd - Shutdown Current - mA
Rdson - On Resistance - mW
100
95
90
85
80
75
70
4
TJ = 150°C
2
TJ = -40°C
65
60
-50
TJ = 25°C
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
3
Figure 1. On Resistance vs Junction Temperature
8
13
18
VI - Input Voltage - V
23
28
Figure 2. Shutdown Quiescent Current vs Input Voltage
0.8240
1020
VIN = 12 V
Vref - Voltage Reference - V
fsw - Oscillator Frequency - kHz
0.8180
1010
1000
990
0.8120
0.8060
0.8000
0.7940
0.7880
0.7820
980
-50
-25
0
25
50
75
100
125
0.7760
-50
150
-25
0
TJ - Junction Temperature - °C
150
14.0
140
VIN = 12 V
13.5
VIN = 12 V
Minimum Controllable Duty Ratio - %
Tonmin - Minimum Controllable On Time - ns
125
Figure 4. Voltage Reference vs Junction Temperature
Figure 3. Switching Frequency vs Junction Temperature
130
120
110
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
100
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 5. Minimum Controllable On Time vs Junction
Temperature
8
25
50
75
100
TJ - Junction Temperature - °C
9.0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 6. Minimum Controllable Duty Ratios Junction
Temperature
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2.10
5.5
2.05
5.0
Current Limit Threshold - A
ISS - Slow Start Charge Current - mA
Typical Characteristics (continued)
2.00
1.95
1.90
-50
-25
0
25
50
75
100
125
150
TJ = -40°C
TJ = 25°C
4.5
TJ = 150°C
4.0
3.5
3
TJ - Junction Temperature - °C
Figure 7. SS Charge Current vs Junction Temperature
8
13
18
VI - Input Voltage - V
23
28
Figure 8. Current Limit Threshold vs Input Voltage
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8 Detailed Description
8.1 Overview
The TPS54232 is a 28-V, 2-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To
improve performance during line and load transients, the device implements a constant frequency, current mode
control which reduces output capacitance and simplifies external frequency compensation design. The
TPS54232 has a pre-set switching frequency of 1MHz.
The TPS54232 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pull-up
current source that can be used to adjust the input-voltage, undervoltage lockout (UVLO) with two external
resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to
operate. The operating current is 85 μA typically when not switching and under no load. When the device is
disabled, the supply current is 1 μA typically.
The integrated 80-mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output
currents up to 2 A.
The TPS54232 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference
voltage.
By adding an external capacitor, the slow start time of the TPS54232 can be adjustable which enables flexible
output filter selection.
To improve the efficiency at light load conditions, the TPS54232 enters a special pulse-skipping Eco-Mode when
the peak inductor current drops below 100 mA typically.
The frequency foldback reduces the switching frequency during startup and over current conditions to help
control the inductor current. The thermal shut down gives the additional protection under fault conditions.
8.2 Functional Block Diagram
EN
VIN
165 C
Thermal
Shutdown
1 mA
3 mA
Shutdown
Shutdown
Logic
1.25 V
Enable
Threshold
Enable
Comparator
Boot
Charge
™
ECO-MODE
Minimum Clamp
Boot
UVLO
BOOT
2.1V
Error
Amplifier
VSENSE
2 mA
PWM
Comparator
Gate
Drive
Logic
gm = 92 mA/V
DC gain = 800 V/V
BW = 2.7 MHz
Voltage
Reference
SS
2 kW
0.8 V
S
Shutdown
PWM
Latch
10 A/V
Current
Sense
R
80 mW
Q
S
Slope
Compensation
PH
Discharge
Logic
VSENSE
Frequency
Shift
Oscillator
GND
COMP
Maximum
Clamp
10
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8.3 Feature Description
8.3.1 Fixed-Frequency PWM Control
The TPS54232 uses a fixed frequency, peak current mode control. The internal switching frequency of the
TPS54232 is fixed at 1 MHz.
8.3.2 Voltage Reference (Vref)
The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by
scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8 V.
8.3.3 Bootstrap Voltage (BOOT)
The TPS54232 has an integrated boot regulator and requires a 0.1-μF ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R
grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve
drop out, the TPS54232 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is
greater than 2.1 V typically.
8.3.4 Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
The EN pin has an internal pull-up current source that provides the default condition of the TPS54232 operating
when the EN pin floats.
The TPS54232 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended
to use an external VIN UVLO to add hysteresis unless VIN is greater than (VOUT + 2V). To adjust the VIN UVLO
with hysteresis, use the external circuitry connected to the EN pin as shown in Figure 9. Once the EN pin voltage
exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate the
resistor values needed for the desired VIN UVLO threshold voltages. The VSTART is the input start threshold
voltage, the VSTOP is the input stop threshold voltage and the VEN is the enable threshold voltage of 1.25 V. The
VSTOP should always be greater than 3.5 V.
TPS54232
VIN
Ren1
1 mA
3 mA
+
EN
Ren2
1.25 V
-
Figure 9. Adjustable Input Undervoltage Lockout
Ren1 =
Ren2 =
VSTART - VSTOP
3 mA
(1)
VEN
VSTART - VEN
+ 1 mA
Ren1
(2)
8.3.5 Programmable Slow-Start Using SS Pin
It is highly recommended to program the slow start time externally because no slow start time is implemented
internally. The TPS54232 effectively uses the lower voltage of the internal voltage reference or the SS pin
voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output
accordingly. A capacitor (CSS) on the SS pin to ground implements a slow start time. The TPS54232 has an
internal pull-up current source of 2 μA that charges the external slow start capacitor. The equation for the slow
start time (10% to 90%) is shown in Equation 3. The Vref is 0.8V and the ISS current is 2μA.
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Feature Description (continued)
TSS (ms ) =
CSS (nF ) ´ Vref (V )
ISS (mA )
(3)
The slow start time should be set between 1 ms to 10 ms to ensure good startup behavior. The slow-start
capacitor should be no more than 27 nF.
If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below
1.25 V, or a thermal shutdown event occurs, the TPS54232 stops switching.
8.3.6 Error Amplifier
The TPS54232 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The
transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation
components are connected between the COMP pin and ground.
8.3.7 Slope Compensation
In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the
TPS54232 adds a built-in slope compensation which is a compensating ramp to the switch current signal.
8.3.8 Current Mode Compensation Design
For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended
when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the
nominal value when the applied voltage increases. For the detailed guidelines, see the Detailed Design
Procedure section.
8.3.9 Overcurrent Protection and Frequency Shift
The TPS54232 implements current mode control that uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared;
when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output
current.
The TPS54232 provides robust protection during short circuits. There is potential for overcurrent runaway in the
output inductor during a short circuit at the output. The TPS54232 solves this issue by increasing the off time
during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2,
and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency
and the VSENSE pin voltage is shown in Table 1.
Table 1. Switching Frequency Conditions
SWITCHING FREQUENCY
VSENSE PIN VOLTAGE
1 MHz
VSENSE ≥ 0.6 V
1 MHz / 2
0.6 V > VSENSE ≥ 0.4 V
1 MHz / 4
0.4 V > VSENSE ≥ 0.2 V
1 MHz / 8
0.2 V > VSENSE
8.3.10 Overvoltage Transient Protection
The TPS54232 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an
overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin
voltage goes above 109% × Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls
below 107% × Vref, the high-side MOSFET will be enabled again.
12
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8.3.11 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence.
8.4 Device Functional Modes
8.4.1 Eco-Mode
The TPS54232 device is designed to operate in pulse skipping Eco-mode at light load currents to boost light load
efficiency. When the peak inductor current is lower than 100 mA (typical), the COMP pin voltage falls to 0.5 V
(typical) and the device enters Eco-mode . When the device is in Eco-mode, the COMP pin voltage is clamped at
0.5 V internally which prevents the high-side integrated MOSFET from switching. The peak inductor current must
rise above 100 mA for the COMP pin voltage to rise above 0.5 V and exit Eco-mode. Because the integrated
current comparator catches the peak inductor current only, the average load current entering Eco-mode varies
with the applications and external output filters.
8.4.2 Operation With VIN < 3.5 V
The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not
specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the
actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device
becomes active when the VIN pin passes the UVLO threshold. Switching begins when the slow-start sequence is
initiated.
8.4.3 Operation With EN Control
The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled
and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced
in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the
device becomes active. Switching is enabled, and the slow-start sequence is initiated.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS54232 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 28 V to
a lower voltage. WEBENCH™ software is available to aid in the design and analysis of circuits.
For additional design needs, see:
TPS54231
TPS54232
TPS54233
TPS54331
TPS54332
IO(Max)
2A
2A
2A
3A
3.5A
Input Voltage Range
3.5V - 28V
3.5V - 28V
3.5V - 28V
3.5V - 28V
3.5V - 28V
Switching Freq. (Typ)
570kHz
1000kHz
285kHz
570kHz
1000kHz
Swiitch Current Limit (Min)
2.3A
2.3A
2.3A
3.5A
4.2A
Pin/Package
8SOIC
8SOIC
8SOIC
8SOIC
8SO PowerPAD™
9.2 Typical Application
Figure 10. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the values listed in Table 2 as the input parameters
Table 2. Design Parameters
14
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
5 V to 15V
Output voltage
2.5 V
Input ripple voltage
300 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating Frequency
1 MHz
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9.2.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS54232. Alternately, the
WEBENCH Software may be used to generate a complete design. The WEBENCH™ Software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design. This
section presents a simplified discussion of the design process.
9.2.2.1 Switching Frequency
The switching frequency for the TPS54232 is fixed at 1 MHz.
9.2.2.2 Output Voltage Set Point
The output voltage of the TPS54232 is externally adjustable using a resistor divider network. In the application
circuit of Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the
resistor divider is given by Equation 4 and Equation 5.
R5 ´ VREF
R6 =
VOUT - VREF
(4)
é R5 ù
VOUT = VREF ´ ê
+1ú
ë R6 û
(5)
Choose R5 to be approximately 10 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage
matching when using standard value resistors. In this design, R4 = 10.2 kΩ and R = 4.75 kΩ, resulting in a 2.5 V
output voltage. The zero ohm resistor R4 is provided as a convenient place to break the control loop for stability
testing.
9.2.2.3 Input Capacitors
The TPS54232 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.
The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be
used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of
circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54232 circuit is not located
within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated
to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple
voltage is acceptable. For this design a 10 μF capacitor issued for the input decoupling capacitor. It isX5R
dielectric rated for 25 V. The equivalent series resistance (ESR) is approximately 5 mΩ, and the current rating is
3 A.
This input ripple voltage can be approximated by Equation 6.
IOUT(MAX) ´ 0.25
DVIN =
+ IOUT(MAX) ´ ESRMAX
CBULK ´ fSW
(
)
(6)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the input capacitor value
and ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 7.
IOUT(MAX)
ICIN =
2
(7)
In this case, the input ripple voltage would be 60 mV and the RMS ripple current would be 1 A. It is also
important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the
layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in
Table 2 and is larger than the calculated value. This measured value is still below the specified input limit of 300
mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen bulk and
bypass capacitors are each rated for 25 V and the ripple current capacity is greater than 3 A, both providing
ample margin. It is very important that the maximum ratings for voltage and current are not exceeded under any
circumstance.
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9.2.2.4 Output Filter Components
Two components need to be selected for the output filter, L1 and C3. Since the TPS54232 is an externally
compensated device, a wide range of filter component types and values can be supported.
9.2.2.4.1 Inductor Selection
To calculate the minimum value of the output inductor, use Equation 8.
LMIN =
VOUT(MAX) ´
(VIN(MAX) - VOUT )
VIN(MAX) ´ KIND ´ IOUT ´ FSW
(8)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
In general, this value is at the discretion of the designer; however, the following guidelines may be used. For
designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.4 may be used. When
using higher ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.35 and the minimum inductor value is calculated to be 2.97 μH. For this
design, a large value was chosen: 3.3 μH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The peak-to-peak inductor current is calculated using Equation 9.
ILPP =
(
VOUT × VIN(MAX)
-
VOUT
)
VIN(MAX) × LOUT ´ ƒSW ´ 0.8
(9)
The RMS inductor current can be found from Equation 10.
IL(RMS) =
2
IOUT(MAX)
(
)
æ VOUT ´ VIN(MAX) - VOUT ö
1
÷
+
´ ç
ç VIN(MAX) ´ LOUT ´ FSW ´ 0.8 ÷
12
è
ø
2
(10)
and the peak inductor current can be determined with Equation 11.
IL(PK) = IOUT(MAX) +
VOUT ´
(VIN(MAX)
- VOUT
)
1.6 ´ VIN(MAX) ´ LOUT ´ FSW
(11)
For this design, the RMS inductor current is 2.01 A and the peak inductor current is 2.39 A. The chosen inductor
is a Coilcraft MSS7341-332NL 3.3 μH. It has a saturation current rating of 3.28 A and an RMS current rating of
3.95 A, meeting these requirements. Smaller or larger inductor values can be used depending on the amount of
ripple current the designer wishes to allow so long as the other design requirements are met. Larger value
inductors will have lower ac current and result in lower output voltage ripple, while smaller inductor values will
increase ac current and output voltage ripple. Inductor values for use with the TPS54232 are in the range of 1 μH
to 47 μH.
9.2.2.4.2 Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor current it determines the amount of output ripple voltage. The actual value of the
output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired
closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is
desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With highswitching frequencies such as the 1 MHz frequency of this design, internal circuit limitations of the TPS54232
limit the practical maximum crossover frequency to about 70 kHz. In general, the closed loop crossover
frequency should be higher than the corner frequency determined by the load impedance and the output
capacitor. This limits the minimum capacitor value for the output filter to:
CO _ min = 1 /(2 ´ p ´ RO ´ FCO _ max )
16
(12)
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Where RO is the output load impedance (VO/IO) and fCO is the desired crossover frequency. For a desired
maximum crossover of 50 kHz the minimum value for the output capacitor is around 2.5 μF. This may not satisfy
the output ripple voltage requirement. The output ripple voltage consists of two components; the voltage change
due to the charge and discharge of the output filter capacitance and the voltage change due to the ripple current
times the ESR of the output filter capacitor. The output ripple voltage can be estimated by:
é ( D - 0 .5 )
ù
+ R ESR ú
V O PP = I LPP ê
û
ë 4 ´ F SW ´ C O
(13)
The maximum ESR of the output capacitor can be determined from the amount of allowable output ripple as
specified in the initial design parameters. The contribution to the output ripple voltage due to ESR is the inductor
ripple current times the ESR of the output filter, so the maximum specified ESR as listed in the capacitor data
sheet is given by Equation 14.
ESRmax =
VOPPMAX
ILPP
-
(D
- 0.5 )
4 ´ FSW ´ CO
(14)
Where VOPPMAX is the desired maximum peak-to-peak output ripple. The maximum RMS ripple current in the
output capacitor is given by Equation 15.
æ VOUT × VIN(MAX) - VOUT ö
1
÷
ICOUT(RMS) =
× ç
ç VIN(MAX) × LOUT × FSW × NC ÷
12
è
ø
(15)
(
)
Where NC is the number of output capacitors in parallel.
For this design example, a single 22-μF ceramic output capacitor is chosen for C6. It is rated at 10 V with a
maximum ESR of 5 mΩ and a ripple current rating in excess of 3 A. The calculated total RMS ripple current is
182 mA and the maximum total ESR required is 51 mΩ. This output capacitor exceeds the requirements by a
wide margin and will result in a reliable, high-performance design. it is important to note that the actual
capacitance in circuit may be less than the catalog value when the output is operating near the rated voltage for
the capacitor. The selected output capacitor must be rated for a voltage greater than the desired output voltage
plus ½ the ripple voltage but in this example a 10-V capacitor is used so that the effective capacitance will
remain close to the stated value of 22 μF. Other capacitor types work well with the TPS54232, depending on the
needs of the application.
9.2.2.5 Compensation Components
The external compensation used with the TPS54232 allows for a wide range of output filter configurations. A
large range of capacitor values and types of dielectric are supported. The design example uses a ceramic X5R
dielectric output capacitor, but other types are supported.
A Type II compensation scheme is recommended for the TPS54232. The compensation components are chosen
to set the desired closed loop cross over frequency and phase margin for output filter components. The type II
compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency
zero / pole pair.
The DC gain is determined by Equation 16.
Vggm ´ VREF
GDC =
VO
(16)
Where:
Vggm = 800
VREF = 0.8 V
The low-frequency pole is determined by Equation 17.
VPO = 1/ (2 ´ p ´ ROO ´ CZ )
(17)
The mid-frequency zero is determined by Equation 18.
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FZ1 = 1/ (2 ´ p ´ R Z ´ CZ )
(18)
And, the mid-frequency pole is given by Equation 19.
FP1 = 1/ (2 ´ p ´ R Z ´ CP )
(19)
The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency
should be less than 1/8 of the minimum operating frequency, but for the TPS54232 it is recommended that the
maximum closed loop crossover frequency be not greater than 75 kHz. Next, the required gain and phase boost
of the crossover network needs to be calculated. By definition, the gain of the compensation network must be the
inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much
higher than the closed loop crossover frequency, the gain of the modulator and output filter can be approximated
by Equation 20.
Gain = - 20 log (2 ´ p ´ RSENSE ´ FCO ´ CO ) - 2dB
(20)
Where:
RSENSE = 1Ω/10
FCO = Closed-loop crossover frequency
CO = Output capacitance
The phase loss is given by Equation 21.
PL = a tan (2 ´ p ´ FCO ´ RESR ´ CO ) - a tan (2 ´ p ´ FCO ´ RO ´ CO ) - 10deg
(21)
Where:
RESR = Equivalent series resistance of the output capacitor
RO = VO/IO
The measured overall loop response for the circuit is given in Figure 20. Note that the actual closed-loop
crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual
values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall
the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of
line and load variability.
Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement
can be determined. The required phase boost is given by Equation 22.
PB = (PM - 90 deg ) - PL
(22)
Where PM = the desired phase margin.
A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop
frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined
by Equation 23 and the resultant zero and pole frequencies are given by Equation 24 and Equation 25.
ö
æ PB
k = tanç
+ 45 deg ÷
ø
è 2
FZ 1 =
(23)
FCO
k
(24)
FP1 = FCO ´ k
(25)
The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the
modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of
RZ can be derived directly by Equation 26.
2 × p × FCO × VO × CO × ROA × 0.754
RZ =
GMICOMP × Vggm × VREF
(26)
Where:
18
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VO = Output voltage
CO = Output capacitance
FCO = Desired crossover frequency
ROA = 8.696 MΩ
GMCOMP = 10 A/V
Vggm = 800
VREF = 0.8 V
With RZ known, CZ and CP can be calculated using Equation 27 and Equation 28.
CZ =
CP =
1
2 ´ p ´ FZ 1 ´ Rz
(27)
1
2 ´ p ´ FP1 ´ Rz
(28)
For this design, a 22-μF output capacitor issued. For ceramic capacitors, the actual output capacitance is less
than the rated value when the capacitors have a dc bias voltage applied. This is the case in a DC - DC converter.
For this design, a 10-V capacitor is chosen to minimize this effect. The ESR is approximately 0.005 Ω.
Using Equation 20 and Equation 21, the output stage gain and phase loss are equivalent as:
Gain = 1.613 dB
and
PL = -92.3 degrees
For 60 degrees of phase margin, Equation 22 requires 62.33 degrees of phase boost.
Equation 23, Equation 24, and Equation 25 are used to find the zero and pole frequencies of:
FZ1 = 12.3 k Hz
And
FP1 = 203 kHz
RZ, CZ, and CP are calculated using Equation 26, Equation 27, and Equation 28.
2 ´ p ´ 50000 ´ 2.5 ´ 22 ´ 10-6 ´ 8.696 ´ 106 ´ 0.754
= 17.7 kW
10 ´ 800 ´ 0.8
1
Cz =
= 730 pF
2 ´ p ´ 12300 ´ 17700
1
Cp =
= 44 pF
2 ´ p ´ 203000 ´ 17700
Rz =
(29)
(30)
(31)
Using standard values for R3, C6, and C7 in the application schematic of Figure 10:
R3 = 17.4 kΩ
C6 = 680 pF
C7 = 47 pF
9.2.2.6 Bootstrap Capacitor
Every TPS54232 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The
bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a highquality ceramic type with X7R or X5R grade dielectric for temperature stability.
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9.2.2.7 Catch Diode
The TPS54232 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B220A is chosen, with a reverse voltage
of 20 V, forward current of 2 A, and a forward voltage drop of 0.5 V.
9.2.2.8 Output Voltage Limitations
Due to the internal design of the TPS54232, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 90%
and is given by Equation 32.
VO(max) = 0.90 x ((VIN(min) – IO(max) x Rdson(max)) +VD) – (IO(max) x RL) – VD
(32)
Where:
VIN(min) = Minimum input voltage
IO(max) = Maximum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
The equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 135 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 33.
VO(min) = 0.162 x ((VIN(max) – IO(min) x Rdson(min)) + VD) – (IO(min) x RL) – VD
(33)
Where:
VIN(max) = Maximum input voltage
IO(min) = Minimum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to assure proper functionality.
20
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9.2.2.9 Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or
pulse-skipping Eco-Mode.
The device power dissipation includes:
1. Conduction loss: Pcon = IOUT2 x RDS(on) x VOUT/VIN
2. Switching loss: Psw = 0.5 x 10-9 x VIN2 x IOUT x Fsw
3. Gate charge loss: Pgc. = 22.8 x 10-9 x Fsw
4. Quiescent current loss: Pq = 0.085 x 10-3 x VIN
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
Fsw is the switching frequency (Hz).
So:
Ptot = Pcon + Psw + Pgc + Pq
For given TA , TJ = TA + Rth x Ptot.
For given TJMAX = 150°C, TAMAX = TJMAX– Rth x Ptot.
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C) .
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
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9.2.3 Application Curves
space
3.75
30
IO = 2 A
IO = 2 A
25
VO - Output Voltage - V
VO - Output Voltage - V
3.25
2.75
2.25
1.75
1.25
20
15
10
5
0.75
0
3
8
13
18
VI - Input Voltage - V
23
28
Figure 11. Typical Minimum Output Voltage vs Input
Voltage
3
8
13
18
VI - Input Voltage - V
23
28
Figure 12. Typical Maximum Output Voltage vs Input
Voltage
100
100
VO = 3.3 V
95
95
VI = 5 V
VI = 8 V
90
90
Efficiency - %
Efficiency - %
85
VI = 12 V
85
80
75
VI = 15 V
80
VI = 12 V
75
70
65
VI = 15 V
70
60
65
55
60
50
0
0.25
0.5
0.75
1
1.25 1.5
IO - Output Current - A
1.75
2
0
Figure 14. TPS54232 Low Current Efficiency
0.1
0.025
0.08
0.02
0.06
0.015
VI = 15 V
Output Regulation - %
Output Voltage Regulation - %
Figure 13. TPS54232 Efficiency
0.04
VI = 5 V
0.02
0
-0.02
VI = 12 V
-0.04
0.01
IO = 1 A
0.005
0
-0.005
-0.01
-0.06
-0.015
-0.08
-0.02
-0.1
-0.025
0
0.2
0.4 0.6 0.8 1 1.2 1.4
IO - Output Current - A
1.6
1.8
2
Figure 15. TPS54232 Load Regulation
22
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
IO - Output Current - A
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5
6
7
8
9
10 11 12
VI - Input Voltage - V
13
14
15
Figure 16. TPS54232 Line Regulation
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60
180
50
VOUT
150
Gain
40
120
30
90
Phase
Gain - dB
20
IOUT 0.5 - 2 A STEP
10
30
0
0
-10
-30
-20
-60
-30
-90
-40
-120
-50
-150
-60
10
t - Time - 2 ms/div
60
Phase - Deg.
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100
1k
10k
f - Frequency - Hz
100k
-180
1M
Figure 18. TPS54232 Loop Response
Figure 17. TPS54232 Transient Response
VOUT
VIN
PH
PH
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 19. TPS54232 Output Ripple
Figure 20. TPS54232 Input Ripple
VOUT
VOUT
VIN
SS
t - Time - 2 ms/div
t - Time - 2 ms/div
Figure 21. TPS54232 Startup
Figure 22. TPS54232 Startup Relative to Enable
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10 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range between 3.5 V and 28 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the converter additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 100 μ F is a typical choice.
11 Layout
11.1 Layout Guidelines
The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the
optimum placement is closest to the VIN pins and the source of the anode of the catch diode. The GND D pin
should be tied to the PCB ground plane at the pin of the IC. The source of the low-side MOSFET should be
connected directly to the top side PCB ground area used to tie together the ground sides of the input and output
capacitors as well as the anode of the catch diode. The PH pin should be routed to the cathode of the catch
diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output
inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent
excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate
heat dissipating area. The TPS54232 uses a fused lead frame so that the GND pin acts as a conductive path for
heat dissipation from the die. Many applications have larger areas of internal or back side ground plane
available, and the top side ground area can be connected to these areas using multiple vias under or adjacent to
the device to help dissipate heat. The additional external components can be placed approximately as shown. It
may be possible to obtain acceptable performance with alternate layout schemes, however this layout has been
shown to produce good results and is intended as a guideline.
11.2 Layout Example
OUTPUT
FILTER
CAPACITOR
TOPSIDE
GROUND
AREA
Route BOOT CAPACITOR
trace on other layer to provide
wide path for topside ground
Vout
Feedback Trace
OUTPUT
INDUCTOR
CATCH
DIODE
PH
INPUT
BYPASS
CAPACITOR
BOOT
Vin
UVLO
RESISTOR
DIVIDER
VIN
GND
EN
COMP
SS
VSENSE
SLOW START
CAPACITOR
Thermal VIA
BOOT
CAPACITOR
PH
COMPENSATION
NETWORK
RESISTOR
DIVIDER
Signal VIA
Figure 23. TPS54232 Board Layout
24
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Product Folder Links: TPS54232
TPS54232
www.ti.com
SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
11.3 Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 10 is 0.44 in2. This area
does not include test points or connectors.
11.4 Electromagnetic Interference (EMI) Considerations
As EMI becomes a rising concern in more and more applications, the internal design of the TPS54232 takes
measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the Detailed Design Procedure above to prevent potential EMI issues.
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Product Folder Links: TPS54232
25
TPS54232
SLVS876D – NOVEMBER 2008 – REVISED NOVEMBER 2014
www.ti.com
12 Device And Documentation Support
12.1 Trademarks
Eco-Mode, WEBENCH, PowerPAD are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54232D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
54232
TPS54232DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
54232
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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