TPS54260QDRCTQ1

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 TPS54260-Q1 3.5-V to 60-V Step-Down Converter With Eco-mode™ 1 Features 3 Description • • The TPS54260-Q1 device is a 60-V, 2.5-A, stepdown regulator with an integrated high-side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces the no load, regulated output supply current to 138 μA. Using the enable pin, shutdown supply current is reduced to 1.3-μA, when the enable pin is low. 1 • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification 2 – Device CDM ESD Classification Level C4B 3.5-V to 60-V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads With a Pulse Skipping Eco-mode™ 138-μA Operating Quiescent Current 1.3-μA Shutdown Current 100-kHz to 2.5-MHz Switching Frequency Synchronizes to External Clock Adjustable Slow Start and Sequencing UV and OV Power Good Output Adjustable UVLO Voltage and Hysteresis 0.8-V Internal Voltage Reference 10-Pin HVSSOP and 10-Pin 3-mm × 3-mm VSON Packages Supported by WEBENCH® Software Tool Under voltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing and tracking. An open drain power good signal indicates the output is within 94% to 107% of the nominal voltage. A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold back and thermal shutdown protects the part during an overload condition. The TPS54260-Q1 is available in 10-pin thermallyenhanced HVSSOP and 10-pin 3-mm × 3-mm VSON package. Device Information(1) PART NUMBER PACKAGE PACKAGE SIZE HVSSOP (10) 3.00 mm × 4.90 mm VSON (10) 3.00 mm × 3.00 mm 2 Applications TPS54260-Q1 • • (1) For all available packages, see the orderable addendum at the end of the data sheet. 12-V and 24-V Automotive and Industrial Systems Infotainment, Cluster, and ADAS Applications Space Simplified Schematic Efficiency vs Load Current 100 VIN 90 PWRGD 80 TPS54260-Q1 BOOT PH Efficiency - % EN 70 60 50 40 30 SS /TR RT /CLK COMP VIN=12V VOUT=3.3V fsw=300kHz 20 10 VSENSE 0 0 GND 0.5 1.0 1.5 2.0 IO - Output Current - A 2.5 3.0 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 7 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 25 8 Application and Implementation ........................ 29 8.1 Application Information............................................ 29 8.2 Typical Application ................................................. 29 9 Power Supply Recommendations...................... 39 10 Layout................................................................... 39 10.1 Layout Guidelines ................................................. 39 10.2 Layout Example .................................................... 40 11 Device and Documentation Support ................. 41 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 41 41 41 41 12 Mechanical, Packaging, and Orderable Information ........................................................... 41 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (December 2014) to Revision F Page • Added package information for VSON to the Device Information table ................................................................................. 1 • Added pinout drawing for DRC package (VSON) ................................................................................................................. 3 • Removed max ratings for BOOT voltage .............................................................................................................................. 4 • Added minimum output voltage for BOOT-PH ...................................................................................................................... 4 • Added thermal information for DRC (VSON) package .......................................................................................................... 5 • Updated Rth parameter definition for Equation 55 .............................................................................................................. 36 • Added Community Resources ............................................................................................................................................. 41 Changes from Revision D (January 2013) to Revision E • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 4 Changes from Revision C (May 2013) to Revision D • Page Page Changed PWRGD from 10 kΩ to 1 kΩ in Power Good (PWRGD Pin) section.................................................................... 21 Changes from Revision B (January, 2013) to Revision C Page • Changed Feature From: Device CDM ESD Classification Level C4B To: Device CDM ESD Classification Level C5.......... 1 • Changed the CDM From: Classification Level C4B, 750 V To: Classification Level C5, 1000 V .......................................... 4 Changes from Revision A (April, 2011) to Revision B Page • Added AEC-Q100 ESD ratings to Features section............................................................................................................... 1 • Updated ESD ratings rows in Abs Max table. ....................................................................................................................... 4 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 5 Pin Configuration and Functions DGQ Package 10-Pin HVSSOP Top View BOOT VIN EN SS/TR RT/CLK 1 10 2 9 Thermal Pad (11) 3 4 8 7 6 5 DRC Package 10-Pin VSON Top View PH GND COMP VSENSE PWRGD BOOT 1 10 PH VIN EN SS/TR RT/CLK 2 9 GND COMP VSENSE PWRGD 3 4 5 Thermal Pad (11) 8 7 6 Pin Functions PIN NAME NO. I/O DESCRIPTION BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. COMP 8 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 3 I Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. GND 9 — PH 10 I PowerPAD — — GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. PWRGD 6 O An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shut down. Ground The source of the internal high-side power MOSFET. RT/CLK 5 I Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. SS/TR 4 I Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. VIN 2 I Input supply voltage, 3.5 to 60 V VSENSE 7 I Inverting node of the transconductance (gm) error amplifier Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 3 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted). (1) Input voltage Output voltage MIN MAX VIN –0.3 65 EN (2) –0.3 5 VSENSE –0.3 3 COMP –0.3 3 PWRGD –0.3 6 SS/TR –0.3 3 RT/CLK –0.3 3.6 BOOT-PH –0.3 8 –0.6 65 200 ns –1 65 30 ns –2 65 PH Maximum dc voltage, T J= –40°C Voltage difference Source current V V –0.85 PAD to GND ±200 mV EN 100 μA BOOT 100 mA VSENSE 10 μA PH Current limit RT/CLK μA 100 VIN Sink current UNIT Current limit COMP 100 μA PWRGD 10 mA 200 μA Operating junction temperature –40 150 °C Storage temperature, Tstg –65 150 °C SS/TR (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See Enable and Adjusting Undervoltage Lockout (UVLO) for details. 6.2 ESD Ratings VALUE Human body model (HBM), per AEC Q100-002 V(ESD) (1) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 (1) UNIT ±2000 Corner pins (1, 5, 6, 10) ±750 Other pins ±500 V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TA 4 Operating ambient temperature –40 Submit Documentation Feedback NOM MAX UNIT 125 °C Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 6.4 Thermal Information TPS54260-Q1 THERMAL METRIC (1) (2) DRC (VSON) DGQ (HVSSOP) 10 PINS 10 PINS 40 62.5 — 57 Standard board UNIT RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 65 83 °C/W RθJB Junction-to-board thermal resistance 8 28 °C/W ψJT Junction-to-top characterization parameter 0.6 1.7 °C/W ψJB Junction-to-board characterization parameter 7.5 20.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.8 21 °C/W (1) (2) (3) Custom board (3) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information. Test boards conditions: (a) 3 inches × 3 inches, 2 layers, thickness: 0.062 inch (b) 2-oz copper traces located on the top of the PCB (c) 2-oz copper ground plane, bottom layer (d) 6 thermal vias (13 mil) located under the device package 6.5 Electrical Characteristics TJ = –40 to 150°C, VIN = 3.5 to 60 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Operating input voltage 3.5 60 Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 138 200 1.25 1.36 V V μA ENABLE AND UVLO (EN PIN) Enable threshold voltage Input current No voltage hysteresis, rising and falling, 25°C 1.15 Enable threshold +50 mV –3.8 Enable threshold –50 mV –0.9 Hysteresis current V μA μA –2.9 VOLTAGE REFERENCE Voltage reference TJ = 25°C 0.792 0.8 0.808 0.784 0.8 0.816 V HIGH-SIDE MOSFET On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 VIN = 12 V, BOOT-PH = 6 V 200 410 mΩ ERROR AMPLIFIER Input current 50 nA Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μS Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V, during slow start VVSENSE = 0.4 V 70 μS 10,000 V/V 2700 kHz ±27 μA 10.5 A/V Error amplifier dc gain VVSENSE = 0.8 V Error amplifier bandwidth Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive COMP to switch current transconductance Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 5 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) TJ = –40 to 150°C, VIN = 3.5 to 60 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.5 6.1 A 182 °C CURRENT LIMIT Current limit threshold VIN = 12 V, TJ = 25°C THERMAL SHUTDOWN Thermal shutdown TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching Frequency Range using RT mode fSW Switching frequency 100 RT = 200 kΩ 450 Switching Frequency Range using CLK mode 581 300 Minimum CLK input pulse width 40 RT/CLK high threshold 1.9 RT/CLK low threshold 0.5 RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series PLL lock in time Measured at 500 kHz 2500 kHz 720 kHz 2200 kHz ns 2.2 V 0.7 V 60 ns 100 μs SLOW START AND TRACKING (SS/TR) Charge current VSS/TR = 0.4 V 2 μA SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV SS/TR-to-reference crossover 98% nominal 1.15 V SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 μA SS/TR discharge voltage VSENSE = 0 V 54 mV VSENSE falling 92% POWER GOOD (PWRGD PIN) VVSENSE 6 VSENSE rising 94% VSENSE rising 109% VSENSE falling 107% Hysteresis VSENSE falling 2% Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA VSENSE threshold Submit Documentation Feedback 0.95 nA Ω 1.5 V Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 0.816 500 375 BOOT-PH = 3 V Voltage Reference (V) Static Drain-Source On-State Resistance (mW) 6.6 Typical Characteristics 250 BOOT-PH = 6 V 125 0 –50 –25 0 75 25 50 100 Junction Temperature (°C) 125 0.808 0.800 0.792 0.784 –50 150 –25 0 C001 Figure 1. On Resistance vs Junction Temperature 75 25 50 100 Junction Temperature (°C) 125 150 C002 Figure 2. Voltage Reference vs Junction Temperature 610 7.0 VI = 12 V Switching Frequency (kHz) 600 Switch Current - A 6.5 6.0 5.5 590 580 570 560 5.0 -50 -25 0 25 50 75 100 125 150 550 –50 –25 0 TJ - Junction Temperature - °C 500 2000 400 1500 1000 500 0 0 25 50 75 100 125 150 RT/CLK Resistance (kW) 175 200 150 C004 300 200 100 0 200 C005 Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range 125 Figure 4. Switching Frequency vs Junction Temperature 2500 Switching Frequency (kHz) Switching Frequency (kHz) Figure 3. Switch Current Limit vs Junction Temperature 75 25 50 100 Junction Temperature (°C) 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) C006 Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 7 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 500 120 VI = 12 V VI = 12 V 450 100 400 gm - mS gm - mS 80 350 60 300 40 20 -50 250 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 200 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. EA Transconductance During Slow Start vs Junction Temperature Figure 8. EA Transconductance vs Junction Temperature 1.40 –3.25 I(EN) (μA) EN Threshold (V) –3.5 1.30 –3.75 1.20 –4 1.10 –50 –25 0 75 25 50 100 Junction Temperature (°C) 125 –1 –0.85 –1.5 I(SS/TR) (μA) I(EN) (μA) 0 –0.9 –0.95 75 25 50 100 Junction Temperature (°C) 125 150 C010 Figure 10. EN Pin Current vs Junction Temperature –0.8 –1 –50 –25 C009 Figure 9. EN Pin Voltage vs Junction Temperature –2 –2.5 –25 0 75 25 50 100 Junction Temperature (°C) 125 150 –3 –50 C011 Figure 11. EN Pin Current vs Junction Temperature 8 –4.25 –50 150 –25 0 75 25 50 100 Junction Temperature (°C) 125 150 C012 Figure 12. SS/TR Charge Current vs Junction Temperature Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Typical Characteristics (continued) 100 575 VI = 12 V 80 % of Nominal fsw II(SS/TR) - mA 500 425 350 60 40 20 275 200 -50 0 50 100 TJ - Junction Temperature - °C 0 150 0 Figure 13. SS/TR Discharge Current vs Junction Temperature 0.2 0.4 VSENSE (V) 0.6 0.8 C014 Figure 14. Switching Frequency vs VSENSE 2 2 TJ = 25°C 1.5 I(VIN) - mA I(VIN) (μA) 1.5 1 0.5 0 –50 0.5 0 –25 0 75 25 50 100 Junction Temperature (°C) 125 150 0 20 VI - Input Voltage - V 30 40 Figure 16. Shutdown Supply Current vs Input Voltage (VIN) 170 210 VI = 12 V, VI(VSENSE) = 0.83 V o TJ = 25 C, VI(VSENSE) = 0.83 V 170 150 I(VIN) - mA I(VIN) - mA 10 C015 Figure 15. Shutdown Supply Current vs Junction Temperature 190 1 150 130 130 110 90 70 -50 110 0 50 100 TJ - Junction Temperature - °C 0 150 Figure 17. VIN Supply Current vs Junction Temperature 10 30 20 VI - Input Voltage - V 40 Figure 18. VIN Supply Current vs Input Voltage Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 9 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 100 115 80 110 PWRGD Threshold (% of Vref) RDSON (W) Typical Characteristics (continued) 60 40 20 0 –50 –25 75 25 50 100 Junction Temperature (°C) 0 125 VSENSE Rising 95 90 VSENSE Falling –25 75 25 50 100 Junction Temperature (°C) 0 3 2.25 2.75 2 125 150 C020 Figure 20. PWRGD Threshold vs Junction Temperature 2.5 VI(VIN) (V) VI(BOOT-PH) (V) VSENSE Falling 100 C019 1.75 2.50 2.25 2 1.5 –50 –25 75 25 50 100 Junction Temperature (°C) 0 125 150 -50 -25 0 C021 Figure 21. Boot-PH UVLO vs Junction Temperature 75 25 50 100 Junction Temperature (°C) 125 150 C022 Figure 22. Input Voltage (UVLO) vs Junction Temperature 600 60 VIN = 12 V TJ = 25°C 500 50 400 V(SS/TR) = 0.4 V VI = 12 V 40 Offset - mV Offset Voltage Threshold (mV) 105 85 –50 150 Figure 19. PWRGD On Resistance vs Junction Temperature 300 30 200 20 100 10 0 0 200 400 600 Voltage Sense (mV) 800 0 -50 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 23. SS/TR to VSENSE Offset vs VSENSE 10 VSENSE Rising Figure 24. SS/TR to VSENSE Offset vs Temperature Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 7 Detailed Description 7.1 Overview The TPS54260-Q1 device is a 60-V, 2.5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS54260-Q1 has a default start up voltage of approximately 2.5 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device operates. The operating current is 138 μA when not switching and under no load. When the device is disabled, the supply current is 1.3 μA. The integrated 200-mΩ high-side MOSFET allows for high efficiency power supply designs capable of delivering 2.5 A of continuous current to a load. The TPS54260-Q1 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54260-Q1 operates at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference. The TPS54260-Q1 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pin to transition high when a pull-up resistor is used. The TPS54260-Q1 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault, UVLO fault or a disabled condition. The TPS54260-Q1, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit slow starts the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 11 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 7.2 Functional Block Diagram PWRGD 6 EN 3 VIN 2 Shutdown UV Thermal Shutdown Enable Comparator Logic UVLO Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum Clamp Pulse Skip ERROR AMPLIFIER PWM Comparator VSENSE 7 Current Sense 1 BOOT Logic And PWM Latch SS/TR 4 Shutdown Slope Compensation 10 PH COMP 8 11 POWERPAD Frequency Shift Overload Recovery Maximum Clamp Oscillator with PLL TPS54260-Q1 Block Diagram 9 GND 5 RT/CLK 7.3 Feature Description 7.3.1 Fixed Frequency PWM Control The TPS54260-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. The Eco-mode is implemented with a minimum clamp on the COMP pin. 7.3.2 Slope Compensation Output Current The TPS54260-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range. 7.3.3 Pulse Skip Eco-mode The TPS54260-Q1 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing switching and gate drive losses. The TPS54260-Q1 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or 500 mV. 12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) When in Eco-mode, the COMP pin voltage is clamped at 500 mV and the high-side MOSFET is inhibited. Further decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level. Because the device is not switching, the output voltage begins to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually falls below the Eco mode threshold at which time the device again enters Eco mode. For Eco mode operation, the TPS54260-Q1 senses peak current, not average or load current, so the load current where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in Figure 50 enters Eco mode at about 5 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 138-μA input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode, the switching transitions occur synchronously with the external clock signal. 7.3.4 Low Dropout Operation and Bootstrap Voltage (Boot) The TPS54260-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics overtemperature and voltage. To improve drop out, the TPS54260-Q1 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET is turned off using an UVLO circuit which allows the low-side diode to conduct and refresh the charge on the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side MOSFET remains on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high. The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode and printed circuit board resistance. During operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH voltage falls below 2.1 V. Attention must be taken in maximum duty cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1 V UVLO threshold, the highside MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. TI recommends to adjust the VIN stop voltage greater than the BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with resistors on the EN pin. The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26. The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching. During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot capacitor being longer than the typical high-side off time when switching occurs every cycle. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 13 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 4 5.6 3.8 5.4 3.6 Input Voltage (V) Input Voltage (V) Feature Description (continued) Start 3.4 Stop 5.2 Start 5 Stop 3.2 4.8 3 4.6 0 0.05 0.10 Output Current (A) 0.15 0.20 0 C025 Figure 25. 3.3-V Start and Stop Voltage 0.05 0.10 Output Current (A) 0.15 0.20 C026 Figure 26. 5-V Start and Stop Voltage 7.3.5 Error Amplifier The TPS54260-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 310 μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is 70 μA/V. The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin to ground. 7.3.6 Voltage Reference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. 7.3.7 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current is noticeable. æ Vout - 0.8V ö R1 = R2 ´ ç ÷ 0.8 V è ø (1) 7.3.8 Enable and Adjusting Undervoltage Lockout (UVLO) The TPS54260-Q1 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher UVLO, use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of 0.9 μA that provides the default condition of the TPS54260-Q1 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the input start voltage. 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) TPS54260-Q1 VIN Ihys I1 0.9 mA R1 2.9 mA + R2 EN - 1.25 V Figure 27. Adjustable UVLO V - VSTOP R1 = START IHYS R2 = (2) VENA VSTART - VENA + I1 R1 (3) Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin. TPS54260-Q1 VIN R1 Ihys I1 0.9 mA 2.9 mA + R2 EN 1.25 V R3 - VOUT Figure 28. Adding Additional Hysteresis R1 = R2 = VSTART - VSTOP V IHYS + OUT R3 (4) VENA VSTART - VENA V + I1 - ENA R1 R3 (5) Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage. The node voltage, (see Figure 29) must remain equal to or less than 5.8 V. The zener diode can sink up to 100 µA. The EN pin voltage can be greater than 5 V if the VIN voltage source has a high impedance and does not source more than 100 µA into the EN pin. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 15 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) VIN R1 Node ENA 10kohm R2 5.8V Figure 29. Node Voltage 7.3.9 Slow Start and Tracking Pin (SS/TR) The TPS54260-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54260-Q1 has an internal pull-up current source of 2 μA that charges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6. The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2 μA. The slow start capacitor should remain lower than 0.47 μF and greater than 0.47 nF. Tss(ms) ´ Iss(m A) Css(nF) = Vref (V) ´ 0.8 (6) At power up, the TPS54260-Q1 does not start switching until the slow start pin is discharged to less than 40 mV to ensure a proper power up, see Figure 30. Also, during normal operation, the TPS54260-Q1 stops switching and the SS/TR must be discharged to 40 mV, when the VIN UVLO is exceeded, EN pin pulled below 1.25 V, or a thermal shutdown event occurs. The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage ramps linearly until clamped at 1.7 V. 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) EN SS/TR VSENSE VOUT Figure 30. Operation of SS/TR Pin When Starting 7.3.10 Overload Recovery Circuit The TPS54260-Q1 has an overload recovery (OLR) circuit. The OLR circuit slow starts the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of 382 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed, the output slow starts from the fault voltage to nominal output voltage. 7.3.11 Constant Switching Frequency and Timing Resistor (RT and CLK Pin) The switching frequency of the TPS54260-Q1 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 7 or the curves in Figure 31 or Figure 32. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 135 ns and limits the maximum operating input voltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of the maximum switching frequency is located below. 206033 RT (k W) = ¦ sw (kHz )1.0888 (7) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 17 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) 500 2500 2000 Switching Frequency (kHz) fs - Switching Frequency - kHz VI = 12 V, TJ = 25°C 1500 1000 500 0 0 25 50 75 100 125 150 RT/CLK - Clock Resistance - kW 175 200 400 300 200 100 0 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) C006 Figure 32. Low-Range RT Figure 31. High-Range RT 7.3.12 Overcurrent Protection and Frequency Shift The TPS54260-Q1 implements current mode control which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high input voltages the TPS54260-Q1 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Because the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still have frequency shift protection. During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. The frequency shift effectively increases the off time allowing the current to ramp down. 7.3.13 Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 8 and Equation 9. Equation 8 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value causes the regulator to skip switching pulses. Equation 9 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the ƒsw(maxshift) frequency. In Equation 9, to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 V, the ƒdiv integer increases from 1 to 8 corresponding to the frequency shift. In Figure 33, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.130Ω, FET on resistance of 0.2 Ω and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching frequency. 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) æ 1 ö æ (IL ´ Rdc + VOUT + Vd) ö fSW (max skip ) = ç ÷ ÷ ´ çç ÷ è tON ø è (VIN - IL ´ Rhs + Vd) ø (8) fdiv æ (IL ´ Rdc + VOUTSC + Vd) ö ´ç fSW (shift ) = ÷ tON çè (VIN - IL x Rhs + Vd) ÷ø where • • • • • • • • • IL = Inductor current Rdc = Inductor resistance VIN = Maximum input voltage VOUT = Output voltage VOUTSC = Output voltage during short Vd = Diode voltage drop RDS(on) = Switch on-resistance tON = Controllable on time ƒDIV = Frequency divide equals (1, 2, 4, or 8) (9) 2500 fs - Switching Frequency - kHz VO = 3.3 V 2000 Shift 1500 Skip 1000 500 0 10 20 30 VI - Input Voltage - V 40 Figure 33. Maximum Switching Frequency vs Input Voltage 7.3.14 How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 34. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device has the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommends to use a frequency set resistor connected as shown in Figure 34 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100 ms. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 19 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) When the device transitions from the PLL to resistor mode the switching frequency slows down from the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage and the resistor then sets the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 35, Figure 36, and Figure 37 show the device synchronized to an external system clock in continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse skip mode (psm). TPS54260-Q1 10 pF 4 kW PLL Rfset EXT Clock Source 50 W RT/CLK Figure 34. Synchronizing to a System Clock PH PH EXT EXT IL IL Figure 35. Plot of Synchronizing in CCM 20 Figure 36. Plot of Synchronizing in DCM Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) PH EXT IL Figure 37. Plot of Synchronizing in PSM 7.3.15 Power Good (PWRGDPin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. TI recommends to use a pull-up resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD achieves full current sinking capability as VIN input voltage approaches 3 V. The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low. 7.3.16 Overvoltage Transient Protection (OVTP) The TPS54260-Q1 incorporates an OVTP circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. 7.3.17 Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence by discharging the SS/TR pin. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 21 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) 7.3.18 Small Signal Model for Loop Response Figure 38 shows an equivalent model for the TPS54260-Q1 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA of 310 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode designs. PH VO Power Stage gmps 10.5 A/V a b R1 RESR RL COMP c 0.8 V CO R3 C2 RO COUT VSENSE gmea 350 mA/V R2 C1 Figure 38. Small-Signal Model for Loop Response 7.3.19 Simple Small-Signal Model for Peak Current Mode Control Figure 39 describes a simple small-signal model that can be used to understand how to design the frequency compensation. The TPS54260-Q1 power stage is approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 10 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 38) is the power stage transconductance. The gmPS for the TPS54260-Q1 is 10.5 A/V. The low-frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 11. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of Figure 39. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases from the ESR zero at the lower frequencies (see Equation 13). 22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 39. Simple Small-Signal Model and Frequency Response for Peak Current Mode Control æ s ö ç1 + ÷ 2p ´ fZ ø VOUT = Adc ´ è VC æ s ö ç1 + ÷ 2 p ´ fP ø è Adc = gmps ´ RL (10) (11) 1 fP = COUT ´ RL ´ 2p (12) 1 fZ = COUT ´ RESR ´ 2p (13) 7.3.20 Small-Signal Model for Frequency Compensation The TPS54260-Q1 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 40. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors.. Equation 14 and Equation 15 show how to relate the frequency response of the amplifier to the small signal model in Figure 40. The open-loop gain and bandwidth are modeled using the RO and CO shown in Figure 40. See the Figure 41 for a design example using a Type 2A network with a low ESR output capacitor. Equation 14 through Equation 23 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application section or use switched information. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 23 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 40. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 41. Frequency Response of the Type 2a and Type 2b Frequency Compensation Aol(V/V) gmea gmea = 2p ´ BW (Hz) Ro = CO (14) (15) æ ö s ç1 + ÷ 2p ´ fZ1 ø è EA = A0 ´ æ ö æ ö s s ç1 + ÷ ´ ç1 + ÷ 2p ´ fP1 ø è 2p ´ fP2 ø è A0 = gmea A1 = gmea P1 = 24 R2 ´ Ro ´ R1 + R2 R2 ´ Ro| | R3 ´ R1 + R2 (16) (17) (18) 1 2p ´ Ro ´ C1 (19) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Feature Description (continued) Z1 = P2 = 1 2p ´ R3 ´ C1 (20) 1 type 2a 2p ´ R3 | | RO ´ (C2 + CO ) (21) 1 P2 = type 2b 2p ´ R3 | | RO ´ CO P2 = 2p ´ R O (22) 1 type 1 ´ (C2 + C O ) (23) 7.4 Device Functional Modes 7.4.1 Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 42 using two TPS54260-Q1 devices. The power good is coupled to the EN pin on the TPS54260-Q1 which enables the second power supply once the primary supply reaches regulation. If needed, a 1 nF ceramic capacitor on the EN pin of the second power supply provides a 1 ms start-up delay. Figure 43 shows the results of Figure 42. TPS54260-Q1 EN PWRGD EN EN1 SS /TR SS /TR PWRGD1 PWRGD VOUT1 VOUT2 Figure 42. Schematic for Sequential Start-Up Sequence Figure 43. Sequential Startup Using EN and PWRGD Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 25 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) TPS54260-Q1 3 EN 4 SS/TR 6 PWRGD TPS54260-Q1 3 EN 4 SS/TR 6 PWRGD Figure 44. Schematic for Ratiometric Startup Using Coupled SS/TR Pins EN1, EN2 VOUT1 VOUT2 Figure 45. Ratiometric Startup Using Coupled SS/TR Pins 26 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Device Functional Modes (continued) Figure 44 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs ramps up and reaches regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 6. Figure 45 shows the results of Figure 44. TPS54260-Q1 EN VOUT 1 SS/TR PWRGD TPS54260-Q1 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 46. Schematic for Ratiometric and Simultaneous Start-Up Sequence Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 46 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 24 and Equation 25, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 26 is the voltage difference between Vout1 and Vout2 at the 95% of nominal output regulation. The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 24 through Equation 26 for deltaV. Equation 26 results in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Because the SS/TR pin must be pulled below 40mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure the calculated R1 value from Equation 24 is greater than the value calculated in Equation 27 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure 23. Vout2 + deltaV Vssoffset R1 = ´ VREF Iss (24) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 27 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Device Functional Modes (continued) VREF ´ R1 Vout2 + deltaV - VREF deltaV = Vout1 - Vout2 R1 > 2800 ´ Vout1 - 180 ´ deltaV R2 = (25) (26) (27) EN EN VOUT1 VOUT1 VOUT2 Figure 47. Ratiometric Startup With VOUT2 Leading VOUT1 VOUT2 Figure 48. Ratiometric Startup With VOUT1 Leading VOUT2 EN VOUT1 VOUT2 Figure 49. Simultaneous Startup With Tracking Resistor 28 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS54260 DC-DC converter is designed to provide up to a 2.5-A output from an input voltage source of 3.5 V to 60 V. The high-side MOSFET is incorporated inside the TPS54260 package along with the gate drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS54260 to achieve high efficiencies and helps keep the junction temperature low at high output currents. The compensation components are external to the integrated circuit (IC), and an external divider allows for an adjustable output voltage. Additionally, the TPS54260 provides adjustable slow start and undervoltage lockout inputs. 8.2 Typical Application TPS54260-Q1 Figure 50. 3.3-V Output TPS54260-Q1 Design Example 8.2.1 Design Requirements This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, use the following known parameters: Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Output voltage 3.3 V Transient response 0- to 1.5-A load step ΔVout = 3 % Maximum output current 2.5 A Input voltage 12 V nom. 10.8 to 13.2 V Output voltage ripple 1% of Vout Start input voltage (rising VIN) 6V Stop input voltage (falling VIN) 5.5 V Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 29 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 Selecting The Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, the user chooses the highest switching frequency possible because it produces the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage and the output voltage and the frequency shift limitation. Equation 8 and Equation 9 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short circuit. The typical minimum on time, tonmin, is 135 ns for the TPS54260-Q1. For this example, the output voltage is 3.3 V and the maximum input voltage is 13.2 V, which allows for a maximum switch frequency up to 2247 kHz when including the inductor resistance, on resistance output current and diode voltage in Equation 8. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 9 or the solid curve in Figure 33 to determine the maximum switching frequency. With a maximum input voltage of 13.2 V, assuming a diode voltage of 0.7 V, inductor resistance of 26 mΩ, switch resistance of 200 mΩ, a current limit value of 3.5 A and a short circuit output voltage of 0.2 V. The maximum switching frequency is approximately 4449 kHz. For this design, a much lower switching frequency of 300 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 7 or the curve in Figure 32. The switching frequency is set by resistor R3 shown in Figure 50 For 300 kHz operation a 412 kΩ resistor is required. 8.2.2.2 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the PWM control system, the inductor ripple current should always be greater than 150 mA for dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 11 μH. For this design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 30 and Equation 31. For this design, the RMS inductor current is 2.51 A and the peak inductor current is 2.913 A. The chosen inductor is a Coilcraft MSS1038-103NLB . It has a saturation current rating of 4.52 A and an RMS current rating of 4.05 A. As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increase the output voltage ripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. 30 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com Lo min = IRIPPLE = IL(rms) = SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 Vinmax - Vout Vout ´ Io ´ KIND Vinmax ´ ƒsw VOUT ´ (Vin max (28) - VOUT ) Vin max ´ L O ´ fSW 1 - VOUT ) ö ÷ ÷ Vinmax ´ LO ´ fSW ø æ VOUT ´ (IO )2 + 12 ´ çç è (29) (Vinmax 2 (30) Iripple ILpeak = Iout + 2 (31) 8.2.2.3 Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulators responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also temporarily is not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance necessary to accomplish this. Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 3% change in Vout for a load step from 1.5 A to 2.5 A (full load). For this example, ΔIout = 2.5 – 1.5 = 1 A and ΔVout = 0.03 × 3.3 = 0.099 V. Using these numbers gives a minimum capacitance of 67 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The catch diode of the regulator can not sink current so any stored energy in the inductor produces an output voltage overshoot when the load current rapidly decreases, see Figure 51. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step is from 2.5 A to 1.5 A. The output voltage increases during this load transition and the stated maximum in our specification is 3% of the output voltage. This makes Vf = 1.03 × 3.3 = 3.399. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 60 μF. Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. Equation 34 yields 12 μF. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 35 indicates the ESR should be less than 36 mΩ. The most stringent criteria for the output capacitor is 67 μF of capacitance to keep the output voltage in regulation during an load transient. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 31 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which increases this minimum value. For this example, 2 × 47 μF, 10 V ceramic capacitors with 3 mΩ of ESR is used. The derated capacitance is 72.4 µF, above the minimum required capacitance of 67 µF. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields 238 mA. 2 ´ DIOUT COUT > fSW ´ DVOUT (32) ((I ) - (I ) ) ´ ((V ) - (V ) ) 2 OH COUT > LO 2 f 1 Cout > 2 OL 8 ´ ¦ sw ´ 2 i (33) 1 VORIPPLE IRIPPLE (34) V RESR < ORIPPLE IRIPPLE Icorms = (35) Vout ´ (Vin max - Vout) 12 ´ Vin max ´ Lo ´ ¦ sw (36) 8.2.2.4 Catch Diode The TPS54260-Q1 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator. Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Although the design example has an input voltage up to 13.2 V, a diode with a minimum of 60-V reverse voltage is selected. For the example design, the B360B-13-F Schottky diode is selected for its lower forward voltage and it comes in a larger package size which has good thermal characteristics over small devices. The typical forward voltage of the B360B-13-F is 0.70 volts. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power dissipation, conduction losses plus ac losses, of the diode. The B360B-13-F has a junction capacitance of 200 pF. Using Equation 37, the selected diode dissipates 1.32 W. If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diode which has a low leakage current and slightly higher forward voltage drop. 2 Pd = 32 (Vin max - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin + Vƒd) + 2 Vin max Submit Documentation Feedback (37) Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 8.2.2.5 Input Capacitor The TPS54260-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54260Q1. The input ripple current can be calculated using Equation 38. The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreases as the dc bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V so a 100 V capacitor should be selected. For this example, two 2.2 μF, 100 V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 39. Using the design example values, Ioutmax = 2.5 A, Cin = 4.4 μF, ƒsw = 300 kHz, yields an input voltage ripple of 206 mV and a rms input ripple current of 1.15 A. Icirms = Iout ´ Vout ´ Vin min (Vin min - Vout ) Vin min (38) Iout max ´ 0.25 ΔVin = Cin ´ ¦ sw (39) Table 2. Capacitor Types VENDOR VALUE (μF) 1 to 2.2 Murata 1 to 4.7 1 1 to 2.2 1 10 1.8 Vishay 1 to 1.2 1 to 3.9 1 to 1.8 1 to 2.2 TDK 1.5 to 6.8 1 to 2.2 1 to 3.3 1 to 4.7 AVX 1.0 1 to 4.7 1 to 2.2 EIA Size 1210 1206 2220 2225 1812 1210 1210 1812 VOLTAGE DIALECTRIC 100 V COMMENTS GRM32 series 50 V 100 V GRM31 series 50 V 50 V 100 V VJ X7R series 50 V 100 V 100 V 50 V 100 V 50 V X7R C series C4532 C series C3225 50 V 100 V 50 V X7R dielectric series 100 V 8.2.2.6 Slow-Start Capacitor The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54260-Q1 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 33 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the effective output capacitance of 72.4 µF up to 3.3 V while only allowing the average output current to be 1 A would require a 0.19 ms slow-start time. Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical because the output capacitor value is 2 × 47μF which does not require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of 3.5 ms which requires a 8.75 nF slow start capacitor. For this design, the next larger standard value of 10 nF is used. Cout ´ Vout ´ 0.8 tss > Issavg (40) 8.2.2.7 Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10 V or higher voltage rating. 8.2.2.8 UVLO Set Point The UVLO can be adjusted using an external voltage divider on the EN pin of the TPS54260-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 6 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 5.5 V (UVLO stop). The programmable UVLO and enable voltages are set using the resistor divider of R1 and R2 between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 124 kΩ between Vin and EN (R1) and a 30.1 kΩ between EN and ground (R2) are required to produce the 6- and 5.5-V start and stop voltages. 8.2.2.9 Output Voltage and Feedback Resistors Selection The voltage divider of R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was selected for R6. Using Equation 1, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values decrease quiescent current and improve efficiency at low output currents but may introduce noise immunity problems. 8.2.2.10 Compensation There are several methods used to compensate DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more accurate design. To get started, the modulator pole, fpmod, and the esr zero, ƒz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, ƒco, to design the compensation. For the example design, ƒpmod is 1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and Equation 44 gives 13.4 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, a higher fco is desired to improve transient response. the target fco is 35 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. Ioutmax ¦p mod = 2 × p × Vout × Cout (41) 34 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 ¦ z mod = 1 2 ´ p ´ Resr × Cout (42) fco = f p mod ´ f z mod (43) fco = f f p mod ´ sw 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 10.5 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 310 μA/V, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 4740 pF for compensating capacitor C5, a 4700 pF is used for this design. ö æ 2 ´ p ´ fco ´ Cout ö æ Vout R4 = ç ÷ ÷´ç gmps è ø è Vref ´ gmea ø 1 C5 = 2 ´ p ´ R4 ´ fpmod (45) (46) A compensation pole can be implemented if desired using an additional capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole. C8 is not used for this design example. C ´ Re sr C8 = o R4 (47) C8 = 1 R4 ´ f sw ´ p (48) 8.2.2.11 Discontinuous Mode and Eco-mode Boundary With an input voltage of 12 V, the power supply enters discontinuous mode when the output current is less than 337 mA. The power supply enters Eco-mode when the output current is lower than 5 mA. The input current draw at no load is 392 μA. 8.2.2.12 Power Dissipation The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq). Vout Pcon = Io2 ´ RDS(on) ´ Vin (49) Psw = Vin 2 ´ ¦ sw ´ lo ´ 0.25 ´ 10-9 Pgd = Vin ´ 3 ´ 10 Pq = 116 ´ 10 -6 -9 (50) ´ ¦ sw (51) ´ Vin Where: • • • • • IOUT is the output current (A) RDS(on) is the on-resistance of the high-side MOSFET (Ω) VOUT is the output voltage (V) VIN is the input voltage (V) ƒsw is the switching frequency (Hz) (52) So Ptot = Pcon + Psw + Pgd + Pq (53) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 35 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com For given TA, TJ = TA + Rth × Ptot (54) For given TJMAX = 150°C TAmax = TJmax – Rth × Ptot where • • • • • • Ptot is the total device power dissipation (W) TA is the ambient temperature (°C) TJ is the junction temperature (°C) Rth is the junction-to-ambient thermal resistance of the IC on the PCB layout (°C/W) TJMAX is maximum junction temperature (°C) TAMAX is maximum ambient temperature (°C) (55) There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and trace resistance that impact the overall efficiency of the regulator. 36 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 8.2.3 Application Curves Vout = 50 mv / div (ac coupled) Vin = 10 V / div Vout = 2 V / div Output Current = 1 A / div (Load Step 1.5 A to 2.5 A) EN = 2 V / div SS/TR = 2 V / div Time = 200 usec / div Time = 5 msec / div Figure 51. Load Transient Figure 52. Startup With VIN Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 2 usec / div Figure 53. Output Ripple, CCM Figure 54. Output Ripple, DCM Vin = 200 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 10 usec / div Figure 55. Output Ripple, PSM Figure 56. Input Ripple, CCM Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 37 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 100 90 Vin = 50 mV / div (ac coupled) 80 Efficiency - % 70 PH = 5 V / div 60 50 40 30 VIN=12V VOUT=3.3V fsw=300kHz 20 10 Time = 2 usec / div 0 0 0.5 Figure 57. Input Ripple, DCM 2.5 1.0 1.5 2.0 IO - Output Current - A 3.0 Figure 58. Efficiency vs Load Current 100 60 180 90 40 80 120 Phase 70 60 Gain 50 40 0 0 -20 30 VIN=12V VOUT=3.3V fsw=300kHz 20 -60 VIN=12 V VOUT=3.3V IOUT=2.5A -40 10 0 0.001 0.1 0.01 IO - Output Current - A -60 10 3.4 3.4 3.38 3.38 VO - Output Voltage - V VO - Output Voltage - V -120 1-104 1-103 f - Frequency - Hz 100 3.36 3.34 3.32 3.36 3.34 VIN=12V VOUT=3.3V fsw=300kHz IOUT=1.5A 3.32 VIN=12V VOUT=3.3V fsw=300kHz 3.3 0.5 1.5 1.0 2.0 IO - Output Current - A 2.5 Figure 61. Regulation vs Load Current 38 -180 1-106 1-105 Figure 60. Overall Loop Frequency Response Figure 59. Light-Load Efficiency 0 Phase - o Gain - dB Efficiency - % 20 60 3.0 3.3 10.8 11.2 11.6 12.4 12 IO - Output Current - A 12.8 13.2 Figure 62. Regulation vs Input Voltage Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 9 Power Supply Recommendations The input decoupling capacitors and bootstrap capacitor must be located as close as possible to the TPS54260Q1. In addition, the voltage set-point resistor divider components must also be kept close to the IC. The voltage divider network ties the output voltage to the point of regulation, the copper VOUT trace past the output capacitors. Ensure that input power supply is clean. TI recommends adding an additional input bulk capacitor depending on the board connection to the input supply. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 63 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. 10.1.1 Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 50 is 0.55 in2. This area does not include test points or connectors. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 39 TPS54260-Q1 SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 www.ti.com 10.2 Layout Example This layout example is shown for the HVSSOP (DGQ) package. The VSON (DRC) package can also use this layout example because the pin assignments on the VSON package are the same as the HVSSOP package. Vout Output Capacitor Topside Ground Area Input Bypass Capacitor Vin UVLO Adjust Resistors Slow Start Capacitor Output Inductor Route Boot Capacitor Trace on another layer to provide wide path for topside ground BOOT Catch Diode PH VIN GND EN COMP SS/TR VSENSE RT/CLK PWRGD Frequency Set Resistor Compensation Network Resistor Divider Thermal VIA Signal VIA Figure 63. PCB Layout Example 40 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 TPS54260-Q1 www.ti.com SLVSAH8F – DECEMBER 2010 – REVISED AUGUST 2015 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks Eco-mode, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54260-Q1 41 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54260QDGQRQ1 ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 5426Q TPS54260QDRCRQ1 ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 5426Q TPS54260QDRCTQ1 ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 5426Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of