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TPS54292PWPR

TPS54292PWPR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    HTSSOP-16_5X4.4MM-EP

  • 描述:

    IC REG BUCK ADJ DL 16HTSSOP

  • 数据手册
  • 价格&库存
TPS54292PWPR 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 TPS5429x 1.5-A and 2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET 1 Features 3 Description • • • • The TPS54290, TPS54291, and TPS54292 devices are dual-output, fully synchronous buck converters capable of supporting applications with a minimal number of external components. It operates from a 4.5-V to 18-V input supply voltage, and supports output voltages as low as 0.8 V and as high as 90% of the input voltage. 1 • • • • • • • • • • • 4.5-V to 18-V Input Range Output Voltage Range 0.8 V to DMAX × VIN Fully Integrated Dual Buck: 1.5 A and 2.5 A Three Fixed Switching Frequency Versions: – TPS54290: 300 kHz – TPS54291: 600 kHz – TPS54292: 1.2 MHz Integrated UVLO 0.8 VREF With 1% Accuracy (0°C to 85°C) Internal Soft Start: – TPS54290: 5.2 ms – TPS54291: 2.6 ms – TPS54292: 1.3 ms Dual PWM Outputs 180° Out-of-Phase Dedicated Enable for Each Channel Current Mode Control for Simplified Compensation External Compensation Pulse-by-Pulse Overcurrent Protection, 2.2-A and 3.8-A Overcurrent Limit Integrated Bootstrap Switch Thermal Shutdown Protection at 145°C 16-Pin PowerPAD™ HTSSOP Package Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. Channel 1 can provide up to 1.5 A of continuous current. Meanwhile, Channel 2 supports up to 2.5 A. Current mode control simplifies the compensation. The external compensation adds flexibility for the user to choose different type of output capacitors. 180° out-of-phase operation reduces the ripple current through the input capacitor, providing the benefit of reducing input capacitance, alleviating EMI and increasing capacitor life. Device Information(1) PART NUMBER TPS54290 TPS54291 TPS54292 PACKAGE HTSSOP (16) BODY SIZE (NOM) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • Set-Top Boxes Digital TVs Power for DSP Consumer Electronics Simplified Schematic VIN TPS54290 VOUT1 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 4 PGND1 5 EN1 BP 12 6 EN2 GND 11 7 FB1 FB2 10 8 COMP1 COMP2 GND SW2 14 VOUT2 PGND2 13 9 UDG-09130 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 5 6 8 Detailed Description ............................................ 10 8.1 8.2 8.3 8.4 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 11 17 9.1 Application Information .......................................... 18 9.2 Typical Applications ................................................ 18 10 Power Supply Recommendations ..................... 25 11 Layout................................................................... 25 11.1 Layout Guidelines ................................................. 11.2 Layout Examples................................................... 11.3 Overtemperature Protection and Junction Temperature Rise .................................................... 11.4 Power Derating ..................................................... 25 26 27 28 12 Device and Documentation Support ................. 29 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 29 29 29 29 29 29 29 13 Mechanical, Packaging, and Orderable Information ........................................................... 30 Application and Implementation ........................ 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2009) to Revision A Page • Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1 • Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1 • Deleted Lead temperature (260°C maximum)........................................................................................................................ 5 • Added Thermal Information table to replace the Package Dissipation Ratings table ............................................................ 5 2 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 5 Device Comparison Table DEVICE DESCRIPTION TPS40222 5-V Input, 1.5-A, Non-Synchronous Buck Converter TPS5428x 2-A Dual Non-Synchronous Converter with Integrated High-Side FET TPS5538x 3-A Dual Non-Synchronous Converter with Integrated High-Side FET 6 Pin Configuration and Functions PWP Package 16-Pin HTSSOP Top View PVDD1 1 16 PVDD2 BOOT1 2 15 BOOT2 SW1 3 14 SW2 PGND1 4 13 PGND2 Thermal Pad EN1 5 12 BP EN2 6 11 GND FB1 7 10 FB2 COMP1 8 9 COMP2 Not to scale Pin Functions PIN NO. NAME 1 PVDD1 I/O DESCRIPTION I Power input to the Output1 high-side MOSFET only. This pin must be locally bypassed to PGND1 with a low-ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together. 2 BOOT1 I Input supply to the high-side gate driver for Output1. Connect a 22-nF to 68-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the off-time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap capacitor. 3 SW1 O Source (switching) output for Output1 PWM 4 PGND1 — Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal logic circuits. 5 EN1 I Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass the enable function. 6 EN2 I Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft start of Output2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass the enable function. 7 FB1 I Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Outputx to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. 8 COMP1 O Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to GND. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 3 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com Pin Functions (continued) PIN NO. 9 NAME COMP2 I/O DESCRIPTION O Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to GND. Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Outputx to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. 10 FB2 I 11 GND — Analog ground pin for the device. 12 BP — Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR, 4.7-µF ceramic capacitor (10-µF capacitor preferred). 13 PGND2 — Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal logic circuits. 14 SW2 O Source (switching) output for Output2 PWM. I Input supply to the high-side gate driver for Output2. Connect a 22-nF to 68-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the off-time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap capacitor. The PVDD2 pin provides power to the device control circuitry, provides the pullup for the EN1 and EN2 pins and provides power to the Output2 high-side MOSFET. This pin must be locally bypassed to PGND2 with a low-ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.2 V. 15 BOOT2 16 PVDD2 I — Thermal Pad — 4 Submit Documentation Feedback This pad must be tied externally to a ground plane. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) PVDD1, PVDD2, EN1, EN2 MIN MAX UNIT –0.3 20 V SW1, SW2 BOOT1, BOOT2 –1 20 V –0.3 SW + 7 V –3 20 V 7 V SW1, SW2 transient (< 50 ns) BP FB1, FB2 –0.3 3 V Operating junction temperature, TJ –40 145 °C Storage temperature, Tstg –55 155 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VDD Input voltage 4.5 18 UNIT V TJ Junction temperature –40 125 °C 7.4 Thermal Information THERMAL METRIC (1) TPS54290 TPS54291 TPS54292 UNIT PWP (HTSSOP) 16 PINS RθJA Junction-to-ambient thermal resistance 39.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.7 °C/W RθJB Junction-to-board thermal resistance 22.3 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 22.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 5 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 7.5 Electrical Characteristics TJ = –40°C to 125°C, PVDD1 and PVDD2 = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 18 V 80 160 µA 1.65 3 mA INPUT SUPPLY PVDD1, PVDD2 Input voltage range IDDSDN Shutdown current EN1 = EN2 = PVDD2 (4.5 V to 18 V) 4.5 IDDQ Quiescent, non-switching FB1 = FB2 = 1 V, outputs off IDDSW Quiescent, while switching FB1 = FB2 = 0.75 V, measured at BP UVLO Minimum turnon voltage PVDD2 only UVLOHYS Hysteresis tstart (1) (2) Time from start-up to soft start begin 10 3.8 CBP = 10 µF, EN1 and EN2 go low simultaneously mA 4.1 4.4 V 460 600 mV 1.5 ms ENABLE (ACTIVE LOW) Enable threshold voltage VENx 0.9 Hysteresis 1.2 1.5 70 IENx Enable pullup current tENx (1) Time from enable to soft start begin Other enable pin = GND BP Regulator voltage 8 V ≤ VPVDD2 ≤ 18 V BPLDO Dropout voltage VPVDD2 = 4.5 V IBPS Regulator short current 4.5 V ≤ VPVDD2 ≤ 18 V V mV 10 10 µA µs BP REGULATOR 5 5.2 5.6 V 400 mV 25 mA OSCILLATOR TPS54290 fSW Oscillator frequency tDEAD (1) 260 300 360 TPS54291 520 600 720 TPS54292 1040 1200 1440 Clock dead time 140 kHz kHz ns gMTRANSCONDUCTANCE AMPLIFIER AND VOLTAGE REFERENCE (APPLIES TO BOTH CHANNELS) VFB Feedback input voltage IFB Feedback Input bias current gM (1) Transconductance ISOURCE Error amplifier source current capability ISINK Error amplifier sink current capability 0°C < TJ < 85°C 792 800 808 mV –40ºC < TJ < 125°C 786 800 812 mV 5 50 nA 200 325 450 µS VFB1 = VFB2 = 0.7 V, VCOMP = 0 V 15 30 40 µA VFB1 = VFB2 = 0.9 V, VCOMP = 2 V 15 30 40 µA TPS54290, 0 V ≤ VFB ≤ 0.8 V 4 5.2 6 TPS54291 2 2.6 3 TPS54292 1 1.3 1.6 VFB = 0.8 V SOFT START (APPLIES TO BOTH CHANNELS) tSS Soft-start time ms OVERCURRENT PROTECTION ICL1 Current limit CH1 1.8 2.2 2.6 ICL2 Current limit CH2 3.2 3.8 4.6 THICCUP (1) Hiccup timeout TPS54290 30 TPS54291 16 TPS54292 tONOC (1) (1) (2) 6 A A ms 8 Minimum overcurrent pulse 150 200 ns Specified by design. Not tested in production. When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value (see Input UVLO and Start-Up) Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 Electrical Characteristics (continued) TJ = –40°C to 125°C, PVDD1 and PVDD2 = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOOTSTRAP (APPLIED TO BOTH CHANNELS) RBOOT Bootstrap switch resistance R(BP to BOOT), I external = 10 mA 33 Ω PGOOD VUV Feedback voltage limit for PGOOD 660 VPG-HYST (1) PGOOD hysteresis voltage on FB 40 730 mV mV OUTPUT STAGE (APPLIED TO BOTH CHANNELS) RDS(on1)(HS) (1) On-resistance of high-side FET and bondwire on CH1 170 265 mΩ RDS(on2)(HS) (1) On-resistance of high-side FET and bondwire on CH2 120 190 mΩ RDS(on1)(LS) (1) On-resistance of low-side FET and bondwire on CH1 120 190 mΩ RDS(on2)(LS) (1) On-resistance of low-side FET and bondwire on CH2 90 150 mΩ tON_MIN (1) Minimum controllable pulse width Minimum duty cycle tDEAD (1) VFB = 0.9 V Output driver dead time DMAX 150 Maximum duty cycle ns 0% HDRV off to LDRV on LDRV off to HDRV on 20 ns 20 ns TPS54290 90% 96% TPS54291 85% 91% TPS54292 78% 82% THERMAL SHUTDOWN TSD (1) TSD_HYS Shutdown temperature (1) Hysteresis Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 145 °C 20 °C Submit Documentation Feedback 7 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 7.6 Typical Characteristics 1.75 140 Non-Switching 120 ISD – Shutdown Current – mA IDDQ – Quiescent Current – mA 1.70 1.65 1.60 VIN = 18 V 100 80 VIN = 12 V 60 40 1.55 VIN = 4.5 V 20 1.50 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 2. Shutdown Current vs Temperature 1.26 4.1 1.24 VEN – Enable Voltage Threshold – V VUVLO – Undervoltage Lockout Threshold Voltage – V Figure 1. Quiescent Current vs Temperature 4.2 UVLO ON 1.22 4.0 1.20 3.9 Enable OFF 1.18 3.8 Enable ON 1.16 UVLO OFF 3.7 1.14 3.6 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 1.12 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 3. UVLO Turnon and Turnoff Thresholds vs Temperature Figure 4. ENx Turnon and Turnoff Threshold vs Temperature 1.4 6 tSS – Soft-Start Time – ms 4 fSW = 300 kHz fSW = 600 kHz 3 2 1 8 fSW – Switching Frequency – MHz 1.2 5 1.0 fSW = 1.2 MHz fSW = 600 kHz 0.8 0.6 0.4 0.2 fSW = 1.2 MHz 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C fSW = 300 kHz 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 5. Soft-Start Time vs Temperature Figure 6. Oscillator Frequency vs Temperature Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 808 4.50 806 4.25 804 4.00 Channel2 IILIMx – Current Limit – A VFB – Feedback Voltage – mV Typical Characteristics (continued) 3.75 802 3.50 800 3.25 798 3.00 796 2.75 794 Channel1 792 2.50 790 2.25 788 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 2.00 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 8. Current Limit vs Temperature Figure 7. Feedback Voltage vs Temperature 5.20 9 VBP – BP Regulation Voltage – V ISW(off) – Switch-Node Current – mA 8 5.15 5.10 5.05 VVDD = 12 V 5.00 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 9. BP Voltage vs Temperature 7 6 5 4 3 2 1 0 -1 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 10. SW Node Leakage Current vs Temperature Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 9 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The TPS5429x is a dual-output fully synchronous buck converter. Each PWM channel contains an error amplifier, current mode pulse width modulator (PWM), switching and rectifying MOSFETs, enable, and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, and clock oscillator. 8.2 Functional Block Diagram BP f(IDRAIN1) + DC(ofst) Current Comparator FET Switch CLK1 + COMP1 8 f(IDRAIN1) FB1 + R R Q 1 PVDD1 IDRAIN1 3 SW1 4 PGND1 BP Overcurrent Comp f(ISLOPE1) Soft Start 1 Q BOOT1 + 7 0.8 VREF S 2 f(IMAX1) CLK1 Anti-Cross Conduction SD1 TSD 10 mA (max) EN1 EN2 10 mA (max) 5 SD1 Internal Control 6 f(ISLOPE1) Ramp Gen 1 SD2 UVLO FB1 FB2 2.4 MHz Oscilator CLK1 Divide by 2/4/8 f(ISLOPE2) Ramp Gen 2 Output Undervoltage Detect CLK2 PVDD2 BP 12 5.25-V Regulator References GND 11 BP 15 BOOT2 f(IDRAIN2) + DC(ofst) Current Comparator 16 PVDD2 FET Switch CLK2 + COMP2 9 f(IDRAIN2) FB2 10 0.8 VREF + SD2 Q R R Q IDRAIN2 14 SW2 + BP Overcurrent Comp f(ISLOPE2) Soft Start 2 S f(IMAX2) CLK2 Anti-Cross Conduction 13 PGND2 FET Switch UDG-09124 Copyright © 2016, Texas Instruments Incorporated 10 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 8.3 Feature Description 8.3.1 Voltage Reference The band-gap cell common to both outputs, trimmed to 800 mV. The reference voltage is 1% accurate in the temperature range from 0°C to 85°C. 8.3.2 Oscillator The oscillator frequency is internally fixed at 2.4 MHz that is divided by 8/4/2 to generate the ramps for TPS5429x, respectively. The two outputs are internally configured to operate on alternating switch cycles (that is, 180° out-of-phase). 8.3.3 Input UVLO and Start-Up When the voltage at the PVDD2 pin is less than 4.4 V, a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turnon threshold, the state of the enable pins determines the remainder of the internal start-up sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start commences. NOTE The internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be higher or lower than PVDD2. 8.3.4 Enable and Timed Turnon of the Outputs Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.25 V with an external circuit, the associated output is enabled and soft start is initiated. If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator shuts down and minimal house keeping functions are active. The total standby current from both PVDD pins is 80 µA at 12-V input supply. An R-C connect to an ENx pin may be used to delay the turnon of the associated output after power is applied to PVDDx (see Figure 11). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.25 V, then the output is enabled and the start-up sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to the PVDD2 pin, then omit these two components and tie the ENx pin to GND directly. If an R-C circuit is used to delay the turnon of the output, the resistor value must be an order of magnitude less than 1.25 V / 10 µA or 120 kΩ. A suggested value is 51 kΩ. This allows the ENx voltage to decay below the 1.25-V threshold while the 10-µA bias current flows. The time to start (after the application of PVDD2) is Equation 1. æ VTH - I ´R ö ENx ÷ (s ) tSTART = -R ´ C ´ ln ç ç VIN - 2 ´ Iuuuuur ´ R ÷ ENx è ø ( ) where • • • R and C are the timing components VTH is the 1.25-V enable threshold voltage IEN is the 10-µA maximum enable pin biasing current (1) Figure 11 and Figure 12 illustrate startup delay with an R-C filter on the enable pin(s). Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 11 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) PVDD2 10 mA (max) ENx C + PVDDx R PVDDx 1.25 V 1.25-V Threshold TPS5429x UDG-09125 ENxB Copyright © 2016, Texas Instruments Incorporated VOUTx Time 0 Figure 11. Start-Up Delay Schematic tDELAY tDELAY + tSS Figure 12. Start-Up Delay Timing Diagram NOTE If delayed output voltage start-up is not necessary, simply connect EN1 and EN2 to GND. This allows the outputs to start immediately on the valid application of PVDD2. If ENx is allowed to go high after the Outputx has been in regulation, the upper and lower MOSFETs shut off, and the output decays at a rate determined by the output capacitor and the load. 8.3.5 Soft Start Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of the two noninverting inputs of the error amplifier. The other input is the internal precise 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 5.2 ms, 2.6 ms, and 1.3 ms for TPS54190, TPS54191, and TPS54192, respectively. During a soft-start interval, the TPS5429x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the noninverting input to the error amplifier reaches the internal 0.8-V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains at the reference voltage. During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six PWM pulses is skipped to allow the inductor current to decay before another PWM pulse is applied (see Output Overload Protection). There is no pulse skipping if a current limit pulse is not detected. If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time soft start completes, the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay start-up from the ENx pin to delay the start-up of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. 8.3.6 Output Voltage Regulation The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (Figure 13). The value of the output voltage is shown in Equation 2. R1 ö æ VOUT = VREF ´ ç 1 + ÷ (V ) R2 è ø where • 12 VREF is the internal 0.8-V reference voltage Submit Documentation Feedback (2) Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 Feature Description (continued) TPS54290 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 4 PGND1 5 EN1 BP 12 6 EN2 GND 11 7 FB1 FB2 10 8 COMP1 VOUT1 R1 R2 SW2 14 PGND2 13 COMP2 9 UDG-09131 Copyright © 2016, Texas Instruments Incorporated Figure 13. Feedback Network for Channel 1 8.3.7 Inductor Selection Equation 3 calculates the inductance value so that the output ripple current falls from 20% to 40% of the full load current. V - V OUT L = IN DIOUT (3) 8.3.8 Maximum Output Capacitance With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance which may be used before start-up problems begin to occur. If the output capacitance is large enough so that the device enters a current-limit protection mode during start-up, then there is a possibility that the output never reaches regulation. Instead, the TPS5429x simply shuts down and attempts a restart as if the output were shortcircuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is given by Equation 4. C OUT(max) = æ t SS æI ´ ç ILIM - ILOAD - ç RIPPLE VOUT è 2 è öö ÷÷ øø where • • tSS is the soft-start time ILIM is the current limit level (4) 8.3.9 Feedback Loop Compensation In the feedback signal path, the output voltage setting divider is followed by an internal gM-type error amplifier with a typical transconductance of 325 µS. An external series connected R-C circuit from the gM amplifier output (COMPx pin) to ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 14. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 13 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) NOTE Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow pulse width operation, especially at load currents less than 1 A. BP ICOMP – ISLOPE Error Amplifier FB 0.8 VREF PWM to Switch x2 ISLOPE + + ICOMP Offset f(IDRAIN) COMP GND 11.5 kW RCOMP CCOMP UDG-09128 Figure 14. Feedback Loop Equivalent Circuit A more conventional small-signal equivalent block diagram is shown in Figure 15. Here, the full closed-loop signal path is shown. Because the TPS5429x contains internal slope compensation, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. V IN VREF VC + _ VOUT + Modulator _ Filter Current Feedback Network Compensation Network Figure 15. Small Signal Equivalent Block Diagram To determine the components necessary for compensating the feedback loop, the controller frequency response characteristics must be understood and the desired crossover frequency selected. The best results are obtained if 10% of the switching frequency is used as this closed-loop crossover frequency. In some cases, up to 20% of the switching frequency is also possible. 14 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 Feature Description (continued) With the output filter components selected, the next step is to calculate the DC gain of the modulator. For TPS5429x, use Equation 5. fSW FM TPS5429x = æ æ (V - VOUT ) ö ö K ´t ç 19.7 ´ e( ON ) + 95 ´ 10 -6 ´ ç IN ÷÷ ÷ ç ç ÷ L è øø è where • • • K = 5.6 ×105 for TPS54290 K = 1.5 × 106 for TPS54291 K = 3.6 × 106 for TPS54292 (5) The overall DC gain of the converter control-to-output transfer function is approximated by Equation 6. fC = VIN ´ FM ´ 2 ´ 10 -4 ( æ æ V ´ FM ´ 95 ´ 10 -6 ç ç IN ç1 + ç 2 ´ RLOAD ç ç è è )ö÷ ö÷ ÷÷ ÷÷ øø (6) The next step is to find the desired gain of the error amplifier at the desired crossover frequency. Assuming a single-pole roll-off, use Equation 6 to evaluate Equation 7 at the desired crossover frequency. æ ö fC ÷ KEA = -20 ´ log ç ç 1 + 2 ´ p ´ fCO ´ (2 ´ RLOAD )´ COUT ÷ è ø ( ) where • ƒCO is the desired crossover frequency (7) TPS54290 VOUT1 ZUPPER C1 (Optional) C2 (Optional) R1 R2 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 4 PGND1 5 EN1 BP 12 6 EN2 GND 11 7 FB1 FB2 10 8 COMP1 SW2 14 PGND2 13 COMP2 9 RCOMP CCOMP ZLOWER UDG-09129 Copyright © 2016, Texas Instruments Incorporated Figure 16. Loop Compensation Network Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 15 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the voltage setting divider (see Equation 8). If duty cycles are less than 50%, this capacitor may be omitted. L ´ COUT C1 = R1 (8) If a high-ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability (see Equation 9). To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor. The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If low-ESR capacitors are used, this capacitor may be omitted. ESR ´ (R1 + R2 ) C2 = COUT ´ (R1´ R2 ) (9) Next, calculate the value of the error amplifier gain setting resistor and capacitor using Equation 10 and Equation 11. RCOMP = CCOMP = 10 KEA 20 ´ (ZLOWER + ZUPPER ) gM ´ ZLOWER (10) 1 2 ´ p ´ fPOLE ´ RCOMP where fPOLE = • 1 2 ´ p ´ (2 ´ RLOAD )´ COUT (11) NOTE When the filter and compensation component values have been established, laboratory measurements of the physical design must be performed to confirm converter stability. 8.3.10 Bootstrap for N-Channel MOSFET A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to maximum (that is, 90% for TPS54291) allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn on, the energy used to drive the MOSFET gate is derived from the voltage on this capacitor. Because this is a charge transfer circuit, take care in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge requirement of the MOSFET being used. Typically a ceramic capacitor with a value from 22 nF to 68 nF is selected for the bootstrap capacitor. 8.3.11 Output Overload Protection In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (which follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled. This ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the other is not loaded. The converter enters a hiccup mode timeout before attempting to restart. If an overcurrent condition exists during soft start, pulse-by-pulse current limiting reduces the pulse width of the affected output’s PWM. In addition, if an overcurrent pulse is detected, six clock cycles are skipped before a next PWM pulse is enabled, effectively dividing the PWM frequency by six and preventing excessive current build up in the inductor. At the end of the soft-start time, a UV fault is declared and the operation is the same as described above. 16 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 Feature Description (continued) The overcurrent threshold for Output1 and Output2 are set nominally 2.2 A and 3.8 A, respectively. NOTE Design hint: The OCP Threshold refers to the peak current in the internal switch. Be sure to add the 1/2 of the peak inductor ripple current to the DC load current in determining how close the actual operating point is to the OCP Threshold. 8.3.12 Operating Near Maximum Duty Cycle If the TPS5429x is operated at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load current transient) then there is a possibility that the output voltage falls from regulation and trip the output UV comparator. If this must occur, the TPS5429x protection circuitry declares a fault and enters hiccup mode. NOTE Design hint: Ensure that under ALL conditions of line and load regulation that there is sufficient duty cycle to maintain output voltage regulation. 8.3.13 Dual-Supply Operation It is possible to operate a TPS5429x from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This is to ensure the internal regulator and the control circuitry is in operation before PVDD1 supplies energy to the output. In addition, Output1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to support Output1 in regulation (see Operating Near Maximum Duty Cycle). The preferred sequence of events follows: 1. PVDD2 rises above the input UVLO voltage 2. PVDD1 rises with Output1 disabled until PVDD1 rises above level to support Output1 regulation With the two conditions above satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1. NOTE Design hint: An R-C delay on EN1 may be used to delay the start-up of Output1 for a long enough period of time to ensure PVDD1 can support Output1 load. 8.3.14 Bypassing and Filtering As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible. • PVDD1 to GND: Use a 10-µF ceramic capacitor • PVDD2 to GND: Use a 10-µF ceramic capacitor • BP to GND: Use a 4.7-µF ceramic capacitor 8.4 Device Functional Modes 8.4.1 PWM Operation TPS5429X is a dual-channel synchronous buck converter. Normal operation occurs when VIN is above 4.5 V and the EN1 and EN2 pins pulled low to enable the device. 8.4.2 Standby Operation TPS5429X can be placed in standby when the EN1 and EN2 pins are set high, disabling the device. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 17 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information TPS5429X is a synchronous buck converter. It can convert an input voltage of 4.5 V to 18 V to two lower voltages. Channel 1 is rated for 1.5-A output, while Channel 2 is rated for 2.5-A output. 9.2 Typical Applications 9.2.1 TPS54291 Design Example The following example illustrates the design process and component selection for a 12-V to 5-V or 3.3-V dual non-synchronous buck regulator using the TPS54291 converter. Copyright © 2016, Texas Instruments Incorporated Figure 17. TPS54291 Design Example 1 Schematic 9.2.1.1 Design Requirements A definition of symbols used can be found in Table 1. The efficiency, line regulation, and load regulation from printed-circuit boards built using this design are shown in Figure 19 and Figure 20. Table 1. Design Example Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8 12 14 V 12 20 mA 4.2 4.4 V INPUT CHARACTERISTICS VIN Input voltage IIN Input current VIN = nom, IOUT = max No load input current VIN = nom, IOUT = 0 A Input UVLO IOUT = min to max VIN(UVLO) 18 Submit Documentation Feedback A 4 Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 Typical Applications (continued) Table 1. Design Example Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT CHARACTERISTICS VOUT1 Output voltage 1 VIN = nom, IOUT = nom 3.2 3.3 3.4 V VOUT2 Output voltage 2 VIN = nom, IOUT = nom 1.15 1.2 1.25 V Line regulation VIN = min to max 1% Load regulation IOUT = min to max 1% VOUT1(ripple) Output1 voltage ripple VIN = nom, IOUT1 = max 50 mVPP VOUT2(ripple) Output2 voltage ripple VIN = nom, IOUT2 = max 24 mVPP IOUT1 Output current 1 VIN = min to max 1.5 A IOUT2 Output current 2 VIN = min to max 2.5 A IOCP1 Output overcurrent Channel 1 VIN = nom, VOUT = (VOUT1 – 5%) 1.8 2.2 2.6 A IOCP2 Output overcurrent Channel 2 VIN = nom, VOUT = (VOUT2 – 5%) 3.2 3.8 4.6 A 0 0 TRANSIENT RESPONSE ΔVOUT Change from load transient ΔIOUT = 1 A at 3 µA/s Settling time to 1% of VOUT 200 mV 1 ms SYSTEMS CHARACTERISTICS fSW Switching frequency ηPEAK Peak efficiency VIN = nom 500 90% η Full load efficiency VIN = nom, IOUT = max 80% TOP Operating temperature VIN = min to max, IOUT = min to max 0 600 700 kHz 60 °C 25 9.2.1.2 Detailed Design Procedure The list of materials for this application is shown below in Table 2. Table 2. Design Example List of Materials REFERENCE DESIGNATOR QTY VALUE DESCRIPTION SIZE PART NUMBER MFR C12 1 4.7 µF Capacitor, Ceramic, 10 V, X5R, 20% 0805 Std Std C2, C14 2 22 µF Capacitor, Ceramic, 6.3 V, X5R, 20% 1206 C3216X5R0J226M TDK C3, C13 2 470 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C4, C11 2 0.047 µF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C5, C10 2 10 µF Capacitor, Ceramic, 25 V, X5R, 20% 1210 C3225X5R1E106M TDK C6 2 1.8 nF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C7 1 15 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C8 1 47 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C9 1 1.2 nF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std MSS1048-822L Coilcraft L1 1 8.2 µH Inductor, SMT, 4.38 A, 20 mΩ 0.402 × 0.394 inch L2 1 3.3 µH Inductor, SMT, 5.04 A, 10 mΩ 0.402 × 0.394 inch MSS1048-332L Coilcraft R10 1 40.2 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R2, R11 2 10 Ω Resistor, Chip, 1/16W, 5% 0603 Std Std R3, R12 2 20.5 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R4 1 6.49 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R6 1 7.87 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R7 1 4.64 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std U1 1 2.5 A/1.5 A, 600 Hz Dual Output Fully Synchronous Buck Converter w/Integrated FET CSP TPS54291PWP TI Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 19 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 9.2.1.2.1 Duty Cycle Estimation The duty cycle of the main switching FET is estimated by Equation 12 and Equation 13. DMAX1 » DMIN1 » VOUT VOUT 3.3 1.2 = = 0.413 ¾¾® DMAX2 » = = 0.15 VIN(min ) 8.0 VIN(min ) 8.0 (12) VOUT VOUT 3.3 1.2 = = 0.236 ¾¾® DMIN2 » = = 0.086 VIN(max ) 14 VIN(max ) 14 (13) 9.2.1.2.2 Inductor Selection The peak-to-peak ripple must be limited to between 20% and 30% of the maximum output current (see Equation 14 and Equation 15). ILrip1(max ) = 0.30 ´ IOUT(max ) = 0.3 ´ 1.5 A = 0.450 A (14) ILrip2(max ) = 0.30 ´ IOUT(max ) = 0.3 ´ 2.5 A = 0.750 A (15) The minimum inductor size can be estimated by Equation 16 and Equation 17. VIN(max ) - VOUT 1 14 - 3.3 1 ´ DMIN ´ = ´ 0.236 ´ = 9.35 mH LMIN1 » ILRIP(max ) 0.45 A 600kHz fSW L MIN2 » VIN(max ) - VOUT ILRIP (max ) ´ DMIN ´ (16) 1 14 - 1.2 1 = ´ 0.086 ´ = 2.45 mH 0.75 A 600 kHz fSW (17) The standard inductor values of 8.2 µH and 3.3 µH are selected for Channel 1 and Channel 2, respectively. The actual ripple currents are estimated by Equation 18 and Equation 19. VIN(max ) - VOUT 1 14 - 3.3 1 ´ DMIN ´ = ´ 0.236 ´ = 0.513 A IRIPPLE1 » fSW L1 8.2 mH 600kHz (18) VIN(max ) - VOUT 1 14 - 1.2 1 ´ DMIN ´ = ´ 0.086 ´ = 0.556A IRIPPLE2 » fSW L2 3.3 mH 600kHz (19) The RMS current through the inductor is approximated by Equation 20 and Equation 21. IL(rms ) = IL(avg)2 + IL(rms ) = IL(avg)2 + 2 1 I 12 RIPPLE 2 1 I 12 RIPPLE » IOUT(max )2 + » IOUT(max )2 + 2 1 I 12 RIPPLE 2 1 I 12 RIPPLE = = (1.5 )2 + 112 (0.513 )2 A = 1.51A 2 (2.5 ) + 1 12 2 (0.556 ) A = 2.51A (20) (21) A DC current with 30% peak-to-peak ripple has an RMS current approximately 0.4% above the average current. The peak inductor current is estimated by Equation 22 and Equation 23. IL(peak ) » IOUT(max ) + 12 IRIPPLE = 1.5 A + 12 0.513A = 1.76 A 1 (22) 1 IL(peak ) » IOUT(max ) + 2 IRIPPLE = 2.5 A + 2 0.556A = 2.78 A (23) A 8.2-µH inductor with a minimum RMS current rating of 1.51 A and minimum saturation current rating of 3.7 A must be selected. A Coilcraft MSS1048-822ML 8.2-µH, 4.38-A inductor is chosen for Channel 1 and a Coilcraft MSS1048-332 3.3-µH inductor is chosen for Channel 2. 20 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 9.2.1.2.3 Output Capacitor Selection Output capacitors are selected to support load transients and output ripple current. The minimum output capacitance to meet the transient specification is given by Equation 24 and Equation 25. COUT1(min ) = ITRAN(max )2 ´ L (VOUT )´ VOVER = 2 C OUT2(min ) = ITRAN(max ) ´ L (VOUT )´ VOVER = 1A 2 ´ 8.2 mH = 12.4 mF 3.3 V ´ 0.2 V (24) 1A 2 ´ 3.3 mH = 13.7 mF 1.2 V ´ 0.2 V (25) The maximum ESR to meet the ripple specification is given by Equation 26 and Equation 27. æ ö IRIPPLE æ ö 0.513 A VRIPPLE(total) - ç ÷ 0.050 V - ç ÷ f ´ ´ 8 C ´ m ´ 8 12.4 F 600kHz OUT SW ø è è ø = 0.081W = ESRMAX = IRIPPLE 0.513 A (26) æ ö IRIPPLE æ ö 0.556 A VRIPPLE(total) - ç ÷ 0.024 V - ç ÷ f ´ ´ 8 C OUT SW ø è è 8 ´ 13.7 mF ´ 600kHz ø = 0.028 W = ESRMAX = IRIPPLE 0.556 A (27) A single 22-µF ceramic capacitor with approximately 2.5 mΩ of ESR is selected to provide sufficient margin for capacitance loss due to DC voltage bias. 9.2.1.2.4 Input Capacitor Selection A minimum 10-µF ceramic input capacitor on each PVDD pin is recommended. The ceramic capacitor must handle the RMS ripple current in the input capacitor. The RMS current in the input capacitors is estimated by Equation 28 and Equation 29. IRMS(CIN1) = IOUT1 ´ D1 ´ (1 - D1 ) = 1.5 A ´ 0.413 ´ (1 - 0.413 ) = 0.74 A (28) IRMS(CIN2 ) = IOUT1 ´ D2 ´ (1 - D2 ) = 2.5 A ´ 0.15 ´ (1 - 0.15 ) = 0.89 A (29) One 1210 10-µF, 25-V, X5R, ceramic capacitor with 2-mΩ ESR and a 2-A RMS current rating are selected for each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the capacitors have sufficient capacitance at the working voltage. 9.2.1.2.5 Feedback The primary feedback divider resistor (RFB) from VOUT to FB must be selected between 10-kΩ and 100-kΩ to maintain a balance between power dissipation and noise sensitivity. For a 3.3-V and 5-V output, 20.5 kΩ is selected and the lower resistor is given by Equation 30. V ´ RFB RBIAS = FB VOUT - VFB (30) For RFB = 20.5 kΩ and VFB = 0.8 V, RBIAS = 6.56 kΩ and 41.0 kΩ (6.49 kΩ and 40.2 kΩ selected) for 3.3 V and 1.2 V, respectively. It is common to select the next lower available resistor value for the bias resistor. This biases the nominal output voltage slightly higher, allowing additional tolerance for load regulation. 9.2.1.2.6 Compensation Components The TPS54291 controller uses a transconductance error amplifier, which is compensated with a series capacitor and resistor to ground plus a high-frequency capacitor to reduce the gain at high frequency. To select the component, Equation 31 to Equation 33 define the control loop and power stage gain and transfer function. FMTPS5429x = fSW é (K´tON ) + 95 ´ 10-6 ´ æ VIN - VOUT ê19.7 ´ e ç L è ë öù ÷ú øû = 600kHz = 3762 6 é 1.5 10 393ns ´ ´ ( ) -6 æ 14 - 3.3 ö ù + 95 ´ 10 ´ ç ê19.7 ´ e ÷ú è 8.2 mH ø ûú ëê Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 21 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com where • • • K = 5.6 × 105 for TPS54290 K = 1.5 × 106 for TPS54291 K = 3.6 × 106 for TPS54292 (31) The overall DC gain of the converter control-to-output transfer function is approximated by Equation 32. fC = VIN ´ FM ´ 2 ´ 10-4 é æ V ´ FM ´ 95 ´ 10-6 ê1 + ç IN ç 2 ´ RLOAD ëê è öù ÷ú ÷ú øû = 14 V ´ 3762 ´ 2 ´ 10-4 é æ 14 V ´ 3762 ´ 95 ´ 10-6 ê1 + ç 4.4 W êë çè öù ÷ú ÷ú øû = 4.293 (32) With the power stage DC gain, it is possible to estimate the required mid-band gain to program a desired crossover frequency. æ ö fC æ ö 3.22 KEA = -20 ´ log ç ÷ = -20 ´ log ç ÷ = 11.83 dB ç 1 + 2 ´ p ´ fCO ´ (2 ´ RLOAD )´ COUT ÷ 1 2 30kHz 4.4 22 F + ´ p ´ ´ W ´ m è ø è ø (33) 9.2.1.2.7 Compensation Gain Setting Resistor RCOMP programs the mid-band error amplifier gain to set the desired crossover frequency in Equation 34. RCOMP = 10 KEA 20 ´ (ZLOWER + ZUPPER ) 10 = gM ´ ZLOWER 11.83dB 20 ´ (6.49kW + 20.5kW) = 50.42kW » 53.6kW 325 mS ´ 6.49kW (34) 9.2.1.2.8 Compensation Integrator Capacitor An integrator capacitor provides maximum DC gain for the best possible DC regulation while programming the compensation zero to match the natural pole of the output filter (see Equation 35). CCOMP is selected by Equation 36. 1 1 fPOLE = = = 1.644kHz 2 ´ p ´ RLOAD ´ COUT 2 ´ p ´ 4.4 W ´ 22 mF (35) CCOMP = 1 = 2 ´ p ´ fPOLE ´ RCOMP 1 = 1.80nF 2 ´ p ´ 1.644kHz ´ 53.6kW (36) 9.2.1.2.9 Bootstrap Capacitor To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 47-nF boot strap capacitor is recommended. 9.2.1.2.10 Power Dissipation The power dissipation in the TPS54291 is made from FET conduction losses, switching losses and regulator losses. Conduction losses are estimated by Equation 37 and Equation 38. ) ( 2 ö = 150mW ´ 0.413 + 100mW ´ 0.587 ´ 1.51 2 = 0.275 W PCON1 = RDS(on )HS ´ D1 + RDS(on )LS ´ (1 - D1 ) ´ æç I ( ) ( ) ÷ è SW 1(RMS ) ø (37) ) ( 2 ö = 105mW ´ 0.15 + 75mW ´ 0.85 ´ 2.51 2 = 0.501W PCON2 = RDS(on )HS ´ D1 + RDS(on )LS ´ (1 - D1 ) ´ æç I ( ) ( ) ÷ è SW 1(RMS ) ø (38) The switching losses are estimated by Equation 39 and Equation 40. PSW1 » 22 VIN(max )2 ´ (COSS(HS) + COSS(LS) ) ´ fSW 2 Submit Documentation Feedback = 142 ´ (140pF + 200pF) ´ 600kHz = 20mW 2 (39) Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com PSW 2 » SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 VIN(max )2 ´ (COSS(HS ) + COSS(LS ) ) ´ fSW 2 = 142 ´ (200pF + 280pF) ´ 600kHz = 28mW 2 (40) The regulator losses are estimated by Equation 41. ) ( PREG » IDD ´ VIN(max ) + IBP ´ VIN(max ) - VBP = 10mA ´ 14 V = 140mW (41) Total power dissipation in the device is the sum of conduction losses and switching losses for both channels plus regulator losses, which is estimated to be 1.01 W. 9.2.1.3 Application Curves 90 VIN = 8 V 85 h – Efficiency – % 80 VIN = 12 V 75 70 VIN = 14 V 65 60 55 VOUT = 1.2 V 50 0 0.5 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 Figure 19. Design Efficiency for 1.2-V Output Figure 18. TPS54291 Design Example Switching Waveforms 100 VIN = 8 V 95 90 h – Efficiency – % 85 VIN = 14 V 80 75 VIN = 12 V 70 65 60 55 VOUT = 3.3 V 50 0 0.3 0.6 0.9 1.2 ILOAD – Load Current – A 1.5 Figure 20. Design Efficiency for 3.3-V Output Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 23 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 9.2.2 TPS54290 Cascaded Design Example TPS5429x can be configured as cascaded operation as shown in Figure 21. The 12-V input supply is applied to PVDD2 and the Channel 2 output is tied to PVDD1. The Channel 2 output is 3.3 V and capable of supporting 1.5 A to the load while generating power for the 1.2-V input for Channel 1. + + 3.3V@1.5A 1.2V@1.5A + + Copyright © 2016, Texas Instruments Incorporated Figure 21. Cascading Operation 9.2.2.1 Application Curves For Figure 22: Channel 1 is a 12-V supply, Channel 2 is VOUT1 (1.2 V), and Channel 3 is VOUT2(3.3 V). For Figure 23: Channel 1 is Channel 1 SW node and Channel 2 is Channel 1 output ripple; Channel 3 is Channel 2 output ripple and Channel 2 is Channel 2 SW node. Figure 22. Start-Up Waveforms 24 Submit Documentation Feedback Figure 23. Output Ripple and SW Nodes Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 10 Power Supply Recommendations The device is designed to operate from an input-voltage supply range between 4.5 V and 18 V. This input supply must be well regulated. If the input supply is placed more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice. 11 Layout 11.1 Layout Guidelines • • • • • • • • • • The PowerPAD™ must be connected to the low-current ground with available surface copper to dissipate heat. TI recommends extending the ground land beyond the device package area between PVDD1 (pin 1) and PVDD2 (pin 16) and between COMP1 (pin 8) and COMP2( pin 9). Connect PGND1 and PGND2 to the PowerPAD™ through a 10-mil wide trace. Place the ceramic input capacitors near PVDD1 and PVDD2 and bypass to PGND1 and PGND2, respectively. Place the inductor near the SW1 or SW2 pin. Connect the output capacitor grounds to PGND1 or PGND2 with wide, tight loops. Use a wide ground connection from input capacitor PGND1 or PGND2 as close to power path as possible. TI recommends that they be placed directly underneath. Place the bootstrap capacitor near the BOOT pin to minimize gate drive loop. Place the feedback and compensation components far from switch node and input capacitor ground connection. Place the snubber components from SW1 or SW2 to PGND1 or PGND2 close to the device, minimizing the loop area. Place the BP bypass capacitor very close to device and bypass to PowerPAD™. Place output ceramic capacitor close to inductor output terminal and between inductor and electrolytic capacitors if used. 11.1.1 PowerPAD™ Package The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™ derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD™ package. Thermal vias connect this area to internal or external copper planes and must have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is required to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material must be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package (see Related Documentation). Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 25 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 11.2 Layout Examples Figure 24. Top Layer Figure 25. Bottom Layer 26 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 11.3 Overtemperature Protection and Junction Temperature Rise The overtemperature thermal protection limits the maximum power to be dissipated at a given operating ambient temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is limited by the maximum allowable junction operating temperature. The device junction temperature is a function of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature must reach the thermal shutdown level, the TPS5429x shuts off both PWMs and remain in this state until the die temperature drops below 125°C, at which time the device restarts. The first step in determining the device junction temperature is to calculate the power dissipation. The power dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by each MOSFET is composed of conduction losses and switching losses. The total conduction loss in the high-side and low-side MOSFETs for each channel is given by Equation 42. æ DI 2 ö PD(cond) = RDS(on )HS ´ D + RDS(on)LS ´ (1 - D ) ´ ç IO2 + O ÷ ç 12 ÷ø è ) ( where • • IO is the DC output current, ΔIO is the peak-to-peak ripple current in the inductor (42) Notice the impact of operating duty cycle on the result. The switching loss for each channel is approximated by Equation 43. PD(SW ) = VIN2 ´ C OSS (HS ) + C OSS (LS ) ´ fS ( ) 2 where • • • COSS(HS) is the output capacitance of the high-side MOSFET COSS(LS) is the output capacitance of the low-side MOSFET ƒS is the switching frequency (43) The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal regulator (see Equation 44). PD = PD(cond)output1 + PD(SW )output1 + PD(cond)output2 + PD(SW )output2 + VIN ´ Iq (44) The temperature rise of the device junction is dependent on the thermal impedance from junction to the mounting pad, plus the thermal impedance from the thermal pad to ambient. The thermal impedance from the thermal pad to ambient is dependent on the PCB layout (PowerPAD™ interface to the PCB, the exposed pad area) and airflow (if any; see Related Documentation for more information). The operating junction temperature is shown in Equation 45. ( TJ = TA + PD ´ qTH(pkg) + qTH(pad-amb) ) where • θTH is the thermal impedance Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 (45) Submit Documentation Feedback 27 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 11.4 Power Derating The TPS5429x delivers full current at wide duty cycles at ambient temperatures up to 85°C if the thermal impedance from the thermal pad is sufficient to maintain the junction temperature below the thermal shutdown level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 26 illustrates the power derating for elevated ambient temperature under various air flow conditions. Note that these curves assume the PowerPAD™ is soldered to the recommended thermal pad. See Related Documentation for further information. 1.8 LFM = 250 1.6 PD – Power Dissipation – W LFM = 500 1.4 LFM = 0 1.2 LFM = 150 1.0 0.8 0.6 LFM 0 150 250 500 0.4 0.2 0 0 20 40 60 80 100 120 TA – Ambient Temperature – °C 140 Figure 26. Power Derating Curves 28 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation These references, including design software, design tools, and links to additional references, may be found at www.power.ti.com. • Under The Hood Of Low Voltage DC/DC Converters (SLUP206) • Understanding Buck Power Stages in Switchmode Power Supplies (SLVA057) • Designing Stable Control Loops (SLUP173) • Additional PowerPAD™ information may be found in: – PowerPAD™ Thermally Enhanced Package (SLMA002) – PowerPAD™ Made Easy (SLMA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS54290 Click here Click here Click here Click here Click here TPS54291 Click here Click here Click here Click here Click here TPS54292 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 29 TPS54290, TPS54291, TPS54292 SLUS973A – OCTOBER 2009 – REVISED NOVEMBER 2016 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPS54290 TPS54291 TPS54292 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54290PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 145 54290 TPS54290PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 145 54290 TPS54291PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 145 54291 TPS54291PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 145 54291 TPS54292PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 145 54292 TPS54292PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 145 54292 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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