TPS542951
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SLVSBI4B – JULY 2012 – REVISED OCTOBER 2013
2A/3A Dual Channel Synchronous Step-Down Switcher with Integrated FET
Check for Samples: TPS542951
FEATURES
APPLICATIONS
•
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1
2
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D-CAP2™ Control Mode
– Fast Transient Response
– No External Parts Required For Loop
Compensation
– Compatible with Ceramic Output
Capacitors
Wide Input Voltage Range : 4.5 V to 18 V
Output Voltage Range : 0.76V to 7.0V
Highly Efficient Integrated FETs Optimized for
Low Duty Cycle Applications
– 150 mΩ (High Side) and 100 mΩ (Low Side)
High Initial Reference Accuracy
Supports Constant 2 A CH1 and 3 A CH2 Load
Current
Low-Side rDS(on) Loss-Less Current Sensing
Adjustable Soft Start
Non-Sinking Pre-Biased Soft Start
700 kHz Switching Frequency
Cycle-by-Cycle Over-Current Limit Control
OCL/UVLO/TSD Protections
Hiccup Timer for Overload Protection
Adaptive Gate Drivers with Integrated Boost
PMOS Switch
OCP Constant Due To Thermally Compensated
rDS(on) with 4000ppm/℃
℃
16-Pin HTSSOP, 16-Pin VQFN
Auto-Skip Eco-mode™
for High Efficiency at
Light Load
Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles and Other
DESCRIPTION
The TPS542951 is a dual, adaptive on-time DCAP2™ mode synchronous buck converter. The
TPS542951 enables system designers to complete
the suite of various end equipment’s power bus
regulators with a cost effective, low component count,
and low standby current solution. The main control
loops of the TPS542951 use the D-CAP2™ mode
control which provides a very fast transient response
with no external compensation components. The
adaptive on-time control supports seamless transition
between PWM mode at higher load conditions and
Eco-mode™ operation at light loads. Eco-mode™
allows the TPS542951 to maintain high efficiency
during lighter load conditions. The TPS542951 is able
to adapt to both low equivalent series resistance
(ESR) output capacitors such as POSCAP or SPCAP, and ultra-low ESR, ceramic capacitors. The
device provides convenient and efficient operation
with input voltages from 4.5V to 18V.
The TPS542951 is available in a 4.4mm × 5.0mm 16
pin TSSOP (PWP) package, and 4mm x 4mm 16 pin
VQFN (RSA) package, and is specified for an
ambient temperature range from –40°C to 85°C.
Input Voltage
VO2 = 1.5 V (50
C11
VO1
L11
1
VIN1
2
VBST1
VIN2
16
3
C12
VBST2 15
C32
C31
SW1
L12
C22
C21
4
PGND
5
R11
VO2
SW2 14
PGND1
TPS542951
HTSSOP16
EN1
6
SS1
7
VFB1
PGND2 13
Iout (2 A/div)
PGND
EN2
12
SS2
11
VFB2
10
(PowerPAD)
SGND
R21
SGND
C4
8
GND
VREG5
R22
9
PGND
SGND
R12
SGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS542951
SLVSBI4B – JULY 2012 – REVISED OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
PACKAGE (2)
(3)
ORDERING PART NUMBER
PWP
TPS542951RSAR
RSA
(2)
(3)
OUTPUT SUPPLY
Tape-and-Reel
16
TPS542951PWP
–40℃ to 85℃
(1)
PINS
TPS542951PWPR
Tube
16
TPS542951RSAT
Tape-and-Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
All packaging options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VALUE
Input voltage range
Output voltage range
Electrostatic discharge
VIN1, VIN2, EN1, EN2
–0.3 to 20
VBST1, VBST2
–0.3 to 26
VBST1, VBST2 (10ns transient)
–0.3 to 28
VBST1–SW1 , VBST2–SW2
–0.3 to 6.5
VFB1, VFB2
–0.3 to 6.5
SW1, SW2
–2 to 20
SW1, SW2 (10ns transient)
–3 to 22
VREG5, SS1, SS2
–0.3 to 6.5
PGND1, PGND2
–0.3 to 0.3
Human Body Model (HBM)
2
V
V
kV
500
V
TA
Operating ambient temperature range
–40 to 85
°C
TSTG
Storage temperature range
–55 to 150
°C
TJ
Junction temperature range
–40 to 150
°C
(1)
(2)
Charged Device Model (CDM)
UNIT
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to IC GND terminal.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS542951
PWP (16) PINS
RSA (16) PINS
θJA
Junction-to-ambient thermal resistance
47.5
34.9
θJCtop
Junction-to-case (top) thermal resistance
27.1
40.0
θJB
Junction-to-board thermal resistance
20.8
11.8
ψJT
Junction-to-top characterization parameter
1.0
0.7
ψJB
Junction-to-board characterization parameter
20.6
11.8
θJCbot
Junction-to-case (bottom) thermal resistance
2.7
.3.3
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VALUES
Supply input voltage range
Input voltage range
VIN1, VIN2
MAX
UNIT
4.5
18
VBST1, VBST2
–0.1
24
VBST1, VBST2 (10ns transient)
–0.1
27
VBST1–SW1, VBST2–SW2
–0.1
5.7
VFB1, VFB2
–0.1
5.7
EN1, EN2
–0.1
18
SW1, SW2
–1.0
18
SW1, SW2 (10ns transient)
Output voltage range
MIN
V
–3
21
VREG5, SS1, SS2
–0.1
5.7
PGND1, PGND2
–0.1
0.1
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating Junction Temperature
–40
150
°C
ELECTRICAL CHARACTERISTICS (1)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
1300
2000
µA
80
150
µA
765
773
mV
115
ppm/℃
0.4
µA
SUPPLY CURRENT
IIN
VIN supply current
TA = 25°C, EN1 = EN2 = 5 V,
VFB1 = VFB2 = 0.8 V
IVINSDN
VIN shutdown current
TA = 25°C,
FEEDBACK VOLTAGE
VVFBTHLx
VFBx threshold voltage
TA = 25°C, CH1 = 3.3 V, CH2 = 1.5 V
TCVFBx
Temperature coefficient
On the basis of 25°C (2)
–115
758
IVFBx
VFBx Input Current
VFBx = 0.8 V, TA = 25°C
–0.4
0.2
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN1 < 18 V,
IVREG = 5 mA
5.5
V
IVREG5
Output current
VIN1 = 6 V, VREG5 = 4.0 V,
TA = 25°C (2)
75
mA
High side switch resistance
TA = 25℃, VBSTx-SWx = 5.5 V
150
mΩ
100
mΩ
MOSFETs
rDS(on)H
rDS(on)L
Low side switch resistance
TA = 25℃
(2)
(2)
ON-TIME TIMER CONTROL
TON1
SW1 On Time
SW1 = 12 V, VO1 = 1.2 V
165
ns
TON2
SW2 On Time
SW2 = 12 V, VO2 = 1.2 V
165
ns
TOFF1
SW1 Min off time
TA = 25℃, VFB1 = 0.7 V (2)
220
ns
SW2 Min off time
TA = 25℃, VFB2 = 0.7 V
(2)
220
ns
SSx charge current
VSSx = 0.5 V, TA = 25℃,
TOFF2
SOFT START
ISSC
TCISSC
ISSC temperature coefficient
ISSD
SSx discharge current
(1)
(2)
On the basis of 25°C, PWP
–8.4
(2)
On the basis of 25°C, RSA (2)
VSSx = 0.5 V
–8.0
–7.6
µA
–4
3
nA/°C
–4
5
nA/°C
10
mA
3
7
x means either 1 or 2, that is, VFBx means VFB1 or VFB2.
Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS(1) (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
VUVREG5
VREG5 UVLO threshold
VREG5 rising
3.83
Hysteresis
V
0.6
LOGIC THRESHOLDs
VENxH
ENx H-level threshold voltage
VENxL
ENx L-level threshold voltage
RENx_IN
ENx input resistance
2.0
V
0.4
V
ENx = 12V
225
450
900
kΩ
CURRENT LIMITs
IOCL1
CH1 Current limit
LOUT1 = 2.2 µH (3)
2.7
3.9
4.5
A
IOCL2
CH1 Current limit
LOUT2 = 1.5 µH (3)
3.5
4.7
5.4
A
63%
68%
73%
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP)
VUVP
Output UVP trip threshold
TUVPDEL
Output UVP delay time
TUVPEN
Output UVP enable delay
measured on VFBx
1.5
UVP enable delay / softstart time
x 1.4
x 1.7
ms
x 2.0
THERMAL SHUTDOWN
TSD
(3)
4
Thermal shutdown threshold
Shutdown temperature (3)
Hysteresis (3)
155
25
°C
Specified by design. Not production tested.
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VBST1
3
SW1
4
PGND1
TPS542951
5
EN1
HTSSOP16
6
SS1
7
VFB1
8
GND
16
VBST2
15
SW 2
14
PGND 2
13
EN2
12
SS2
11
VFB2
10
VREG5
9
VBST2
1
VIN2
2
EN2
SS2
16
15
14
13
12
VFB2
11
VREG5
PowerPAD
VIN1
3
10
GND
VBST1
4
9
VFB1
SW1
5
(PowerPAD)
6
7
8
SS1
2
VIN2
EN1
VIN1
PGND1
1
PGND2
HTSSOP PACKAGE
(TOP VIEW)
SW2
DEVICE INFORMATION
PIN FUNCTIONS (1)
PIN
NAME
NUMBER
I/O
PWP
RSA
VIN1
1
3
VIN2
16
2
VBST1
2
4
VBST2
15
1
SW1
3
5
SW2
14
16
PGND1
4
6
PGND2
13
15
EN1
5
7
EN2
12
14
PG1
6
—
PG2
11
—
SS1
—
8
SS2
—
13
DESCRIPTION
I
Power inputs and connects to both high side NFET drains.
Supply Input for 5.5V linear regulator.
I
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor
between VBSTx and SWx pins. An internal diode is connected between VREG5 and
VBSTx
I/O
Switch node connections for both the high-side NFETs and low–side NFETs. Input of
current comparator.
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
I
Enable. Pull High to enable according converter.
O
Open drain power good outputs. Low indicates the corresponding output voltage is out of
regulation.
O
Soft-Start Programming Pin. Connect Capacitor from SSx pin to GND to program SoftStart time.
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB1
7
9
VFB2
10
12
GND
8
10
I/O
Signal GND. Connect sensitive VFBx returns to GND at a single point.
VREG5
9
11
O
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at
least 1.0 µF. VREG5 is active when VIN1 is high.
Back
side
Back
side
I/O
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must
be connected to GND.
PowerPAD™
(1)
x means either 1 or 2, that is, VFBx means VFB1 or VFB2.
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FUNCTIONAL BLOCK DIAGRAM
VIN1
VIN1
- 32
VBST1
UV1
UV
0.1uF
SW1
Ref1
SS1
VO1
PGND1
Err
Comp
PGND1
VFB1
Ref_OCL
PGND1
SW1
OCP1
EN1
EN2
EN
Logic
SW1
ZC1
EN Logic
VIN1
VREG5
GND
CH1 Min- off timer
5VREG
1.0 uF
CH2 Min- off timer
SS1
SS1
SS2
SoftStart
UV1
UV2
SS2
CSS1
UVLO
TSD
CSS2
-32
UV
Ref1
Ref2
REF
UVLO
Protection
Logic
VIN2
VIN2
VBST2
UV2
0.1uF
VO2
SW2
Ref2
SS2
PGND2
Err
Comp
PGND2
VFB2
Ref_OCL
PGND2
SW2
OCP2
6
SW2
ZC2
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OVERVIEW
The TPS542951 is a 2A/3A dual synchronous step-down (buck) converter with two integrated N-channel
MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™
control reduces the required output capacitance to meet a specific level of performance. Proprietary internal
circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS542951 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal
timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a
pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset
and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.
An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR
induced output ripple from D-CAP™ control.
PWM Frequency and Adaptive On-Time Control
TPS542951 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS542951 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set
the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOx/VINx, the frequency is constant.
Auto-Skip Eco-mode™ Control
The TPS542951 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where
its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with
smaller load current to the nominal output voltage. The transition point to the light load operation IOx(LL) current
can be estimated with Equation 1 with 700-kHz used as fSW.
(VINx - VOx ) ´ VOx
1
´
IOx(LL) =
2 ´ L1x ´ fSW
VINx
(1)
Soft Start and Pre-Biased Soft Start
The soft start time is adjustable. When the ENx pin becomes high, 8-µA current begins charging the capacitor
which is connected from the SSx pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFBx voltage is 0.765-V and SSx pin source current
is 8-µA.
C4x(nF) ´ VFBx(V)
C4x(nF) ´ 0.765 V
TSS (ms) =
=
ISS (m A)
8 mA
(2)
The TPS542951 contains a unique circuit to prevent current from being pulled from the output during startup if
the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft
start becomes greater than internal feedback voltage VFBx), the controller slowly activates synchronous
rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that ontime on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the
converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage
(VOx) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
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Current Sensing and Over-Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit.
The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx
pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the
measurement accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx,
VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOx. If the sensed voltage on the
low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
Important considerations for this type of over-current protection: The load current is one half of the peak-to-peak
inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage
tends to fall as the demanded load current may be higher than the current available from the converter. When
the over current condition is removed, the output voltage returns to the regulated value. This protection is nonlatching.
Undervoltage Protection and Hiccup Mode
Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.
If the OCL comparator circuit detects an over-current event the output voltage falls. When the feedback voltage
falls below 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After counting UVP delay time, the TPS542951 shuts off the power supply for a given
time (7x UVP Enable Delay Time) and then tries to re-start the power supply. If the over-load condition has been
removed, the power supply starts and operates normally; otherwise, the TPS542951 detects another over-current
event and shuts off the power supply again, repeating the previous cycle. Excess heat due to overload lasts for
only a short duration in the hiccup cycle, therefore the junction temperature of the power device is much lower.
UVLO Protection
Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than the UVLO threshold, the TPS542951 shuts down. As soon as the voltage increases above the UVLO
threshold, the converter starts again.
Thermal Shutdown
TPS542951 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the
device shuts down. When the temperature falls below the threshold, the IC starts again.
When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is
lower than 155°C. As long as VIN1 rises, TJ must be kept below 110°C.
8
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TYPICAL CHARACTERISTICS
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VINx = 12 V, TA = 25°C (unless otherwise noted).
EN1, EN2 = ON
1600
Icc − Supply Current (µA)
Supply Current−Shutdown Current (µA)
1800
1400
1200
1000
800
600
400
200
VIN1, VIN2 = 12 V
0
−50
0
50
100
Junction Temperature (°C)
150
120
100
80
60
40
20
VIN1, VIN2 = 12 V
0
−50
50
3.40
45
3.38
40
3.36
35
30
25
20
15
10
50
100
Junction Temperature (°C)
0
5
10
EN Input Voltage (V)
15
3.32
3.30
3.28
3.26
VIN = 6 V
VIN = 12 V
VIN = 18 V
3.20
0.0
20
0.2
0.5
0.8
1.0
1.2
Output Current (A)
G003
1.5
1.8
2.0
G004
Figure 4. VO1 = 3.3V Output Voltage vs Output Current
1.55
3.40
VOUT = 1.5 V
3.38
3.36
Output Voltage (V)
1.53
1.52
1.51
1.50
1.49
1.48
VIN = 5 V
VIN = 12 V
VIN = 18 V
1.47
1.46
1.45
0.0
G002
3.34
3.22
Figure 3. EN Current vs EN Voltage (VEN = 12V)
1.54
150
VOUT = 3.3 V
3.24
EN1
EN2
5
0
0
Figure 2. Input Shutdown Current vs Junction Temperature
Output Voltage (V)
EN Input Current (µA)
EN1. EN2 = OFF
140
G001
Figure 1. Input Current vs Junction Temperature
Output Voltage (V)
160
0.5
1.0
1.5
2.0
Output Current (A)
2.5
3.34
3.32
3.30
3.28
3.26
3.24
IOUT = 10 mA
IOUT = 1 A
3.22
3.0
3.20
0
G005
Figure 5. VO2 = 1.5V Output Voltage vs Output Current
2
4
6
8
10
12
Input Voltage (V)
14
16
18
20
G006
Figure 6. VO1 = 3.3V Output Voltage vs Input Voltage
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TYPICAL CHARACTERISTICS (continued)
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VINx = 12 V, TA = 25°C (unless otherwise noted).
1.55
1.54
Vout(50mV/div)
Output Voltage (V)
1.53
1.52
1.51
1.50
1.49
Iout(1A/div)
1.48
1.47
IOUT = 10 mA
IOUT = 1 A
1.46
1.45
0
2
4
6
8
10
12
Input Voltage (V)
14
16
18
20
100 ms/div
G007
Figure 7. VO2 = 1.5V Output Voltage vs Input Voltage
Figure 8. VO1 = 3.3V, 0A to 4A Load Transient Response
EN1(10V/div)
Vout(50mV/div)
Vout(1V/div)
Iout(2A/div)
SS1(2V/div)
400 ms/div
100 ms/div
Figure 9. VO2 = 1.5V, 0A to 2A Load Transient Response
Figure 10. VO1 = 3.3V, SoftStart
100
EN2(10V/div)
90
Efficiency (%)
80
Vout2(0.5V/div)
70
60
50
40
30
VIN = 6 V
VIN = 12 V
VIN = 18 V
20
SS2(2V/div)
10
0
0.00
400 ms/div
Figure 11. VO2 = 1.5V, SoftStart
10
0.25
0.50
0.75 1.00 1.25
Output Current (A)
1.50
1.75
2.00
G012
Figure 12. VO1 = 3.3V, Efficiency vs Output Current
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TYPICAL CHARACTERISTICS (continued)
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VINx = 12 V, TA = 25°C (unless otherwise noted).
60
50
40
30
50
40
30
VIN = 6 V
VIN = 12 V
VIN = 18 V
20
10
0
0.001
0.01
0.1
Output Current (A)
1
10
0
0.0
10
750
Switching Frequency (kHz)
90
80
70
60
50
40
30
VIN = 5 V
VIN = 12 V
VIN = 18 V
20
10
0.1
Output Current (A)
1
550
500
450
IOUT1 = 1 A
400
10
0
Switching Frequency (kHz)
Switching Frequency (kHz)
10
Input Voltage (V)
700
650
600
550
500
450
15
20
20
G016
VIN1, VIN2 = 12 V
700
600
500
400
300
200
100
VOUT2 = 1.5 V
15
Figure 16. VO1 = 3.3V, SW-frequency vs
Input Voltage (PWP)
800
10
Input Voltage (V)
VOUT1 = 3.3 V
5
G015
900
5
G014
600
750
0
3.0
650
800
IOUT2 = 1 A
2.5
700
Figure 15. VO2 = 1.5V, Light Load Efficiency vs Output
Current
400
1.0
1.5
2.0
Output Current (A)
Figure 14. VO2 = 1.5V, Efficiency vs Output Current
800
0.01
0.5
G013
100
0
0.001
VIN = 5 V
VIN = 12 V
VIN = 18 V
20
Figure 13. VO1 = 3.3V, Light Load Efficiency vs Output
Current
Efficiency (%)
60
0
0.01
G017
Figure 17. VO2 = 1.5V, SW-frequency vs
Input Voltage (PWP)
VOUT1 = 3.3 V
0.1
1
Output Current (A)
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G018
Figure 18. VO1 = 3.3V, SW-frequency vs
Output Current (PWP)
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TYPICAL CHARACTERISTICS (continued)
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VINx = 12 V, TA = 25°C (unless otherwise noted).
900
Switching Frequency (kHz)
800
VIN1, VIN2 = 12 V
VO1(10mV/div)
VO1 = 3.3 V
IO1 = 2A
700
600
500
400
SW1(5V/div)
300
200
100
VOUT2 = 1.5 V
0
0.01
0.1
1
Output Current (A)
10
400 nsec/div)
G019
Figure 19. VO2 = 1.5V, SW-frequency vs
Output Current (PWP)
VO2(10mV/div)
VO2 = 1.5 V
Figure 20. VO1 = 3.3V, VO1 Ripple Voltage (IO1= 2 A)
VIN1(50mV/div)
IO2 = 3A
SW2(5V/div)
VO1 = 3.3 V
IO1 = 2 A
SW1(5V/div)
400 nsec/div)
400 nsec/div)
Figure 21. VO2 = 1.5V, Ripple Voltage (IO2 = 3 A)
VIN2(50mV/div)
Figure 22. VIN1 Input Voltage Ripple (IO1= 2 A)
VO2 = 1.5 V
IO2 = 3 A
SW2(5V/div)
400 nsec/div)
Figure 23. VIN2 Input Voltage Ripple (IO2= 3 A)
12
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DESIGN GUIDE
Step By Step Design Procedure
To
•
•
•
begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated
switching frequency of 700 kHz is used.
VINx
12V ± 10%
C11
10 mF
VO1
3.3 V
L11
2.2 mH
C31
0.1 mF
C21
22 mF
x2
1
VIN1
2
VBST1
3
4
PGND1
R11
73.2 kW
5
EN1
16
VBST2 15
L12
1.5 mH
C32
0.1 mF
SW1
PGND
C41
0.01 mF
VIN2
C12
10 mF
SW2 14
TPS542951
HTSSOP16
VO2
1.5 V
C22
22 mF
x2
PGND2 13
PGND
EN2
12
SS2
11
6
SS1
7
VFB1
VFB2
10
8
GND
VREG5
9
C42
0.01 mF
SGND
R12
21.5 kW
SGND
R21
22.1 kW
C4 1uF
R22
22.1 kW
PGND
SGND
SGND
Figure 24. Schematic Diagram for the Design Example
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOx.
To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values
will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.
æ R1x ö
VOx = 0.765 V ´ ç 1+
÷
è R2x ø
(3)
Output Filter Selection
The output filter used with the TPS542951 is an LC circuit. This LC filter has double pole at:
1
FP =
2p L1x ´ C1x
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS542951. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.
Table 1. Recommended Component Values
Output Voltage (V)
R1x (kΩ)
R2x (kΩ)
L1x (µH)
C2x (µF)
1
6.81
22.1
Cffx (pF)
1.5 - 2.2
20 - 68
1.05
8.25
22.1
1.5 - 2.2
20 - 68
1.2
12.7
22.1
1.5 - 2.2
20 - 68
1.5
21.5
22.1
1.5 - 2.2
20 - 68
1.8
30.1
22.1
5 - 22
2.2 - 3.3
20 - 68
2.5
49.9
22.1
5 - 22
2.2 - 3.3
20 - 68
3.3
73.2
22.1
5 - 22
2.2 - 3.3
20 - 68
5
124
22.1
5 - 22
4.7
20 - 68
6.5
165
22.1
5-22
4.7
20 - 68
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (Cffx) in parallel with R1x.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the
peak current of Equation 6 and the RMS current of Equation 7.
VINx(MAX) - VOx
VOx
´
ΔIL1x =
VINx(MAX)
L1x ´ fSW
(5)
IL1xpeak = IOx
ΔI
+ L1x
2
IL1x(RMS) =
IOx 2 +
(6)
1
DIL1x 2
12
(7)
For the above design example, the calculated peak current is 2.78 A and the calculated RMS current is 2.05 A
for VO1. The inductor used is a TDK CLF7045T-2R2N with a rated current of 5.5A based on the inductance
change, and of 4.3A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS542951 is intended for
use with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use
Equation 8 to determine the required RMS current rating for the output capacitor(s).
VOx ´ (VINx - VOx )
IC2x(RMS) =
12 ´ VINx ´ L1x ´ fSW
(8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.488A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS542951 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1
µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the
SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.
14
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Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
VREG5 Capacitor Selection
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.
Thermal Information
This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to
the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of
thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical
schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.
This design optimizes the heat transfer from the integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 25. Thermal Pad Dimensions
Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VINx and PGNDx broad.
7. Exposed pad of device must be soldered to PGND.
8. VREG5 capacitor should be placed near the device, and connected to GND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shields.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
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12. Providing sufficient vias is preferable for VIN, SW and PGND connections.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
VIN2
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
～0.1µF
VIN1
1
16
VIN2
VBST 1
2
15
VBST2
SW 1
3
14
SW2
4
13
PGND 2
EN1
5
12
EN2
SS1
6
11
SS2
VFB1
7
10
VFB2
GND
8
9
PGND 1
Symmetrical Layout
for CH1 and CH2
VIN INPUT
BYPASS
CAPACITOR
10µF x2
Switching noise
flows through IC
and CIN . It avoids
the thermal Pad.
OUTPUT
FILTER
CAPACITOR
VO2
OUTPUT
INDUCTOR
Recommend to keep
distance more than 3-4mm.
(to avoid noise scattering,
especially GND plane.)
TO ENABLE
CONTROL
Keep
distance more
than 1 inch
VREG 5
POWER GND
To feedback
resisters
Feedback
resisters
BIAS
CAP
GND
PLANE
2,3 or bottom
layer
Via to GND Plane
- Blue parts can be placed on the bottom side
- Connect the SWx pins through another layer with the inductor
(yellow line)
Figure 26. TPS542951 Layout
16
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VOUT2
KEEP
VIAS > 3-4 mm
FROM OUTPUT
CAPACITORS
OUTPUT2
FILTER
CAPACITORS
POWER
GROUND
OUTPUT2
INDUCTOR
KEEP OUTPUT
VIAS > 25 mm
FROM INPUT VIAS
TO ENABLE
CONTROL
VIN INPUT
BYPASS
CAPACITORS
SS2
16
15
14
13
SLOW
START
CAP 2
FEEDBACK
RESISTORS
EXPOSED THERMAL
PAD AREA
2
11
VREG5
VIN1
3
10
GND
VBST1
4
9
VFB1
BOOST
CAPACITOR
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
5
6
7
FEEDBACK
RESISTORS
8
SLOW
START
CAP 1
KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS
VIA to Internal or
Bottom Layer Ground Plane
VIN INPUT
BYPASS
CAPACITORS
TO ENABLE
CONTROL
VIA to internal or
Bottom Layer Etch
OUTPUT1
INDUCTOR
Etch or Copper Fill
on Top Layer
BIAS ANALOG
CAP GROUND
TRACE
SS1
VIN2
EN 1
VFB2
1
PGND1
12
VBST2
SW1
VIN
EN2
BOOST
CAPACITOR
PGND2
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
SW2
KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS
KEEP OUTPUT
VIAS > 25 mm
FROM INPUT VIAS
POWER
GROUND
Internal or Bottom
Layer Ground Plane
Etch on Bottom Layer,
Internal Layer or
Under Component
OUTPUT1
FILTER
CAPACITORS
VOUT1
NOTE: IT IS POSSIBLE TO PLACE
SOME COMPONENTS SUCH AS
BOOST CAPACITOR AND FEEDBACK
RESISTORS ON BOTTOM LAYER
KEEP
VIAS > 3-4 mm
FROM OUTPUT
CAPACITORS
INTERNAL OR
BOTTOM LAYER
GROUND PLANE
Figure 27. RSA Package Layout
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REVISION HISTORY
Changes from Original (July 2012) to Revision A
Page
•
Changed Feature From: 16-Pin HTSSOP To: 16-Pin HTSSOP, 16-Pin VQFN ................................................................... 1
•
Added 16-pin VQFN (RSA) package to the Description text ................................................................................................ 1
•
Added RSA -16 pin to the Ordering Information table .......................................................................................................... 2
•
Added RSA values to ISSC temperature coefficient ............................................................................................................... 3
•
Added the RSA 16 - Package to the Device Information section ......................................................................................... 5
•
Added Figure 27 ................................................................................................................................................................. 17
Changes from Revision A (April 2013) to Revision B
Page
•
Deleted VO1 and VO2 from the RECOMMENDED OPERATING CONDITIONS table ....................................................... 3
•
Changed the GND pin description From: Connect sensitive SSx and VFBx returns to GND at a single point. To:
Connect sensitive VFBx returns to GND at a single point. ................................................................................................... 5
18
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS542951PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
S542951
TPS542951PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
S542951
TPS542951RSAR
ACTIVE
QFN
RSA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
542951
TPS542951RSAT
ACTIVE
QFN
RSA
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
542951
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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