TPS542A50
SNVSBC0B – SEPTEMBER 2020 – REVISED OCTOBER 2021
TPS542A50 4-V to 18-V Input, 15-A, Synchronous Buck Converter
With Differential Remote Sense and I2C
1 Features
2 Applications
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Integrated 9.1-mΩ and 2.6-mΩ MOSFETs support
up to 15-A output current
0.5-V to 5.5-V output voltage range
Fixed-frequency voltage control mode with
selectable internal compensation
Seven selectable frequency settings from 400 kHz
to 2.2 MHz
Synchronizes to an external clock
Fully differential remote sense
Device configurable by analog pinstrap resistors or
through I2C interface
VOUT adjustment with controlled slew rate through
I2C from –20% to +10% in 0.25% steps
Six selectable overcurrent limits, four soft-start
slew rates, and two I2C addresses
Monotonic start-up into pre-biased outputs
EN pin allowing for adjustable input UVLO
Power good indicator
17-µA typical shutdown quiescent current draw
Selectable FCCM or PFM for light load efficiency
–40 to +150°C operating junction temperature
4-mm × 4.5-mm VQFN package
Create a custom design using the TPS542A50
with the WEBENCH® Power Designer
Enterprise storage, SSD
ASIC, SoC, FPGA, DSP core, and I/O rails
Wired networking switches and routers
Industrial machines and machine tools
3 Description
The TPS542A50 is a high-efficiency synchronous
buck converter with differential remote sense and I2C.
This device features fixed-frequency, voltage-control
mode with pinstrap selectable internal compensation
for reduced system cost and complexity. The PWM
can be synchronized to an external clock through
the SYNC pin. Other key features include PFM for
high light load efficiency, low shutdown quiescent
current draw, adjustable UVLO through the EN pin
and monotonic start up into pre-biased conditions.
This device also features an I2C interface for device
configuration and output voltage adjustment. The
TPS542A50 is a lead-free device. It is fully RoHS
compliant without exemption.
Device Information
TPS542A50
(1)
AVIN
VREG
SW
RSP
EN
RSN
SYNC
SDA
FSEL
COMP
SREF
SS/PFM
VSET
ILIM
AGND
BODY SIZE (NOM)
4.50 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
BOOT
PGD
SCL
VQFN (33)
100%
PVIN
VOUT
95%
90%
Efficiency
VIN
PACKAGE(1)
PART NUMBER
85%
80%
1.2MHz_12VIN
1.0MHz_12VIN
0.8MHz_12VIN
0.6MHz_12VIN
75%
PGND
1.2MHz_5VIN
1.0MHz_5VIN
0.8MHz_5VIN
0.6MHz_5VIN
70%
0
Simplified Schematic
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
Typical Efficiency at 1 VOUT
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS542A50
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SNVSBC0B – SEPTEMBER 2020 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 9
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................21
7.5 Programming............................................................ 21
7.6 Pin-Strap Programming............................................ 22
7.7 Register Maps...........................................................22
8 Application and Implementation.................................. 26
8.1 Application Information............................................. 26
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................31
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 33
11 Device and Documentation Support..........................34
11.1 Device Support........................................................34
11.2 Receiving Notification of Documentation Updates.. 34
11.3 Support Resources................................................. 34
11.4 Trademarks............................................................. 34
11.5 Electrostatic Discharge Caution.............................. 35
11.6 Glossary.................................................................. 35
12 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2020) to Revision B (October 2021)
Page
• Changed "VVRSF" to "VRSP" for IQ - PFM Mode current test condition in the Electrical Characteristics table..... 5
• Changed RFSEL test condition values under Switching Frequency in the Electrical Characteristics ................. 5
• Changed RILIM test condition values under Current Sense and Protection in the Electrical Characteristics ..... 5
• Changed title from "Line Regulation" to "Load Regulation" in Figure 6-8 and Figure 6-9 ................................. 9
• Removed "Chroma" from title of Figure 6-23 and Figure 6-24 .......................................................................... 9
• Updated RFSEL, RCOMP, RSS/PFM and RILIM with correct values across document........................................... 14
• Changed RFSEL values in Table 7-1 .................................................................................................................16
• Changed RCOMP values in Table 7-2 ................................................................................................................16
• Changed RSS/PFM values in Table 7-5 ..............................................................................................................18
• Changed RILIM values in Table 7-7 .................................................................................................................. 19
• Changed RCOMP values in Table 7-8 ................................................................................................................21
• Updated the output voltage increments percentage value and removed the tables which included the binary
codes for adjusting the output voltage.............................................................................................................. 22
• Updated the RESERVED field to a R/W type................................................................................................... 24
• Updated all figures in Section 8.2.1.4 to demonstrate new RFSEL, RCOMP, RSS/PFM and RILIM values............. 30
• Added information on Fusion Digital Power™ designer software tool..............................................................34
Changes from Revision * (September 2020) to Revision A (October 2020)
Page
• Updated Figure 3-1 ............................................................................................................................................1
2
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4
SYNC
5
RSN
6
BOOT
SDA
PVIN
3
PVIN
SCL
PVIN
2
AVIN
SS/PFM
EN
1
FSEL
ILIM
COMP
5 Pin Configuration and Functions
24
23
22
21
20
19
18
17
25
28
27
26
29
SW
30
31
AGND
PGND
10
11
12
13
14
15
VREG
PGND
PGND
16
PGND
9
PGND
8
PGD
7
SREF
RSP
AGND
33
VSET
32
Figure 5-1. 33-Pin VQFN RJM Package (Top View)
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
8, 25
G
Ground of the internal analog and digital circuitry
AVIN
21
P
Power input to the controller. Tie this pin to PVIN. It is best to use an RC filter from PVIN
such as 10 Ω and 100 nF to 1 μF.
BOOT
17
P
Gate drive voltage for high-side FET. Connect a bootstrap capacitor between this pin and
SW.
COMP
24
I
A resistor to ground sets the I2C address and compensation network. This pin can be
grounded to select the default compensation and reduce BOM count.
EN
22
I
Enable pin. Float to enable, enable/disable with an external signal, or adjust the input
undervoltage lockout with a resistor divider.
FSEL
23
I
A resistor to ground sets the switching frequency of the converter. This pin can be grounded
to select the default switching frequency to reduce BOM count.
ILIM
1
I
A resistor to ground sets the overcurrent protection limit. This pin can be grounded to select
default settings and reduce BOM count.
PGD
11
O
Open-drain power good status
PGND
13-16, 29-33
G
Power ground. These pins are internally connected to the return of the internal low-side FET.
PVIN
18-20
P
Power inputs to the power stage. Low impedance bypassing of these pins to PGND is
critical. At least 10 nF to 100 nF capacitor from PVIN to PGND is required.
RSN
6
I
Remote sense ground return
RSP
7
I
Remote sense connection to VOUT
SCL
3
I
Clock input for I2C programming
SDA
4
I/O
Data input for I2C programming
SREF
10
O
1.2-V nominal system reference
SS/PFM
2
I
A resistor to ground sets the soft-start slew rate and PFM mode. To reduce BOM count this
pin can be grounded to use the default soft-start rate and enable PFM mode.
SYNC
5
I
In shutdown mode, an active high puts the IC into programming mode. In operation, this pin
is a clock input for synchronizing the oscillator.
26-28
O
Switch node output of the converter. Connect this pin to the output inductor.
VREG
12
I/O
Bypass pin for the internal power stage LDO. It is recommended to use 4.7-μF ceramic
capacitor to ground.
VSET
9
I
Output voltage reference for the control loop. This must be the mid-point of a resistive
divider from SREF to AGND. Set this voltage to be 1/5 of the desired VOUT.
SW
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input
Output
(1)
MIN
MAX
PVIN, AVIN
–0.3
20
PVIN - SW
–0.3
24
BOOT
–0.3
27.5
BOOT-SW
–0.3
5.5
EN, SYNC, SDA, SCL
–0.3
6
FS, COMP, ILIM, SS/PFM, SREF, VSET
–0.3
1.98
RSP
–0.3
6
PGD
–0.3
6
SW
–0.3
22
–2
22
SW transient ( 1.2 V, no
switching, VRSP > 5*VVSET
V
17
µA
1800
ENABLE and UVLO (EN PIN)
VEN
Enable threshold: ON/OFF
IEN
Enable input current
Rising and falling
1.2
Enable threshold – 50 mV
–0.6
Enable threshold + 50 mV
–5
V
µA
UVLO (AVIN, PVIN PINS)
AVIN, PVIN
UVLO rising threshold
3.75
UVLO falling threshold
3.50
Hysteresis
3.85
4
3.6
3.7
V
4.96
V
220
mA
0.25
INTERNAL REGULATOR, POWER STAGE (VREG PIN)
VVREG
LDO output voltage
LDO output current = 0A
VVREG
LDO output voltage
LDO output current = 30mA
Output current limit
VVREG = 4.7V
Nominal output current
fsw = 2.2 MHz, output current = 15 A,
VVREG = 4.7V
VREG(UVLO)
4.3
4.7
120
170
4.7
V
30
UVLO rising yhreshold
2.8
UVLO falling threshold
2.6
UVLO hysteresis
0.2
mA
V
CONTROL REFERENCE VOLTAGE (SREF PIN)
VSREF
SREF output voltage
Tolerance included in RSP/RSN
accuracy
ISREF
SREF current sourcing capability
Resistance > 6 kΩ
1.2
V
200
µA
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SNVSBC0B – SEPTEMBER 2020 – REVISED OCTOBER 2021
TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output Voltage Accuracy; Vout = 1V
Total internal accuracy, measured at the
RSP and RSN pins = 5*VSET, VSET =
0.2V, –40 to 150°C
-15
15
mV
Output Voltage Accuracy; Vout =1V
Total internal accuracy, measured at the
RSP and RSN pins = 5*VSET, VSET =
0.2V, –40 to 125°C
-13
13
mV
Output Voltage Accuracy; Vout = 1V
Total internal accuracy, measured at the
RSP and RSN pins = 5*VSET, VSET =
0.2V, 0 to 105°C
-11.0
9.0
mV
Output Voltage Accuracy; Vout = 0.8V
Total internal accuracy, measured at the
RSP and RSN pins = 5*VSET, VSET =
0.16V, –40 to 150°C
-15
15
mV
Output Voltage Accuracy; Vout = 1.2V
Total internal accuracy, measured at the
RSP and RSN pins = 5*VSET, VSET =
0.24V, –40 to 150°C
-15
15
mV
Total internal accuracy, measured at the
Output Voltage Accuracy; Vout = 5.5V (1) RSP and RSN pins = 5*VSET, VSET =
1.1V, –40 to 150°C
-30
30
mV
OUTPUT VOLTAGE REGULATION ACCURACY
REMOTE SENSE AMPLIFIER
Unity gain bandwidth (1)
Open loop gain (1)
Slew rate
(1)
MHz
dB
2.5
Input common mode range (1)
-0.05
Input offset voltage (RSA and EA
combined offset trim) (1)
Vos
7
83
V/us
1.1
0.25
V
mV
SWITCHING FREQUENCY
FSW_1MHz
Switching frequency 1MHz
RFSEL = 35.7 kΩ or Short
900
FSW_400kH
Switching frequency 400kHz
z
RFSEL = 7.5 kΩ
FSW_600kH
Switching frequency 600kHz
z
1100
kHz
-10
+15
%
RFSEL = 18.2 kΩ
-10
+15
%
FSW_800kH
Switching frequency 800kHz
z
RFSEL = 26.1kΩ
-10
+15
%
FSW_1.2MH
Switching frequency 1.2MHz
z
RFSEL = 47.5 kΩ
-9
+11
%
FSW_2MHz
RFSEL = 61.9 kΩ
-10
+15
%
RFSEL = 78.7 kΩ
-10
+15
%
Switching frequency 2MHz
FSW_2.2MH
Switching frequency 2.2MHz
z
1000
Minimum On-Time
12
ns
Minimum Off-Time
85
ns
SYNC
VIH(SYNC)
High-level input voltage
VIL(SYNC)
Low-level input voltage
EN = High
1.35
Sync input minimum pulse width
ΔfSYNC
SYNC pin frequency range from fSW
VIH(SYNC)-
High-level input voltage to enter
programming mode when EN = 0V
PROG
–10%
EN = Low
V
0.8
V
50
ns
15%
1.35
V
1.35
V
I2C COMMUNICATION (SDA, SCL)
6
VIH(I2C)
High-level input voltage
VIL(I2C)
Low-level input voltage
0.8
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TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER(1)
IIH(I2C)
High-level input leakage current
IIL(I2C)
Low-level input leakage current
VOL(I2C)
Low-level output voltage
IPULLUP
Current through pull-up resistor
fCLK(I2C)
I2C operating frequency
CPin
Typical pin capacitance for each line
(SDA, SCL)
TEST CONDITIONS
MIN
TYP
–5
–5
IPULLUP = 20mA
10
MAX
UNIT
5
µA
5
µA
0.4
V
20
mA
1000
kHz
10
pF
POWER STAGE
Rds(on)1
Main high-side MOSFET on-resistance
VVREG = 4.7 V, TJ = 25°C
9.1
mΩ
Rds(on)2
Main Low-side MOSFET on-resistance
VVREG = 4.7 V, TJ = 25°C
2.6
mΩ
Tdt(L-H)
Dead-time between low-side off and
high-side on transition
VREG = 4.7V, TJ = 25°C
10
ns
Tdt(H-L)
Dead-time between high-side off and
low-side on transition
VREG = 4.7V, TJ = 25°C
10
ns
20
A
CURRENT SENSE AND PROTECTION
IS1
IS2
OC limit HS FET
OC limit LS FET 6
RILIM = 61.9 kΩ
17.60
20
22
OC limit LS FET 5
RILIM = 47.5 kΩ
14.78
16.5
18.48
OC limit LS FET 4
RILIM = 35.7 kΩ
11.56
13
15.62
OC limit LS FET 3
RILIM = 26.1 kΩ
9.26
10.5
13.56
OC limit LS FET 2
RILIM = 18.2 kΩ
6.96
8
11.60
OC limit LS FET 1
RILIM = 7.5 kΩ
4.66
5.5
9.60
A
IS2
Negative OC limit LS FET
-8.5
A
IS2
Zero-cross detection comparator trip
point
135
mA
SOFT-START COUNTER
tSS
SS setting 1: 2.0MHz CLK
VVSET = 0.1 V to 0.28 V
0.45
SS setting 2: 1.0MHz CLK
VVSET = 0.1 V to 0.28 V
0.9
SS setting 3: 0.5MHz CLK
VVSET = 0.1 V to 0.28 V
1.8
SS setting 4: 0.25MHz CLK
VVSET = 0.1 V to 0.28 V
3.6
ms
OUTPUT ADJUSTMENT
Output voltage adjust upper limit
10
%
Output voltage adjust lower limit
–20
%
Step size
0.5
%
0.3
V
INTERNAL BOOTSTRAP SWITCH
Forward voltage
VVREG(BOOT), IF = 10 mA, TA = 25°C
0.16
From EN to SS; VIN > 4 V
500
OUTPUT VOLTAGE OVERSHOOT REDUCTION
POWER-ON DELAY
Power-on delay time
us
POWER GOOD and OV/UV WARNING
VRSP
OV warning level
RSP rising (fault)
105
110
OV warning level
RSP falling (reset)
100
105
UV warning level
RSP falling (fault)
87
90
UV warning level
RSP rising (reset)
91
PGD delay time
Delay from SS finish to PGD high
Rds(on)PGFET
PGD FET On Resistance, IPGOOD =5mA
95
115
109
%
93.5 5*VVSET
99
500
4.1
5.8
µs
9.1
Ω
OUTPUT OVERVOLTAGE PROTECTION (OVP)
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TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER(1)
VRSP
TEST CONDITIONS
OVP trip level
RSP rising (fault), VVSET ≤ 1.04 V
OVP reset level
RSP falling
MIN
TYP
MAX
110
115
120
76
80
OVP delay
UNIT
%
84 5*VVSET
100
ns
OUPUT UNDERVOLTAGE PROTECTION (UVP)
VRSP
UVP detect voltage
76
UV delay
80
84
%
5*VSET
100
ns
165
0C
15
0C
THERMAL SHUTDOWN
TSDN
Shutdown temperature(1)
155
Hysteresis(1)
(1)
8
Specified by design. Not production tested.
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6.6 Typical Characteristics
Measured at 25°C unless otherwise specified
100%
95%
Power Loss (W)
Efficiency ()
90%
85%
80%
75%
5VIN
9VIN
12VIN
14VIN
70%
65%
0
1
2
3
4
5
VOUT = 1 V
6 7 8 9 10 11 12 13 14 15
Output Current (A)
0
90%
Power Loss (W)
Efficiency ()
80%
75%
70%
65%
5VIN FCCM
5VIN DCM
12VIN FCCM
12VIN DCM
60%
55%
50%
2
3
4
5
VOUT = 1 V
2
3
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
fSW = 1 MHz, FCCM
Figure 6-2. Power Loss vs Output Current
95%
85%
1
VOUT = 1 V
100%
1
5VIN
9VIN
12VIN
14VIN
fSW = 1 MHz, FCCM
Figure 6-1. Efficiency vs Output Current
0
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
6 7 8 9 10 11 12 13 14 15
Output Current (A)
5VIN FCCM
5VIN DCM
12VIN FCCM
12VIN DCM
0
fSW = 1 MHz, DCM versus FCCM
1
2
3
4
5
VOUT = 1 V
6 7 8 9 10 11 12 13 14 15
Output Current (A)
fSW = 1 MHz, DCM versus
FCCM
Figure 6-3. Efficiency vs Output Current
Figure 6-4. Power Loss vs Output Current
100%
5
9VIN
12VIN
14VIN
4.5
95%
4
Power Loss (W)
Efficiency ()
90%
85%
80%
9VIN
12VIN
14VIN
75%
70%
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
VOUT = 5 V
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
fSW = 400 kHz, FCCM
Figure 6-5. Efficiency vs Output Current
0
1
2
3
VOUT = 5 V
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
fSW = 400 kHz, FCCM
Figure 6-6. Power Loss vs Output Current
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1.015
1.015
5VIN
5VIN
5VIN
5VIN
1.012
12VIN
12VIN
12VIN
12VIN
25C
-40C
85C
105C
1.006
1.003
1
0.997
0.994
5VIN
5VIN
5VIN
5VIN
1.012
1.009
Output Votlage (V)
Output Voltage (V)
1.009
25C
-40C
85C
105C
25C
-40C
85C
105C
12VIN
12VIN
12VIN
12VIN
25C
-40C
85C
105C
1.006
1.003
1
0.997
0.994
0.991
0.991
0.988
0.988
0.985
0.985
0
1
2
3
4
5
0
6 7 8 9 10 11 12 13 14 15
Output Current (A)
VOUT = 1 V
fSW = 1 MHz, FCCM
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
VOUT = 1 V
Figure 6-7. Load Regulation
fSW = 1 MHz, DCM
Figure 6-8. Load Regulation
110
5.05
Output Voltage (V)
5.03
5.02
5.01
5
4.99
4.98
4.97
9VIN 25C
9VIN -40C
9VIN 85C
4.96
12VIN 25C
12VIN -40C
12VIN 85C
Ambient Temperature (0C)
5.04
4.95
0
1
2
3
4
5
VIN = 12 V
fSW = 400 KHz,
FCCM
110
105
95
90
85
80
Nat conv
100 LFM
200 LFM
400 LFM
75
1
3
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
VOUT = 1 V
fSW = 1 MHz
100
95
90
85
80
Nat conv
100 LFM
200 LFM
400 LFM
75
65
2
Figure 6-10. Ambient Temperature vs Output
Current
105
100
Nat conv
100 LFM
200 LFM
400 LFM
VIN = 12 V
110
70
70
0
1
2
VIN = 12 V
3
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
VOUT = 5 V
fSW = 600 kHz
Figure 6-11. Ambient Temperature vs Output
Current
10
95
0
Ambient Temperature (0C)
Ambient Temperature (0C)
Figure 6-9. Load Regulation
100
90
6 7 8 9 10 11 12 13 14 15
Output Current (A)
VOUT = 5 V
105
0
1
2
VIN = 5.5 V
3
4
5
6 7 8 9 10 11 12 13 14 15
Output Current (A)
VOUT = 1 V
fSW = 2.2 MHz
Figure 6-12. Ambient Temperature vs Output
Current
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VIN = 12 V
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VOUT = 1 V
fSW = 1 MHz
VIN = 5.5 V
VOUT = 1 V
fSW = 2.2 MHz
Figure 6-13. Thermal Image at 15-A Output Current Figure 6-14. Thermal Image at 14-A Output Current
VIN = 12 V
VIN = 12 V
VOUT = 5 V
fSW = 0.6 MHz
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-16. 100% Pre-biased Start-up by EN at 0-A
Output Current
Figure 6-15. Thermal Image at 12-A Output Current
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-17. 90% Pre-biased Start-up by EN at 0-A
Output Current
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-18. 50% Pre-biased Start-up by EN at 0-A
Output Current
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VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-19. Start-up and Shutdown by EN at 0-A
Output Current
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-21. Steady State at 10-A Output Current
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-23. 20-A Overcurrent Protection by
Electronic Load
12
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-20. Steady State at 0-A Output Current
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-22. Switch Node Ringing and Dead-Time
at 10-A Output Current
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-24. Short Overcurrent Protection Hiccup
by Electronic Load
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VIN = 12 V
VOUT = 1 V
fSW = 1.2 MHz BOM
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-25. Overvoltage Protection, Negative OCP, Figure 6-26. Load Transient 2 A to 12 A to 2 A at 20
A/μs
then Undervoltage Protection by Load Stepdown
VIN = 12 V
VOUT = 1 V
fSW = 1.0 MHz BOM
Figure 6-27. Load Transient in DCM to FCM 0.5 A to 10.5 A to 0.5 A at 1 A/μs
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7 Detailed Description
7.1 Overview
The TPS542A50 is a high-efficiency, single-channel, synchronous buck converter with integrated n-channel
MOSFETs. The device suits low-output voltage point-of-load applications with 15-A or lower current. The
TPS542A50 has a maximum operating junction temperature of 150°C, making it suitable for high-ambient
temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V, and the output
voltage range is 0.5 V to 5.5 V. The device features a fixed-frequency, voltage-control mode with a switching
frequency range of 400 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter
components. The controller features selectable internal compensation that makes the device easy to use with
low external component count. The internal compensation networks support a wide range of output inductance
and capacitance, supporting all types of capacitors. The controller uses a digital PWM modulator that allows
for very narrow on-times with low jitter, making it ideal for high-frequency and high-step down ratio applications.
The switching frequency of the device can be synchronized to an external clock applied to the SYNC pin. The
TPS542A50 also features an I2C interface for device configuration and output voltage adjustment.
7.2 Functional Block Diagram
14
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7.3 Feature Description
7.3.1 Enable and Adjustable Undervoltage Lockout
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold
voltage (typically 1.2 V), the device starts operation. If the EN pin voltage is pulled below the threshold voltage,
the regulator stops switching and enters low power shutdown.
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device.
The EN pin can also be externally driven high or low.
For adjustable input undervoltage lockout (UVLO), connect the EN pin to the middle point of an external resistor
divider. Once the EN pin voltage exceeds the threshold, an additional 5 µA of hystersis current is added to
facilitate UVLO hysteresis. Equation 1 shows the calculation of resistor divider network.
VIN
IP
IH
RHS
RLS
EN
VEN
+
-
Figure 7-1. EN UVLO
RHS
RLS
VEN
VSTART VSTOP
IH
VSTOP
1.2V; IP
RHS ˜ VEN
VEN RHS IP
IH
0.6PA; IH
5PA
(1)
7.3.2 Input and VREG Undervoltage Lockout Protection
The TPS542A50 provides fixed VIN and VREG UVLO thresholds and hysteresis. The typical VIN turnon
threshold is 3.85 V and hystersis is 0.25 V. The typical VREG turnon threshold is 2.8 and hysteresis is 0.2
V. There is no power-up sequence. Once all of the UVLO requirements have been met and the EN pin voltage
exceeds the enable threshold, the converter begins operation.
7.3.3 Voltage Reference and Setting the Output Voltage
The device has a 1.2-V reference that comes out on the SREF pin. To set the reference voltage of the converter,
connect the VSET pin to the mid-point of a resistor divider between SREF and AGND. TI recommends that the
total impedance of this divider network be > 6 kΩ. Do not connect anything other than a resistor divider network
to SREF.
There is an internal 5:1 resistor divider between the RSP and RSN feedback pins, so the VSET voltage must be
set to 1/5 of the desired output voltage. VSET can be programmed to any value between 0.1 and 1.1 V.
7.3.4 Remote Sense Function
RSP and RSN pins are used for remote sensing purposes. Always connect RSP to the positive sensing point of
the load, and always connect the RSN pin to the load return. There is an internal 5:1 divider in the device, so do
not connect an external feedback resistor divider. The converter loop gain can tolerate between 10 Ω to 50 Ω in
series with RSP and output voltage.
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7.3.5 Switching Frequency
The internal oscillator of the device can be set to one of seven switching frequencies by a resistor to ground
on the FSEL pin or through I2C programming. The FSEL pin can be shorted to ground to reduce BOM
component count. When shorted to ground, the default converter switching frequency is used. If the user
programs the switching frequency using the I2C interface, TI recommends shorting the FSEL pin to ground to
reduce component count. The following frequencies can be programmed on the FSEL pin.
Table 7-1. Frequency
Resistor Selection
RFSEL (kΩ)
fSW (kHz)
Short
1000
7.5
400
18.2
600
26.1
800
35.7
1000
47.5
1200
61.9
2000
78.7
2200
The oscillator can also be synchronized to an external clock on the SYNC pin. The external clock frequency
must be within -10% and +15% of the programmed frequency of the converter. The SYNC pin has an internal
pulldown so it can be left floating externally.
When the converter operates at 2 MHz or 2.2 MHz, it is recommended to set the OCP at 13 A or lower and
without a snubber circuit. For operation with OCP at 16.5 A, a snubber circuit is required. The snubber circuit
components can start with a 470-pF cap and 2-Ω resistor. The component values will need to be tuned to
achieve optimal results.
7.3.6 Voltage Control Mode Internal Compensation
The TPS542A50 has 15 unique internal compensation settings to cover a wide range of output inductors and
capacitors. For each switching frequency option, there are four compensation options that can be chosen using
a single resistor to ground on the COMP pin or through I2C programming.
In addition to selecting the compensation option, the COMP pin also selects the device I2C address. The
following compensation settings and I2C address combinations can be programmed on the COMP pin.
Table 7-2. Compensation and I2C Address Resistor
Selection
RCOMP (kΩ)
I2C ADDRESS
COMPENSATION
SETTING
Short
0x60
COMP 2
7.5
18.2
26.1
COMP 1
0x60
COMP 2
COMP 3
35.7
COMP 4
47.5
COMP 1
61.9
78.7
0x61
102
COMP 2
COMP 3
COMP 4
Each compensation network consists of two zeros and one high frequency pole. Table 7-3 maps the
compensation settings to the first zero frequency at different output voltage range, second zero frequency, and
high frequency pole.
16
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Table 7-3. Compensation Settings
FREQUENCY (kHz)
400
600
800
1000
1200
2000
2200
COMPENSATION SETTING
ZERO 1
(kHz) FOR
VOUT =
0.5 V-1.1 V
ZERO 1
(kHz) for
VOUT = 1.2
V-1.5 V
ZERO 1
(kHz) FOR
VOUT = 1.6
V-2.8 V
ZERO 1
(kHz) FOR
VOUT = 2.9
V-4.0 V
ZERO 1 (kHz)
for VOUT = 4.1
V-5.5 V
ZERO 2
(kHz)
POLE
(kHz)
COMP 1
2.2
2.1
1.8
1.6
1.2
5.5
60
COMP 2
2.2
2.1
1.8
1.6
1.2
7.3
80
COMP 3
3.6
3.4
3.0
2.7
2.0
14.5
159
COMP 4
7.2
7.0
6.1
5.4
4.1
28.4
312
COMP 1
2.2
2.1
1.8
1.6
1.2
5.5
60
COMP 2
2.7
2.6
2.3
2.0
1.5
11.0
121
COMP 3
4.5
4.3
3.8
3.4
2.5
18.1
199
COMP 4
10.5
10.1
8.8
7.9
5.9
45.2
497
COMP 1
2.2
2.1
1.8
1.6
1.2
7.3
80
COMP 2
3.6
3.4
3.0
2.7
2.0
14.5
159
COMP 3
7.2
7.0
6.0
5.4
4.1
28.4
312
COMP 4
13.5
13
11.4
10.1
7.6
55.6
612
COMP 1
2.2
2.1
1.9
1.7
1.2
9.0
99
COMP 2
4.5
4.3
3.8
3.4
2.5
18.1
199
COMP 3
9.0
8.7
7.6
6.7
5.1
37.1
408
COMP 4
18.8
18.2
15.9
14.1
10.6
72.3
796
COMP 1
2.7
2.6
2.3
2.0
1.5
11.0
121
COMP 2
4.5
4.3
3.8
3.4
2.5
18.1
199
COMP 3
10.5
10.1
8.8
7.9
5.9
45.2
497
COMP 4
23.5
22.7
19.9
17.7
13.3
90.4
995
COMP 1
4.5
4.3
3.8
3.4
2.5
18.1
199
COMP 2
9
8.7
7.6
6.7
5.1
37.1
408
COMP 3
18.8
18.2
15.9
14.1
10.6
72.3
796
COMP 4
37.7
36.4
31.8
28.3
21.2
144.7
1592
COMP 1
4.5
4.3
3.8
3.4
2.5
18.1
199
COMP 2
9
8.7
7.6
6.7
5.1
37.1
408
COMP 3
18.8
18.2
15.9
14.1
10.6
72.3
796
COMP 4
37.7
36.4
31.8
28.3
21.2
144.7
1592
Table 7-4 shows the second zero frequency placement about two times based on a ratio (fO/fSW) of the LC
frequency (fO) to the switching frequency and lists the values in Table 7-3. The second zero frequency does
not change with the output voltage. The high frequency pole is about 10 times of the second zero frequency to
attenuate the switching frequency noise and to have a safe gain margin.
The output filter LC frequency must be designed between the first and second zero frequencies. The ratio of the
LC frequency to the switching frequency in Table 7-4 is a guide to select the LC frequency fO. For example, the
LC frequency for 1-MHz switching frequency is 10 kHz at 1% ratio. Given 1-V output voltage, COMP2 has the
first zero at 4.5 kHz to compensate the LC filter double poles. For the same LC filter and switching frequencies
of 3.3-V output voltage, COMP3 has the first zero at 6.7 kHz to compensate the LC filter double poles. The
compensation setting needs to consider for the output capacitor derating, especially ceramic capacitor, and
inductor tolerance. It is recommended to verify the load transient and bode plot based upon the compensation
selection.
Table 7-4. Second Zero Frequency
fO/fSW
COMPENSATION
SETTING
SECOND ZERO
FREQUENCY
0.5%
COMP 1
~2X of 0.5% fO/fSW
1%
COMP 2
~2X of 1% fO/fSW
2%
COMP 3
~2X of 2% fO/fSW
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Table 7-4. Second Zero Frequency (continued)
fO/fSW
COMPENSATION
SETTING
SECOND ZERO
FREQUENCY
4%
COMP 4
~2X of 4% fO/fSW
7.3.7 Soft Start and Prebiased Output Start-up
The TPS542A50 uses a programmable soft-start rate to gradually ramp the output voltage reference to reduce
inrush currents. The device prevents current from being discharged from the output during start-up when a
pre-biased condition exists. No switching pulses occur until the internal soft-start reference exceeds the voltage
on the error amplifier input voltage (RSP and RSN pins). The TPS542A50 supports the output voltage with
pre-biased up to 100%.
The soft-start clock in Table 7-5 can be programmed on the SS/PFM pin along with enabling/disabling PFM
and hiccup time. These same options can also be programmed through the I2C interface. The SS/PFM pin
can be shorted to ground to reduce BOM component count. When shorted to ground the default soft-start slew
rate is used, and PFM is disabled. If the user programs these functions frequently using the I2C interface, TI
recommends shorting the SS/PFM pin to ground to reduce component count. The soft-start timing in Table 7-6
can be programmed based upon the output voltage and soft-start clock. There are four choices of soft-start times
to select different soft-start clocks. Using 1-V output voltage as an example, the soft-start time equals to 1.8 ms
at 0.5-MHz SS CLK and 0.45 ms at 2.0-MHz SS CLK.
Table 7-5. Soft-Start CLK and PFM Resistor
Selection and Hiccup Time
RSS/PFM (kΩ)
PFM
SS CLK
(MHz)
HICCUP
DURATION (ms)
Short
Disable
1.0
25.2
2.0
12.6
7.5
18.2
1.0
25.2
0.50
50.4
35.7
0.25
100.8
47.5
2.0
12.6
26.1
61.9
78.7
102
18
Enable
Disable
1.0
25.2
0.50
50.4
0.25
100.8
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Table 7-6. Soft-Start Timing versus Output Voltage
LSB SIZE (mV)
SS TIMING (ms) AT
CLK: 2.0 MHz
0.5
0.112
0.45
0.9
1.8
3.6
1
0.223
0.45
0.9
1.8
3.6
0.28
1.4
0.313
0.45
0.9
1.8
3.6
0.3
1.5
0.167
0.9
1.8
3.6
7.2
0.4
2.0
0.223
0.9
1.8
3.6
7.2
0.5
2.5
0.279
0.9
1.8
3.6
7.2
0.56
2.8
0.313
0.9
1.8
3.6
7.2
0.6
3.0
0.167
1.8
3.6
7.2
14.4
0.7
3.5
0.195
1.8
3.6
7.2
14.4
0.8
4
0.223
1.8
3.6
7.2
14.4
0.9
4.5
0.251
1.8
3.6
7.2
14.4
1
5.0
0.279
1.8
3.6
7.2
14.4
VSET (V)
VOUT (V)
0.1
0.2
SS TIMING (ms) AT SS TIMING (ms) AT SS TIMING (ms) AT
CLK: 1.0 MHz
CLK: 0.5 MHz
CLK: 0.25 MHz
7.3.8 Power Good
The power good pin is an open-drain output and needs to pull up to a voltage supply if a designer uses this
feature. During normal converter operation, the device leaves this pin floating. Power good warnings occur if the
output voltage is not within the OV or UV warning levels. Power Good (PGD) is forced low when a fault occurs,
when the converter is in soft start, and when the converter is in shutdown or programming mode. The PGD pin is
released to floating after the PGD delay time when all of the above conditions are met.
TI recommends connecting a pullup resistor to a voltage source that is 5.5 V or less, such as to the device
VREG pin.
7.3.9 Overvoltage and Undervoltage Protection
An output overvoltage (OV) fault is triggered if the output voltage, sensed by RSP/RSN, is greater than the OVP
trip level. When this condition is detected, the converter terminates the switching cycle and turns on the low-side
FET to discharge the output voltage. The low-side FET remains on until the low-side FET current reaches the
negative overcurrent limit. When the negative overcurrent limit is reached, the low set FET turns off for 2000
ns. After the 2000 ns delay, the low-side FET turns back on until the negative overcurrent limit is reached. This
process repeats until the output voltage is discharged below the undervoltage fault threshold (typically 80% set
VOUT). The converter then enters hiccup for seven cycles of soft-start CLK frequency due to the output voltage
being below the UV threshold.
An output undervoltage fault is triggered if the output voltage, sensed by RSP/RSN, is less than UVP threshold.
When this condition is detected, power conversion is disabled, and the converter enters hiccup for seven cycles
of soft-start CLK frequency.
7.3.10 Overcurrent Protection
The device senses overcurrent (OC) in both the high-side and low-side power MOSFETs using cycle by cycle
detection. OC is detected in the low-side FET by sensing the voltage across the FET while it is on. After the
low-side FET turns on, there is a blanking time of approximately 70 ns to allow noise to settle before the OC
comparator begins sensing. Once an OC fault condition is detected, the device stops switching and enters
hiccup for seven cycles of soft-start CLK frequency. The overcurrent limit is set through a single resistor to
ground on the ILIM pin or through I2C programming. The ILIM pin can be shorted to ground to reduce BOM
component count. When shorted to ground, the default current limit is used. If the user programs the current
limit using the I2C interface, TI recommends shorting the ILIM pin to ground to reduce component count. Current
limits shown in Table 7-7 can be programmed on the ILIM pin.
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Table 7-7. Current Limit Resistor Selection
RILIM (kΩ)
TYPICAL LIMIT (A)
Short
20
7.5
5.5
18.2
8
26.1
10.5
35.7
13
47.5
16.5
61.9
20
The device also senses negative overcurrent in the low-side FET by sensing the voltage across the FET while it
is on. After the low-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator
begins sensing. Once a negative OC fault condition is detected, the device stops switching and enters hiccup for
seven cycles of soft-start CLK frequency. The negative overcurrent threshold is fixed to a single value.
Overcurrent is detected in the high-side FET by sensing the voltage across the FET while it is on. After the
high-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator begins
sensing. Once an OC fault condition is detected, the device stops switching and enters hiccup for seven cycles
of soft-start CLK frequency. The high-side overcurrent threshold is fixed to a single value. For an application with
on-time less than 70 ns, the high-side FET overcurrent is not guaranteed to enable. In this case, the low-side
OC will dominate and protect the load while the output current ramps up gradually. With on-times less than 70 ns
and a hard short at the load, the controller loop will extend the on-time to respond to the output voltage drooping,
and as a result, both high-side and low-side OC protections will engage to protect the load.
7.3.11 High-Side FET Throttling
When the high-side FET turns on or off, the ringing voltage across the FET depends on the output current,
loop inductance, and PCB parasitic inductance. To diminish the ringing voltage during turning on or off, the
TPS542A50 reduces the gate driver strength when TPS542A50 detects PVIN higher than 14 V with 0.5-V
hysteresis.
7.3.12 Overtemperature Protection
When the device senses a temperature above the thermal shutdown limit (typically 165°C), power conversion is
disabled. The converter remains disabled until the temperature cools down to the thermal recovery limit (typically
150°C). At this point, the converter enters hiccup for seven cycles of soft-start CLK frequency.
20
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7.4 Device Functional Modes
7.4.1 Pulse-Frequency Modulation Eco-mode™ Light Load Operation
When the SS/PFM pin is terminated with a 35.7-kΩ or lower resistance, the TPS542A50 operates in pulsefrequency modulation (PFM) for light load conditions to maintain high efficiency.
As the output current decreases from heavy-load conditions, the inductor current also decreases until the valley
of the inductor current reaches zero amps, which is the boundary between continuous-conduction mode (CCM)
and discontinuous-conduction mode (DCM). The synchronous MOSFET turns off when this zero inductor current
is detected. As the load current decreases further, the converter runs in DCM. In DCM operation, the on-time is
maintained to a level approximately the same as during CCM and the converter off-time is modulated to maintain
the proper output voltage. For the application of 5-V input voltage, it is not recommend to operate in PFM due to
the accuracy of the zero comparator which will be reduced because of the low input voltage.
7.4.2 Forced Continuous-Conduction Mode
When the SS/PFM pin is terminated with a 47.5-kΩ or higher resistance, the TPS542A50 operates in forced
continuous conduction mode (FCCM) for all load currents. During FCCM, the switching frequency is set by an
internal oscillator for which the frequency can either be selected by the FSEL pin, programmed through I2C, or
synchronized to an external clock on the SYNC pin.
7.4.3 Soft Start
The TPS542A50 operates in FCCM during soft start regardless of the setting selected by the SS/PFM pin. If
PFM is enabled by the SS/PFM pin, the PFM operation begins after PGD is asserted. The delay between soft
start finishing and PGD being asserted is typically 500 µs. During the start-up, the TPS542A50 has the low-side
current limit at 16.5 A when the OCP configures 20 A. However, if the OCP configures below 16.5 A such as 13
A, then the current limit during soft start sets to be at 13 A.
7.5 Programming
7.5.1 I2C Address Selection
The I2C address is selected by a single resistor to ground on the COMP pin. Note that this function is combined
with setting the compensation value. Refer to Table 7-8 for selecting a COMP pin resistor value for your
application.
Table 7-8. COMP Resistor
Selection for I2C Address
RCOMP (kΩ)
I2C ADDRESS
≤ 35.7
0x60
≥ 47.5
0x61
7.5.2 Powering Device Into Programming Mode
The TPS542A50 can be powered on into programming mode for pre-operation configuration by bringing the
SYNC pin above the SYNC threshold. This wakes up the device from low-power shutdown mode and the I2C
interface is active for communication. Once the device configuration is complete, the EN pin can be brought
above the EN threshold to begin power conversion. After this, the SYNC pin can either be driven low, Hi-Z, or
used to synchronize the switching frequency to an external clock.
7.5.3 Device Configuration
The device settings can be configured when in programming mode before the device begins power conversion.
When in programming mode, the switching frequency, current limit, internal compensation, soft-start rate, and
FCCM enable/disable can be configured. Once the voltage on the EN pin exceeds the EN threshold and power
conversion begins, these registers are read only. Configuration settings will be lost if device is allowed to go back
into low-power shutdown mode.
When the TPS542A50 detects an individual fault of OCP, OT, OV, or UV, the STATUS register (0x01) asserts a
logic high or "1" in its respective bit field. The asserted fault bits will remain high even after the fault is removed.
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To clear the asserted fault bits, cycle power to the device, or write a logic high to the bit field of the STATUS
register for the desired bits to be cleared. Bits can be cleared individually or all at once by writing “0xDE.” In the
case of both OCP and OT bits detection, they are designed to automatically clear one another. For example, in
the case of an OCP fault followed by an OT fault, the OCP will initially assert a logic high, but when the OT is
encountered, the OCP will automatically clear to a logic low or “0”, and only the OT fault bit will remain asserted
as a logic high. If the events are encountered in the reverse order, then only the OCP will remain asserted as a
logic high and the OT fault bit will be cleared to a logic low.
7.5.4 Output Voltage Adjustment
The TPS542A50 output voltage can be adjusted in ~0.028% increments from –20% to +10% of the set output
voltage. This function can only be performed after PGOOD goes high. During programming mode, these
registers are read only.
For positive margin, write to 0x02 and 0x03 registers. Writing only to the 0x02 register does not adjust the output
voltage. Writing to both registers, 0x02 and 0x03, does adjust the output voltage. Bits [7:3] of register 0x02 must
be equal to 0000 for a positive output voltage adjustment. Bits [7:3] of register 0x02 must be 1111 for a negative
output voltage adjustment.
•
•
•
Writing 0x01 to 0x02 register and 0x66 to 0x03 register will margin the output voltage +10%. The output
voltage will transition with a slew rate of soft start.
Writing 0xFD to 0x02 register and 0x34 to 0x03 register will margin the output voltage -20%.
Writing 0x01 to the 0x03 register will step the output voltage margin by one positive step. The 0x02 register
does not have to be written for small positive steps.
7.6 Pin-Strap Programming
Table 7-9 and Table 7-10 provide the binary code for these pin-strap pins.
Table 7-9. Pin-Strap Programming 1
RILIM (kΩ)
RFSEL (kΩ)
BINARY CODE
7.5
7.5
000
18.2
18.2
001
26.1
26.1
010
35.7
35.7
011
47.5
47.5
100
61.9
61.9
101
N/A
78.7
110
N/A
N/A
111
Table 7-10. Pin-Strap Programming 2
I2C
ADDRESS
RSS/PFM
(kΩ)
BINARY
CODE
COMPENSATION
SETTING
BINARY
CODE
7.5
00
COMP 1
18.2
01
COMP 2
26.1
10
COMP 3
35.7
11
COMP 4
11
47.5
00
COMP 1
00
61.9
01
COMP 2
78.7
10
COMP 3
102
11
COMP 4
00
0x60
0x61
01
10
01
10
11
7.7 Register Maps
Table 7-11 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in
Table 7-11 should be considered as reserved locations and the register contents should not be modified.
22
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Table 7-11. Device Registers
Offset
Acronym
Register Name
Section
0x0
ID
Go
0x1
STATUS
Go
0x2
VOUT_ADJ1
Go
0x3
VOUT_ADJ2
Go
0x4
CONFIG1
Go
0x5
CONFIG2
Go
Complex bit access types are encoded to fit into small table cells. Table 7-12 shows the codes that are used for
access types in this section.
Table 7-12. Device Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
7.7.1 ID Register (Offset = 0x0) [reset = 0x21]
ID is shown in Figure 7-2 and described in Table 7-13.
Return to Summary Table.
Figure 7-2. ID Register
7
6
5
4
3
2
1
0
0
IC_Revision
R-0x21
Table 7-13. ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
IC_Revision
R
0x21
IC Revision
7.7.2 STATUS Register (Offset = 0x1) [reset = 0x0]
STATUS is shown in Figure 7-3 and described in Table 7-14.
Return to Summary Table.
Figure 7-3. STATUS Register
7
6
5
4
3
2
1
RESERVED
OT_FAULT
OC_FAULT
OV_FAULT
UV_FAULT
PGOOD
R-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
Table 7-14. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0x0
Reserved
4
OT_FAULT
R/W
0x0
Overtemperature Fault Flag
3
OC_FAULT
R/W
0x0
Overcurrent Fault Flag
2
OV_FAULT
R/W
0x0
Output Overvoltage Fault Flag
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Table 7-14. STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
UV_FAULT
R/W
0x0
Output Undervoltage Fault Flag
0
PGOOD
R/W
0x0
Power Good Indicator
7.7.3 VOUT_ADJ1 Register (Offset = 0x2) [reset = 0x0]
VOUT_ADJ1 is shown in Figure 7-4 and described in Table 7-15.
Return to Summary Table.
Figure 7-4. VOUT_ADJ1 Register
7
6
5
4
3
2
1
RESERVED
VOUT_ADJ
R/W-0x0
R/W-0x0
0
Table 7-15. VOUT_ADJ1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0x0
Reserved
3-0
VOUT_ADJ
R/W
0x0
Output Voltage Adjustment Most Significant Bits
For the command to work, bits [7:4] must match bit 3. For example, bit [7:4] = 0000 then bit 3 must equal 0.
Otherwise, no changes are made.
7.7.4 VOUT_ADJ2 Register (Offset = 0x3) [reset = 0x0]
VOUT_ADJ2 is shown in Figure 7-5 and described in Table 7-16.
Return to Summary Table.
Figure 7-5. VOUT_ADJ2 Register
7
6
5
4
3
2
1
0
VOUT_ADJ
R/W-0x0
Table 7-16. VOUT_ADJ2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
VOUT_ADJ
R/W
0x0
Output Voltage Adjustment Least Significant Bits
7.7.5 CONFIG1 Register (Offset = 0x4) [reset = 0x0B]
CONFIG1 is shown in Figure 7-6 and described in Table 7-17.
Return to Summary Table.
Figure 7-6. CONFIG1 Register
7
6
5
4
3
2
1
RESERVED
RESERVED
RESERVED
COMP
FSW
R-0x0
R-0x0
R-0x0
R/W-0x1
R/W-0x3
0
Table 7-17. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0x0
Reserved
6
RESERVED
R
0x0
Reserved
5
RESERVED
R
0x0
Reserved
COMP
R/W
0x1
Internal Compensation
4-3
24
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Table 7-17. CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
FSW
R/W
0x3
Switching Frequency
7.7.6 CONFIG2 Register (Offset = 0x5) [reset = 0x2D]
CONFIG2 is shown in Figure 7-7 and described in Table 7-18.
Return to Summary Table.
Figure 7-7. CONFIG2 Register
7
6
5
4
3
2
1
0
RESERVED
ILIM
FCCM
SS
R-0x0
R/W-0x3
R/W-0x1
R/W-0x1
Table 7-18. CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0x0
Reserved
5-3
ILIM
R/W
0x3
Overcurrent Limit
FCCM
R/W
0x1
Force Continuous Conduction Mode
SS
R/W
0x1
Soft Start Rate
2
1-0
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS542A50 is a high-efficiency, single-channel, synchronous buck converter with integrated n-channel
MOSFETs. The device suits low-output voltage point-of-load applications with 15-A or lower current. The
TPS542A50 has a maximum operating junction temperature of 150°C, which makes it suitable for high-ambient
temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V, and the output
voltage range is 0.5 V to 5.5 V. The device features a fixed-frequency voltage-control mode with a switching
frequency range of 400 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter
components. The controller features selectable internal compensation making the device easy to use with a
low external-component count. The internal compensation networks are able to support a wide range of output
inductance and capacitance, supporting all types of capacitors. The controller utilizes a digital PWM modulator
that allows for very narrow on-times making it ideal for high-frequency and high-step down ratio applications.
The switching frequency of the device can be synchronized to an external clock applied to the SYNC pin. The
TPS542A50 also features an I2C interface for device configuration and output voltage adjustments.
8.2 Typical Application
8.2.1 Full Analog Configuration
A resistor to ground on the FSEL, COMP, SS/PFM, and ILIM pins configure the device. Any of these pins can be
grounded to use the default values and reduce component count.
PVIN
VIN
AVIN
CIN
VREG
RENH
RPGD
CBST
BOOT
L
SW
PGD
RSP
EN
RSN
VOUT
COUT
CVREG
RENL
SYNC
SCL
FSEL
SDA
COMP
R1
SREF
SS/PFM
VSET
R2
AGND
ILIM
RILIM RSS/PFM
RCOMP
RFSET
PGND
Figure 8-1. Full Analog Configuration
8.2.1.1 Design Requirements
For this design example, use the input parameters shown in Table 8-1.
Table 8-1. Design Example Specifications
PARAMETER
VIN, Input Voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
9
12
14
V
0.2
V
VIN(ripple), Input Ripple Voltage
26
VOUT, Output Voltage
1
V
VPP, Ouput Ripple Voltage
15
mV
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Table 8-1. Design Example Specifications (continued)
PARAMETER
TEST CONDITION
VOVER, Transient Response
Overshoot
MIN
ISTEP = 5 A at 1 A/μs
30
mV
VUNDER, Transient Response
Undershoot
ISTEP = 5 A at 1 A/μs
30
mV
10
A
IOUT, Output Current
TYP
MAX
UNIT
IOC, Over-Current Trip Point
16
A
FSW, Switching Frequency
1.2
MHz
tSS, Soft-start time
0.5
ms
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS542A50 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Output Voltage Calculation
The output voltage equals five times of VSET. To set VSET voltage, a resistor divider network is required from
SREF (1.2 V). Equation 2 shows the output voltage calculation. It is recommended to use R1 and R2 in the range
of 1 kΩ to 100 kΩ. For example, R1 equals 50 kΩ and R2 equals 10 kΩ for 1-V output voltage.
VOUT
5 u VSET
R2
u 1.2
VSET
R1 R2
R2
u 1.2
VOUT 5 u
R1 R2
(2)
8.2.1.2.3 Switching Frequency Selection
There is a trade off between higher and lower switching frequencies. Higher switching frequencies can produce
a smaller solution size using lower valued inductors and smaller output capacitors compared to a power supply
that switches at a lower frequency. However, the higher switching frequency causes extra switching losses,
which decreases efficiency and impacts thermal performance. In this design, a moderate switching frequency of
1.2 MHz that achieves both a small solution size and a high efficiency operation is selected. TPS542A50 offers
seven choices of switching frequency in Table 7-1. RFSET equals to 47.5 kΩ for 1.2-MHz switching frequency.
8.2.1.2.4 Inductor Selection
The inductor value is a compromise between having a good load step transient response, output ripple voltage,
and efficiency. A good practice is to select the inductor ripple current value between 15% to 50% of the
maximum output current. The output capacitor absorbs the inductor-ripple current. Therefore, selecting a high
inductor-ripple current impacts the selection of the output capacitor because the output capacitor must have
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a ripple-current rating equal to or greater than the inductor-ripple current. Using 35% target ripple current, the
required inductor size can be calculated as shown in Equation 3.
L
VOUT u VIN VOUT
1.0 V× 12 V-1.0 V
VIN u fSW u IOUT u 0.35
12 V×1.2 MHz u 10 A u 0.35
218 nH
(3)
A standard inductor value of 220 nH is selected.
8.2.1.2.5 Input Capacitor Selection
The TPS542A50 requires a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a value of
at least 1 μF of effective capacitance on the PVIN pin, relative to PGND. The power stage input decoupling
capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high switching
currents demanded when the high-side MOSFET switches on, while providing minimal input voltage ripple as a
result. This effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must
be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than
the maximum input current ripple to the device during full load. The input ripple current can be calculated by
Equation 4.
ICIN(rms)
IOUT(max) u
VOUT (VIN VOUT )
u
VIN
VIN
2.8 Amps
(4)
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are
shown in Equation 5. The input ripple is composed of a capacitive portion, VIN(RIPPLE_CAP), and a resistive
portion, VIN(RIPPLE_ESR).
CIN(min)
IOUT(max) u 1 D u D
VIN(RIPPLE _ CAP) u fSW
VIN(RIPPLE _ ESR)
ESRCIN(max)
IRIPPLE
IOUT(max)
6.4 PF
8.5 m:
2
where
x D is the duty cycle
(5)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with
at least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V
input ripple for VIN(RIPPLE_CAP), and 0.1-V input ripple for VIN(RIPPLE_ESR). UsingEquation 5, the minimum input
capacitance for this design is 6.4 µF, and the maximum ESR is 8.5 mΩ. In a real application, it is recommended
to use a combination of small capacitors such as 0.1 μF and larger value 10-μF or 22-μF ceramic capacitors in
parallel for the power stage.
8.2.1.2.6 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with
a voltage rating of 25 V or higher.
8.2.1.2.7 R-C Snubber and VIN Pin High-Frequency Bypass
Though it is possible to operate the TPS542A50 within absolute maximum ratings without voltage ringing
reduction techniques, some designs may require external components to further reduce ringing levels. This
example uses two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C
snubber between the SW area and GND.
28
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The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimize the
outboard parasitic inductances in the power stage, which store energy during the high-side MOSFET on-time,
and discharge once the high-side MOSFET is turned off. For this example two of 0.1-μF to 1-μF, 25-V, 0402sized high-frequency capacitors are used. The placement of these capacitors is critical to its effectiveness.
Additionally, an optional R-C snubber circuit is added to this example. To balance efficiency and spike levels,
a 220-pF capacitor and a 2-Ω resistor are chosen. In this example, a 0805-sized resistor is chosen, which is
rated for 0.125 W, nearly twice the estimated power dissipation. See the Seminar 900 Topic 2 - Snubber Circuits:
Theory, Design and Application application note for more information about snubber circuits.
8.2.1.2.8 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
affects three criteria:
•
•
•
Stability
Regulator response to a change in load current or load transient
Output voltage ripple
These three considerations are important when designing regulators that must operate where the electrical
conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these
three criteria.
8.2.1.2.9 Response to a Load Transient
The output capacitance must supply the load with the required current when current is not immediately provided
by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects
the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.
Use Equation 6 and Equation 7 to calculate the minimum output capacitance to meet the undershoot and
overshoot requirements. For this example, COUT(min_under) is 136 μF and 92 μF for COUT(min_over). In a real
application, the value of a ceramic capacitor varies significantly over temperature and the amount of DC bias
applied to the capacitor. It is recommended to check the capacitor datasheet and account for the capacitance
derating.
COUT(min_under) =
COUT(min_over) =
L ´ DILOAD(max)2
2 ´ DVLOAD(INSERT) ´ (VIN -VVOUT )
LOUT ´
+
DILOAD(max) ´ (1 - D ) ´ tSW
DVLOAD(INSERT)
(6)
2
(DILOAD(max) )
2 ´ DVLOAD(release) × VOUT
(7)
where
•
•
•
•
•
•
•
•
•
•
COUT(min_under) is the minimum output capacitance to meet the undershoot requirement
COUT(min_over)is the minimum output capacitance to meet the overshoot requirement
D is the duty cycle
L is the output inductance value (0.22 µH)
∆ILOAD(max) is the maximum transient step (5 A)
VOUT is the output voltage value (1 V)
tSW is the switching period (0.833 µs)
VIN is the minimum input voltage for the design (12 V)
∆VLOAD(insert) is the undershoot requirement (30 mV)
∆VLOAD(release) is the overshoot requirement (30 mV)
8.2.1.2.10 Pin-Strap Setting
For overcurrent protection at 16.5 A, 47.5 kΩ is chosen from Table 7-7. For 0.5-ms soft start and FCCM
operation, 47.5 kΩ is chosen from Table 7-5 and Table 7-6.
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For converter stability and selecting the compensation network, Table 7-3 provides four compensation choices.
First, the power stage double pole filter frequency needs to be known. For this example, the output capacitor
bank selects as 4x100-μF ceramic capacitors in 0805 size to account the capacitor de-rate factors. Next, the LC
filter frequency is calculated to 17 kHz. Finally, COMP3 becomes the best choice to select by using a 26.1-kΩ or
78.7-kΩ resistor on the COMP pin to GND.
8.2.1.3 Application Curves
VIN = 12 V
VIN = 12 V
VOUT = 1 V
fSW = 1.2 MHz
Figure 8-2. 450 μs Start-up by EN at 0-A Output
Current
VIN = 12 V
VOUT = 1 V
fSW = 1.2 MHz
Figure 8-3. Load Transient 5 A to 10 A to 5 A at 1
A/μs
VOUT = 1 V
fSW = 1.2 MHz
Figure 8-4. Bode Plot at 10-A Output Current
8.2.1.4 Typical Application Circuits
VIN
PVIN
10
3 x 10 µF
AVIN
0.1 µF
0.47 µF
10 k
4.7 µF
VREG
BOOT
0.1 µF
0.68 µH
SW
PGD
RSP
EN
RSN
VOUT
2 x 22 µF
5 x 100 µF
SYNC
SCL
FSEL
SDA
COMP
46.4 k
SREF
VSET
20 k
AGND
SS/PFM
ILIM
PGND
61.9 k
61.9 k
18.2 k
35.7 k
Figure 8-5. Typical Application Circuit for 1.8-V Output at 1.0 MHz
30
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VIN
PVIN
10
AVIN
0.1 µF
4 x 10 µF
10 k
0.47 µF
4.7 µF
0.1 µF
BOOT
VREG
1.5 µH
SW
VOUT
PGD
RSP
EN
RSN
220 µF
Optional: 4 x 100 µF
2 x 22 µF
SYNC
SCL
FSEL
SDA
COMP
28 k
SREF
SS/PFM
VSET
ILIM
20 k
AGND
61.9 k
PGND
61.9 k
26.1 k
26.1 k
Figure 8-6. Typical Application Circuit for 2.5-V Output at 0.8 MHz
VIN
PVIN
10
AVIN
0.1 µF
4 x 10 µF
10 k
0.47 µF
4.7 µF
0.1 µF
BOOT
VREG
1.5 µH
SW
PGD
RSP
EN
RSN
VOUT
2 x 22 µF
220 µF
Optional: 4 x 100 µF
SYNC
FSEL
SCL
COMP
SDA
16.5 k
SS/PFM
SREF
61.9 k
ILIM
VSET
20 k
AGND
PGND
61.9 k
26.1 k
26.1 k
Figure 8-7. Typical Application Circuit for 3.3-V Output at 0.8 MHz
VIN
4 x 10 µF
PVIN
10
AVIN
0.1 µF
10 k
0.47 µF
4.7 µF
VREG
BOOT
0.1 µF
2.2 µH
SW
PGD
RSP
EN
RSN
VOUT
2 x 22 µF
330 µF
SYNC
SCL
FSEL
SDA
COMP
10 k
49.9 k
SREF
SS/PFM
VSET
ILIM
AGND
PGND
47.5 k
61.9 k
26.1 k
18.2 k
Figure 8-8. Typical Application Circuit for 5-V Output at 0.6 MHz
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4 V and 18 V. This input supply
must be well regulated. Proper bypassing of input supplies (AVIN and PVIN) is critical for noise performance, as
is the PCB layout and grounding scheme. See the recommendations in Section 10.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
32
The PVIN pins are the power inputs to the main half bridge and AVIN is the power input to the controller.
Connect AVIN and PVIN together on the PCB. It is important that these pins are at the same voltage potential
because the controller feedforward block uses this voltage information in the modulator to increase transient
performance. For AVIN, it is best to use RC filter from PVIN such as 10-Ω and 100 nF.
To minimize the power loop inductance for the half bridge, place the bypassing capacitors as close as
possible to the PVIN pins on the converter. When using a multilayer PCB (more than two layers), the power
loop inductance is minimized by having the return path to the input capacitor small and directly underneath
the first layer as shown below. Loop inductance is reduced due to flux cancellation as the return current is
directly underneath and flowing in the opposite direction.
Place the bias capacitor for VREG pin as close as possible to the pin as shown below.
The resistor divider network for SREF and VSET needs to placed as close as possible to the pins. Limit the
high frequency noise source coupling onto these components.
RSP and RSN signals are best to route parallel to the load sense location. It is recommended to limit high
frequency noise source coupling onto these traces.
PGND thermal vias: It is recommended to add vias under and outside the IC of PGND plane as shown below.
AGND thermal vias: It is recommended to add at least two vias under the IC of AGND plane as shown below.
AGND plane can be routed as a separate island in an internal layer. AGND can connect as a net tied to
PGND between the two thermal grounds under the IC as shown below.
Total PCB area can be routed in 17 mm by 14 mm as shown below. See the Using the TPS542A50EVM-059
user's guide for more details.
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8/18
8/18
8/18
8/18
Total Area:
17mm x 14mm
PGND
8/18
8/18
8/18
8/18
8/18
PGND
PVIN
8/18
10.2 Layout Example
0805
8/18
0805
PVIN
0402
BOOT
PVIN
PVIN
PVIN
AVIN
EN
COMP
0402
FSEL
8/18
0402
0402
ILIM
0402
0402
8/18
8/18
8/18
AGND
0402
0402
Optional
MSEL
resistors
0402
AGND
0402
SS/PFM
SW
8/18
SCL
7mm x 7mm
VOUT
8/18
AGND
8/18
8/18
SDA
8/18
PGND
8/18
8/18
SYNC
8/18
8/18
8/18
PGND
8/18
8/18
PGND
8/18
0805 8/18
8/18
VREG
0805
8/18
0402
0805
0402
0402
AGND
8/18
8/18
0402
8/18
AGND
PGND
PGND
VREG
PGD
SREF
8/18
AGND
VSET
8/18
RSP
0805
8/18
8/18
RSN
PGND
Figure 10-1. Example PCB Layout
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TPS542A50
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SNVSBC0B – SEPTEMBER 2020 – REVISED OCTOBER 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Fusion Digital Power™ Designer Tool
Click here to download the Graphical User Interface (GUI) used to configure and monitor the TPS542A50 with
the Fusion Digital Power™ designer.
The Fusion Digital Power™ designer uses the PMBus protocol to communicate with the device over serial bus
by way of a TI USB adapter.
Some of the tasks you can perfrom with the GUI include:
• Turn on or off the power supply output, either through hardware control line or the PMBus OPERATION
command.
• Monitor real-time data. Items such as input voltage, output voltage, output current, temperature, and
warnings/faults are continuously monitored and displayed by the GUI.
Get more information about the software tool at www.ti.com/tool/FUSION_DIGITAL_POWER_DESIGNER.
11.1.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS542A50 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
Eco-mode™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
34
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TPS542A50
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SNVSBC0B – SEPTEMBER 2020 – REVISED OCTOBER 2021
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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SNVSBC0B – SEPTEMBER 2020 – REVISED OCTOBER 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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Product Folder Links: TPS542A50
PACKAGE OUTLINE
RJM0033A-C01
VQFN-HR - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
4.6
4.4
A
B
PIN 1 INDEX AREA
4.1
3.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
2X 3.5
0.95 0.1
21X 0.5
0.08 C
7X 0.175 0.05
PKG
(2X 0.375)
(0.127) TYP
9
8
16
4X (0.2)
33
32
0.388 0.1
5X 1
3.5
29
25
2.05 0.1
26
27
PKG
31
30
28
8X 0.7 0.1
PIN 1 ID
17
1
1.906
1.2
2X 1.5
0.9
0.3
2X 0.6
0.4
0.3
0.000
24X
24X
1.225
(2X 0.375)
24
0.3
0.2
0.1
0.05
C A B
4228229/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RJM0033A-C01
VQFN-HR - 1 mm max height
20X (0.55)
4X (0.2)
(0.9)
4X (0.55)
(0.3)
PLASTIC QUAD FLATPACK - NO LEAD
7X (0.175)
24
17
(1.925)
4X (0.575)
1
(0.95)
24X (0.25)
27
26
28
8X (0.7)
21X
(0.5)
25
(2.05)
29
PKG
31
30
0.000
( 0.2) VIA
(0.388)
5X (1)
33
32
(R0.05) TYP
8
(1.925)
9
(1.906)
2X (1.5)
(1.2)
2X (0.6)
0.000
PKG
(1.225)
(2.175)
16
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228229/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RJM0033A-C01
VQFN-HR - 1 mm max height
2X (2)
4X (0.55)
(0.9)
(0.3)
PLASTIC QUAD FLATPACK - NO LEAD
20X (0.55)
4X (0.2)
2X (0.25)
24
17
(1.925)
4X (0.575)
2X (1.75)
1
7X (0.175)
2X (0.237)
4X (0.37)
4X (0.83)
28
27
26
3X (0.56)
3X (1)
2X (0.515)
29
25
0.000
PKG
31
30
(0.7)
2X (0.035)
EXPOSED
METAL
2X (0.515)
(0.388)
17X
(0.5)
8
4X (0.63)
(1.925)
2X (1.5)
(1.2)
2X (0.6)
0.000
PKG
2X (0.94)
2X (2)
(2.175)
(1.906)
16
9
(R0.05) TYP
2X (1.51)
2X (1.744)
2X (0.965)
33
32
SOLDER PASTE EXAMPLE
BASED ON 0.1 - 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1 & 8: 95%; PAD 25: 63%; PADS 26-28: 80%; PADS 29, 30, 32 & 33: 90%
SCALE:25X
4228229/A 11/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS542A50RJMR
ACTIVE
VQFN-HR
RJM
33
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
542A50
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
