TPS5430EVM-173F

TPS5430, TPS5431 SLVS632J – JANUARY 2006 – REVISED JULY 2022 TPS543x 3-A, Wide Input Range, Step-Down Converter 1 Features 3 Description • The TPS543x is a high-output-current PWM converter that integrates a low-resistance, high-side N-channel MOSFET. Included on the substrate with the listed features are a high-performance voltage error amplifier that provides tight voltage regulation accuracy under transient conditions; an undervoltagelockout circuit to prevent start-up until the input voltage reaches 5.5 V; an internally set slow-start circuit to limit inrush currents; and a voltage feedforward circuit to improve the transient response. Using the ENA pin, shutdown supply current is reduced to 18 μA typically. Other features include an active-high enable, overcurrent limiting, overvoltage protection and thermal shutdown. To reduce design complexity and external component count, the TPS543x feedback loop is internally compensated. The TPS5431 is intended to operate from power rails up to 23 V. The TPS5430 regulates a wide variety of power sources including 24 V bus. • • • • • • • • 2 Applications • • • • Consumer: set-top box, DVD, LCD displays Industrial and car audio power supplies Battery chargers, high-power LED supply 12-V and 24-V distributed power systems The TPS543x device is available in a thermally enhanced, easy to use 8-pin SOIC PowerPAD™ package. TI provides evaluation modules and the Designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. Device Information PART NUMBER TPS5430 (1) PACKAGE(1) INPUT VOLTAGE HSOP (8) TPS5431 5.5 V to 36 V 5.5 V to 23 V For all available packages, see the orderable addendum at the end of the datasheet. Efficiency vs Output Current Simplified Schematic 100 VIN PH VIN VOUT 95 TPS5430/31 NC BOOT NC ENA VSENSE GND 90 Efficiency − % • • Wide input voltage range: – TPS5430: 5.5 V to 36 V – TPS5431: 5.5 V to 23 V Up to 3-A continuous (4-A peak) output current High efficiency up to 95% enabled by 110-mΩ integrated MOSFET switch Wide output voltage range: adjustable down to 1.22 V with 1.5% initial accuracy Internal compensation minimizes external parts count Fixed 500-kHz switching frequency for small filter size Improved line regulation and transient response by input voltage feedforward System protected by overcurrent limiting, overvoltage protection, and thermal shutdown –40°C to 125°C operating junction temperature range Available in small thermally enhanced 8-pin SO PowerPAD™ package Create a custom design using the TPS5430 with the WEBENCH® Power Designer 85 80 75 70 VI = 12 V VO = 5 V fs = 500 kHz o TA = 25 C 65 60 55 50 0 0.5 2 1 1.5 2.5 3 IO - Output Current - A 3.5 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Typical Characteristics................................................ 7 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Feature Description...................................................10 7.4 Device Functional Modes..........................................11 8 Application and Implementation.................................. 12 8.1 Application Information............................................. 12 8.2 Typical Applications.................................................. 13 9 Power Supply Recommendations................................25 10 Layout...........................................................................25 10.1 Layout Guidelines................................................... 25 10.2 Layout Example...................................................... 26 11 Device and Documentation Support..........................27 11.1 Device Support........................................................27 11.2 Receiving Notification of Documentation Updates.. 27 11.3 Support Resources................................................. 27 11.4 Trademarks............................................................. 27 11.5 Electrostatic Discharge Caution.............................. 27 11.6 Glossary.................................................................. 27 12 Mechanical, Packaging, and Orderable Information.................................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (April 2017) to Revision J (July 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 Changes from Revision H (April 2016) to Revision I (March 2017) Page • Added WEBENCH® Model ................................................................................................................................1 • Changed Section 6.1 PH (transient < 10 ns) spec MIN voltage from "–1.2" to "–4"........................................... 4 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 5 Pin Configuration and Functions BOOT 1 NC 2 8 PH 7 VIN PowerPAD NC 3 6 GND VSENSE 4 5 ENA Figure 5-1. DDA Package 8-Pin SOIC with Thermal Pad Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. BOOT 1 O Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin. Not connected internally. NC 2, 3 — VSENSE 4 I Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 I On/off control. Below 0.5 V, the device stops switching. Float the pin to enable. GND 6 — Ground. Connect to PowerPAD. VIN 7 — Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic capacitor. PH 8 PowerPAD I — Source of the high side power MOSFET. Connected to external inductor and diode. GND pin must be connected to the exposed pad for proper operation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 3 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) TPS5430 VI Input voltage range TPS5431 MIN MAX VIN –0.3 40(3) PH (steady-state) –0.6 40(3) VIN –0.3 25 PH (steady-state) –0.6 25 ENA –0.3 7 BOOT-PH –0.3 10 VSENSE –0.3 3 PH (transient < 10 ns) UNIT V –4 IO Source current PH Ilkg Leakage current PH 10 μA TJ Operating virtual junction temperature range –40 150 °C Tstg Storage temperature range –65 150 °C (1) (2) (3) Internally Limited Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) Charged-device model (CDM), per JEDEC specification JESD22C101(2) UNIT ±2000 V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions 4 VIN Input voltage range TJ Operating junction temperature MIN MAX TPS5430 5.5 36 TPS5431 5.5 23 –40 125 Submit Document Feedback UNIT V °C Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 6.4 Thermal Information TPS5430 TPS5431 THERMAL METRIC(1) (2) (3) DDA UNIT 8 PINS RθJA Junction-to-ambient thermal resistance (2-layer custom board) (4) RθJA Junction-to-ambient thermal resistance (4-layer custom board) (5) RθJA Junction-to-ambient thermal resistance (standard board) ψJT Junction-to-top characterization parameter 4.9 ψJB Junction-to-board characterization parameter 20.7 RθJC(top) Junction-to-case(top) thermal resistance 46.4 RθJC(bottom) Junction-to-case(bottom) thermal resistance 0.8 RθJB Junction-to-board thermal resistance 20.8 (1) (2) (3) 33 26 42.3 °C/W (4) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report. Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more information. Test boards conditions: (5) a. 3 in x 3 in, 2 layers, thickness: 0.062 inch. b. 2 oz. copper traces located on the top and bottom of the PCB. c. 6 thermal vias in the PowerPAD area under the device package. Test board conditions: a. b. c. d. 3 in x 3 in, 4 layers, thickness: 0.062 inch. 2 oz. copper traces located on the top and bottom of the PCB. 2 oz. copper ground planes on the 2 internal layers. 6 thermal vias in the PowerPAD area under the device package. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 5 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 6.5 Electrical Characteristics TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 4.4 mA 18 50 μA Start threshold voltage, UVLO 5.3 5.5 Hysteresis voltage, UVLO 330 SUPPLY VOLTAGE (VIN PIN) IQ Quiescent current VSENSE = 2 V, Not switching, PH pin open Shutdown, ENA = 0 V UNDERVOLTAGE LOCK OUT (UVLO) V mV VOLTAGE REFERENCE Voltage reference accuracy TJ = 25°C 1.202 1.221 1.239 IO = 0 A – 3 A 1.196 1.221 1.245 V OSCILLATOR Internally set free-running frequency 400 Minimum controllable on time Maximum duty cycle 87% 500 600 kHz 150 200 ns 1.3 V 89% ENABLE (ENA PIN) Start threshold voltage, ENA Stop threshold voltage, ENA 0.5 Hysteresis voltage, ENA V 450 Internal slow-start time (0~100%) mV 6.6 8 10 ms 4 5 6 A 13 16 20 ms 135 162 CURRENT LIMIT Current limit Current limit hiccup time THERMAL SHUTDOWN Thermal shutdown trip point Thermal shutdown hysteresis °C 14 OUTPUT MOSFET rDS(on) 6 High-side power MOSFET switch VIN = 5.5 V 150 110 Submit Document Feedback 230 mΩ Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 6.6 Typical Characteristics 530 3.5 VI = 12 V I Q−Quiescent Current −mA f − Oscillator Frequency − kHz 520 510 500 490 480 3.25 3 2.75 470 460 −50 −25 0 25 50 75 100 2.5 −50 125 −25 Figure 6-1. Oscillator Frequency vs. Junction Temperature T J = 125°C 15 T J = 27°C T J = –40°C 10 5 0 5 10 15 20 25 30 35 100 125 1.220 1.215 1.210 -50 40 Figure 6-3. Shutdown Quiescent Current vs. Input Voltage -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 Figure 6-4. Voltage Reference vs. Junction Temperature 9 180 TSS − Internal Slow Start Time − ms V I = 12 V 160 150 140 130 120 110 r DS(on) −On Resistance −mΩ 75 1.225 V I −Input V oltage −V 170 50 1.230 ENA = 0 V 20 25 Figure 6-2. Non-Switching Quiescent Current vs. Junction Temperature VREF - Voltage Reference - V I SD −Shutdown Current −µ A 25 0 T J −Junction T emperature − °C T − Junction Temperature − °C 8.5 8 7.5 100 7 −50 90 80 −50 −25 0 25 50 75 100 T J −Junction Temperature − °C 125 Figure 6-5. On Resistance vs. Junction Temperature −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 6-6. Internal Slow Start Time vs. Junction Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 7 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8 170 7.75 Minimum Duty Ratio - % Minimum Controllable On Time − ns 180 160 150 140 7.25 130 120 −50 7 -50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 6-7. Minimum Controllable On Time vs. Junction Temperature 8 7.50 -25 50 0 25 75 100 TJ - Junction Temperature - °C 125 Figure 6-8. Minimum Controllable Duty Ratio vs. Junction Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 7 Detailed Description 7.1 Overview The TPS543x is a 3-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. The TPS5431 is intended to operate from power rails up to 23 V and the TPS5430 up to 36 V. These devices implement constant-frequency voltage-mode control with voltage feed forward for improved line regulation and line transient response. Internal compensation reduces design complexity and external component count. The integrated 110-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering 3-A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied by a bootstrap capacitor connected from the BOOT to PH pins. The TPS543x reduces the external component count by integrating the bootstrap recharge diode. The TPS543x has a default input start-up voltage of 5.3 V typical. The ENA pin can be used to disable the TPS543x reducing the supply current to 18 µA. An internal pullup current source enables operation when the ENA pin is floating. The TPS543x includes an internal slow-start circuit that slows the output rise time during start up to reduce in rush current and output voltage overshoot. The minimum output voltage is the internal 1.221-V feedback reference. Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than 112.5% of the desired output voltage. Internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side MOSFET. For continuous overcurrent fault conditions the TPS543x will enter hiccup mode overcurrent limiting. Thermal protection protects the device from overheating. 7.2 Functional Block Diagram VIN VIN 1.221 V Bandgap Reference UVLO VREF SHDN Slow Start Boot Regulator BOOT HICCUP 5 µA ENA ENABLE SHDN SHDN VSENSE Z1 Thermal Protection NC SHDN VIN Ramp Generator NC SHDN VSENSE Z2 Feed Forward Gain = 25 PWM Comparator SHDN GND POWERPAD Error Amplifier SHDN HICCUP Overcurrent Protection Oscillator SHDN Gate Drive Control OVP 112.5% VREF Gate Driver SHDN BOOT PH VOUT Copyright © Texas Instruments Incorporated Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 9 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 7.3 Feature Description 7.3.1 Oscillator Frequency The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching frequency allows less output inductance for the same output ripple requirement resulting in a smaller output inductor. 7.3.2 Voltage Reference The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of 1.221 V at room temperature. 7.3.3 Enable (ENA) and Internal Slow Start The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The quiescent current of the TPS543x in shutdown mode is typically 18 μA. The ENA pin has an internal pull-up current source, allowing the user to float the ENA pin. If an application requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its final value, linearly. The internal slow start time is 8 ms typically. 7.3.4 Undervoltage Lockout (UVLO) The TPS543x incorporate an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV. 7.3.5 Boost Capacitor (BOOT) Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable values over temperature. 7.3.6 Output Feedback (VSENSE) and Internal Compensation The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage reference 1.221 V. The TPS543x implements internal compensation to simplify the regulator design. Since the TPS543x uses voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover frequency and a high phase margin for good stability. See the Internal Compensation Network in the applications section for more details. 7.3.7 Voltage Feed-Forward The internal voltage feed-forward provides a constant dc power stage gain despite any variations with the input voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constant at the feed forward gain, i.e. Feed Forward Gain + 10 VIN Ramp pk*pk Submit Document Feedback (1) Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 The typical feed forward gain of TPS543x is 25. 7.3.8 Pulse-Width-Modulation (PWM) Control The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle. Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET. 7.3.9 Overcurrent Limiting Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches. Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current limiting. Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup mode overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the highside MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under control of the slow start circuit. 7.3.10 Overvoltage Protection The TPS543x has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side MOSFET will be enabled again. 7.3.11 Thermal Shutdown The TPS543x protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction temperature drops 14°C below the thermal shutdown trip point. 7.4 Device Functional Modes 7.4.1 Operation near Minimum Input Voltage The TPS543x is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO threshold is 5.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage the device will not switch. If EN is floating or externally pulled up to greater up than 1.3 V, when V(VIN) passes the UVLO threshold the TPS543x will become active. Switching is enabled and the slow-start sequence is initiated. The TPS543x starts linearly ramping up the internal reference voltage from 0 V to its final value over the internal slow-start time period. 7.4.2 Operation with ENA control The enable start threshold voltage is 1.3 V max. With ENA held below the 0.5 V minimum stop threshold voltage the TPS543x is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent current is reduced in this state. If the ENA voltage is increased above the max start threshold while V(VIN) is above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start sequence is initiated. The TPS543x starts linearly ramping up the internal reference voltage from 0 V to its final value over the internal slow-start time period. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 11 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The TPS543x is a 3-A, step down regulator with an integrated high side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 3 A. Example applications are: High Density Point-of-Load Regulators for Set-top Box, DVD, LCD and Plasma Displays, High Power LED Supply, Car Audio, Battery Chargers, and other 12-V and 24-V Distributed Power Systems. Use the following design procedure to select component values for the TPS543x. This procedure illustrates the design of a high frequency switching regulator. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. To begin the design process a few parameters must be decided upon. The designer needs to know the following: • Input voltage range • Output voltage • Input ripple voltage • Output ripple voltage • Output current rating • Operating frequency 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2 Typical Applications 8.2.1 12-V Input to 5.0-V Output Figure 8-1 shows the schematic for a typical TPS5430 application. The TPS5430 can provide up to 3 A output current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™ underneath the device must be soldered down to the printed-circuit board. U1 TPS5430DDA 10.8 - 19.8 V 7 VIN 5 EN 2 C1 10 mF 3 6 VIN BOOT ENA NC PH NC VSNS GND C2 0.01 mF L1 15 mH 5V 1 8 4 D1 B340A + C3 220 mF VOUT R1 10 kW PwPd 9 R2 3.24 kW Copyright © Texas Instruments Incorporated Figure 8-1. Application Circuit, 12 V Input to 5.0 V Output 8.2.1.1 Design Requirements For this design example, use the following as the input parameters: (1) DESIGN PARAMETER(1) EXAMPLE VALUE Input voltage range 10.8 V to 19.8 V Output voltage 5V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 3A Operating frequency 500 kHz As an additional constraint, the design is set up to be small size and low component height. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 13 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.1.2 Detailed Design Procedure The following design procedure can be used to select component values for the TPS5430. This section presents a simplified discussion of the design process. 8.2.1.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TPS5430 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.1.2.2 Switching Frequency The switching frequency for the TPS5430 is internally set to 500 kHz. It is not possible to adjust the switching frequency. 8.2.1.2.3 Input Capacitors The TPS5430 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The recommended value for the decoupling capacitor, C1, is 10 μF. A high quality ceramic type X5R or X7R is required. For some applications, a smaller value decoupling capacitor may be used, so long as the input voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage, including ripple. This input ripple voltage can be approximated by Equation 2 : DVIN + I OUT(MAX) C BULK 0.25 ƒsw ǒ ) I OUT(MAX) Ǔ ESR MAX (2) Where IOUT(MAX) is the maximum load current, f SW is the switching frequency, CIN is the input capacitor value and ESRMAX is the maximum series resistance of the input capacitor. The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be approximated by Equation 3 : I I CIN + OUT(MAX) 2 (3) In this case the input ripple voltage would be 156 mV and the RMS ripple current would be 1.5 A. The maximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is rated for 25 V and the ripple current capacity is greater than 3 A, providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded under any circumstance. Additionally some bulk capacitance may be needed, especially if the TPS5430 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage is acceptable. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.1.2.4 Output Filter Components Two components need to be selected for the output filter, L1 and C2. Since the TPS5430 is an internally compensated device, a limited range of filter component types and values can be supported. 8.2.1.2.4.1 Inductor Selection To calculate the minimum value of the output inductor, use Equation 4: V L MIN + ǒ V * V OUT(MAX) IN(MAX) OUT V K I F IN(max) IND OUT SW Ǔ (4) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. Three things need to be considered when determining the amount of ripple current in the inductor: the peak to peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using the TPS5430, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when paired with the proper output capacitor, the peak switch current will be well below the current limit set point and relatively low load currents can be sourced before discontinuous operation. For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 12.5 μH. The next highest standard value is 15 μH, which is used in this design. For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 5: I L(RMS) + Ǹ 1 I2 ) OUT(MAX) 12 ǒ V V OUT ǒVIN(MAX) * VOUTǓ L IN(MAX) OUT F SW 0.8 Ǔ 2 (5) and the peak inductor current can be determined with Equation 6: V I L(PK) + I OUT(MAX) ) OUT 1.6 ǒVIN(MAX) * VOUTǓ V IN(MAX) L OUT F SW (6) For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen inductor is a Sumida CDRH104R-150 15 μH. It has a saturation current rating of 3.4 A and a RMS current rating of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was chosen because of its low profile component height. In general, inductor values for use with the TPS5430 are in the range of 10 μH to 100 μH. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 15 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.1.2.4.2 Capacitor Selection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the design of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range 3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design example, it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHz and also below the ESR zero of the output capacitor. Under these conditions the closed loop crossover frequency is related to the LC corner frequency by: f CO + f LC 2 85 VOUT (7) And the desired output capacitor value for the output filter to: C OUT + 1 3357 L OUT f CO V OUT (8) For a desired crossover of 18 kHz and a 15 μH inductor, the calculated value for the output capacitor is 220 μF. The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR should be: ESR MAX + 2p 1 C OUT f CO (9) The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter. Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output ripple voltage: VPP (MAX) = ESRMAX x VOUT x ( VIN(MAX) - VOUT ) NC x VIN(MAX) x LOUT x FSW (10) where • • • ΔVPP is the desired peak-to-peak output ripple. NC is the number of parallel output capacitors. FSW is the switching frequency. For this design example, a single 220 μF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 mΩ and a ripple current rating of 3 A. An additional small 0.1 μF ceramic bypass capacitor may also used, but is not included in this design. The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54 kHz. The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the output capacitor is given by Equation 11: 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 ICOUT(RMS) + 1 Ǹ12 ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ ȧVIN(MAX) LOUT FSW NCȧ Ȣ Ȥ (11) where • • NC is the number of output capacitors in parallel. FSW is the switching frequency. Other capacitor types can be used with the TPS5430, depending on the needs of the application. 8.2.1.2.5 Output Voltage Set-Point The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin. Calculate the R2 resistor value for the output voltage of 5 V using Equation 12: R2 + R1 V OUT 1.221 * 1.221 (12) For any TPS5430 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ. 8.2.1.2.6 BOOT Capacitor The BOOT capacitor should be 0.01 μF. 8.2.1.2.7 Catch Diode The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater than IOUT(MAX) plus on half the peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V. 8.2.1.2.8 Advanced Information 8.2.1.2.8.1 Output Voltage Limitations Due to the internal design of the TPS543x, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by: V OUTMAX + 0.87 ǒǒVINMIN * I OMAX Ǔ Ǔ ǒ 0.230 ) VD * I OMAX Ǔ RL * VD (13) where • • • • VINMIN = minimum input voltage IOMAX = maximum load current VD = catch diode forward voltage. RL= output inductor series resistance. This equation assumes maximum on resistance for the internal high side FET. The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by: V OUTMIN + 0.12 ǒǒVINMAX * I OMIN Ǔ Ǔ ǒ 0.110 ) VD * I OMIN Ǔ RL * VD (14) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 17 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 where • • • • VINMAX = maximum input voltage IOMIN = minimum load current VD = catch diode forward voltage. RL= output inductor series resistance. 8.2.1.2.8.2 Internal Compensation Network The design equations given in the example circuit can be used to generate circuits using the TPS543x. These designs are based on certain assumptions and will tend to always select output capacitors within a limited range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the TPS543x. Equation 15 gives the nominal frequency response of the internal voltage-mode type III compensation network: H(s) + ǒ1 ) 2p Ǔ ǒ1 ) 2p s Fz1 Ǔ s Fz2 ǒ2p sFp0Ǔ ǒ1 ) 2p sFp1Ǔ ǒ1 ) 2p sFp2Ǔ ǒ1 ) 2p sFp3Ǔ (15) where • • • fp0 = 2165 Hz, fz1 = 2170 Hz, fz2 = 2590 Hz fp1 = 24 kHz, fp2 = 54 kHz, fp3 = 440 kHz fp3 represents the non-ideal parasitics effect. Using this information along with the desired output voltage, feed forward gain and output filter characteristics, the closed loop transfer function can be derived. 8.2.1.2.8.3 Thermal Calculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working at light loads in the discontinuous conduction mode. Conduction Loss: Pcon = IOUT 2 x Rds(on) x VOUT/VIN Switching Loss: Psw = VIN x IOUT x 0.01 Quiescent Current Loss: Pq = VIN x 0.01 Total Loss: Ptot = Pcon + Psw + Pq Given TA => Estimated Junction Temperature: TJ = TA + Rth x Ptot Given TJMAX = 125°C => Estimated Maximum Ambient Temperature: TAMAX = TJMAX – Rth x Ptot 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.1.3 Application Curves The performance graphs (Figure 8-2 through Figure 8-8) are applicable to the circuit in Figure 8-1. Ta= 25 °C. unless otherwise specified. 0.3 100 VI = 10.8 V 95 0.2 VI = 12 V Output Regulation - % Efficiency - % VI = 15 V 90 VI = 18 V 85 VI = 19.8 V 80 0.1 0 -0.1 -0.2 -0.3 75 0 0.5 1 1.5 2 2.5 IO - Output Current - A 3 3.5 Figure 8-2. Efficiency vs. Output Current 0 0.5 1 2 1.5 2.5 3 IO - Output Current - A Figure 8-3. Output Regulation % vs. Output Current 0.1 VIN = 100 mV/Div (AC Coupled) 0.08 0.06 Input Regulation - % 0.04 IO = 3 A IO = 1.5 A 0.02 0 PH = 5 V/Div -0.02 -0.04 IO = 0 A -0.06 -0.08 -0.1 10.8 13.8 16.8 VI - Input Voltage - V t -Time - 500 ns/Div 19.8 Figure 8-4. Input Regulation % vs. Input Voltage Figure 8-5. Input Voltage Ripple and PH Node, IO = 3 A. VOUT = 20 mV/Div (AC Coupled) VOUT = 50 mV/Div (AC Coupled) PH = 5 V/Div IOUT = 1 A /Div t - Time = 200 μs/Div t - Time = 500 ns/Div Figure 8-6. Output Voltage Ripple and PH Node, IO =3A Figure 8-7. Transient Response, IO Step 0.75 to 2.25 A. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 19 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 VIN = 5 V/Div VOUT = 2 V/Div t - Time = 2 ms/Div Figure 8-8. Startup Waveform, VIN and VOUT. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.2 Wide Input Voltage Ranges with TPS5430 Figure 8-9 shows an application circuit using the wide input voltage range of the TPS5430. 10-35 V VIN C1 4.7 mF ENA C4 4.7 mF U1 TPS5430DDA VIN BOOT ENA PH NC NC VSNS GND PwPd L1 22 mH C2 0.01 mF 5V VOUT D1 B340A + C3 220 mF C3 = Sanyo POSCAP 10TP220M R1 10 kW R2 3.24 kW Copyright © Texas Instruments Incorporated Figure 8-9. 10 V– 35 V Input to 5 V Output Application Circuit 8.2.2.1 Design Requirements For this design example, use the following as the input parameters. This circuit is also designed with a larger value output inductor and a lower closed loop crossover frequency. DESIGN PARAMETER EXAMPLE VALUE Input voltage range 10 V to 35 V Output voltage 5V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 3A Operating frequency 500 kHz 8.2.2.2 Detailed Design Procedure The design procedure is similar to what is given for the design example in Section 8.2.1.2. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 21 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.2.3 Wide Input Voltage Ranges with TPS5431 Figure 8-10 shows an application circuit using the wide input voltage range of the TPS5431. 9-21 V VIN ENA C1 U1 TPS5431DDA VIN BOOT ENA PH NC NC VSNS GND PwPd L1 18 mH C2 0.01 mF 5V VOUT D1 B340A + C3 220 mF C3 = Sanyo POSCAP 10TP220M R1 10 kW R2 3.24 kW Copyright © Texas Instruments Incorporated Figure 8-10. 9 V – 21 V Input to 5 V Output Application Circuit 8.2.2.3.1 Design Requirements For this design example, use the following as the input parameters. This circuit is also designed with a larger value output inductor and a lower closed loop crossover frequency. DESIGN PARAMETER EXAMPLE VALUE Input voltage range 9 V to 21 V Output voltage 5V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 3A Operating frequency 500 kHz 8.2.2.3.2 Detailed Design Procedure The design procedure is similar to what is given for the design example in Section 8.2.1.2. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.3 Circuit Using Ceramic Output Filter Capacitors Figure 8-11 shows an application circuit using all ceramic capacitors for the input and output filters. U1 TPS5430DDA VIN 10-24 V VIN C1 4.7 mF EN 7 VIN 1 BOOT 5 ENA 2 8 PH NC 3 4 NC VSNS 6 GND PwPd 9 L1 15 mH C2 0.01 mF 3.3 V VOUT C3 100 mF D1 MRBS340 R1 10 kW C7 0.1 mF C4 150 pF R3 549 W R2 5.9 kW C6 1500 pF Copyright © Texas Instruments Incorporated Figure 8-11. Ceramic Output Filter Capacitors Circuit 8.2.3.1 Design Requirements For this design example, use the following as the input parameters. This circuit is also designed with a ceramic output filter capacitor. DESIGN PARAMETER EXAMPLE VALUE Input voltage range 10 V to 24 V Output voltage 3.3 V Input ripple voltage 300 mV Output current rating 3A Operating frequency 500 kHz 8.2.3.2 Detailed Design Procedure The design procedure is similar to what is given for the design example in Section 8.2.1.2, except for the selection of the output filter capacitor values and the design of the additional compensation components required to stabilize the circuit. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 23 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 8.2.3.2.1 Output Filter Component Selection Using Equation 11, the minimum inductor value is 12 μH. A value of 15 μH is chosen for this design. When using ceramic output filer capacitors, the recommended LC resonant frequency should be no more than 7 kHz. Since the output inductor is already selected at 15 μH, this limits the minimum output capacitor value to: CO (MIN) ³ 1 2 (2p x 7000) x LO (16) The minimum capacitor value is calculated to be 34 μF. For this circuit a larger value of capacitor yields better transient response. A single 100 μF output capacitor is used for C3. It is important to note that the actual capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to 3.3 V, minimizing this effect. 8.2.3.2.2 External Compensation Network When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this circuit, the external components are R3, C4, C6, and C7. To determine the value of these components, first calculate the LC resonant frequency of the output filter: FLC = 1 2p Ö LO x CO (EFF) (17) For this example the effective resonant frequency is calculated as 4109 Hz The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole and zero locations are given by the following equations: Fp1 = 500000 x VO FLC (18) Fz1 = 0.7 x FLC (19) Fz2 = 2.5 x FLC (20) The final pole is located at a frequency too high to be of concern. The second zero, fz2 as defined by Equation 20 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower. Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3 V output voltage as calculated using Equation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 401 Hz, Fz1 = 2876 Hz and Fz2 = 10.3 kHz, the values of R3, C6 and C7 are determined using Equation 21, Equation 22, and Equation 23: C7 = 1 2p x Fp1 x (R1 || R2) (21) R3 = 1 2p x Fz1 x C7 (22) C6 = 1 2p x Fz2 x R1 (23) For this design, using the closest standard values, C7 is 0.1 μF, R3 is 549 Ω, and C6 is 1500 pF. C4 is added to improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole frequency, so it should be small in relationship to C6. C4 should be less the 1/10 the value of C6. For this example, 150 pF works well. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 For additional information on external compensation of the TPS5430, TPS5431 or other wide voltage range devices, see the Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors application report. 9 Power Supply Recommendations The TPS5430 is designed to operate from an input voltage supply range between 5.5 V and 36 V. The TPS5431 is designed to operate from an input voltage supply range between 5.5 V and 23 V. This input supply should remain within the input voltage supply range. If the input supply is located more than a few inches from the TPS543x converter bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice. 10 Layout 10.1 Layout Guidelines Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the TPS543x ground pin. The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 μF ceramic with a X5R or X7R dielectric. There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by connecting it to the ground area under the device as shown below. The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placements and connections shown work well, but other connection routings may also be effective. Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the loop formed by the PH pin, Lout, Cout and GND as small as is practical. Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a trace under the output capacitor is not desired. If using the grounding scheme shown in Figure 10-1, use a via connection to a different layer to route to the ENA pin. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 25 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 10.2 Layout Example PH BOOT CAPACITOR OUTPUT INDUCTOR RESISTOR DIVIDER VOUT BOOT PH NC VIN NC GND VSENSE ENA OUTPUT FILTER CAPACITOR Route feedback trace under output filter capacitor or on other layer CATCH DIODE INPUT INPUT BYPASS BULK CAPACITOR FILTER Vin TOPSIDE GROUND AREA VIA to Ground Plane Signal VIA Figure 10-1. Design Layout 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support 11.1.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TPS5430 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 27 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 PACKAGE OUTLINE DDA0008J PowerPADTM SOIC - 1.7 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.2 TYP 5.8 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 1.27 8 1 2X 3.81 5.0 4.8 NOTE 3 4 5 8X B 4.0 3.8 NOTE 4 0.51 0.31 0.1 C A 1.7 MAX B 0.25 TYP 0.10 SEE DETAIL A 5 4 EXPOSED THERMAL PAD 0.25 GAGE PLANE 3.1 2.5 8 1 0 -8 0.15 0.00 1.27 0.40 DETAIL A 2.6 2.0 TYPICAL 4221637/B 03/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012, variation BA. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 29 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 EXAMPLE BOARD LAYOUT DDA0008J PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.95) NOTE 9 SOLDER MASK DEFINED PAD (2.6) SOLDER MASK OPENING SEE DETAILS 8X (1.55) 1 8 8X (0.6) SYMM (1.3) TYP (3.1) SOLDER MASK OPENING (4.9) NOTE 9 6X (1.27) 5 4 ( 0.2) TYP VIA METAL COVERED BY SOLDER MASK SYMM (1.3) TYP (5.4) LAND PATTERN EXAMPLE SCALE:10X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4221637/B 03/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 TPS5430, TPS5431 www.ti.com SLVS632J – JANUARY 2006 – REVISED JULY 2022 EXAMPLE STENCIL DESIGN DDA0008J PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.6) BASED ON 0.125 THICK STENCIL 8X (1.55) 1 8 8X (0.6) (3.1) BASED ON 0.127 THICK STENCIL SYMM 6X (1.27) 5 4 METAL COVERED BY SOLDER MASK SYMM (5.4) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.150 0.175 2.91 X 3.47 2.6 X 3.1 (SHOWN) 2.37 X 2.83 2.20 X 2.62 4221637/B 03/2016 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS5430 TPS5431 31 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS5430DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5430 Samples TPS5430DDAG4 ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5430 Samples TPS5430DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5430 Samples TPS5430DDARG4 ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5430 Samples TPS5431DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5431 Samples TPS5431DDAG4 ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5431 Samples TPS5431DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5431 Samples TPS5431DDARG4 ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5431 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of