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TPS54327DDAR

TPS54327DDAR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC8_150MIL_EP

  • 描述:

    4.5V 至 18V 输入,3A 同步降压转换器

  • 数据手册
  • 价格&库存
TPS54327DDAR 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 TPS54327 3-A Output Single Synchronous Step-Down Switcher With Integrated FET 1 Features 3 Description • The TPS54327 device is an adaptive on-time DCAP2™ mode synchronous buck converter. TheTPS54327 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54327 uses the D-CAP2 mode control which provides a fast transient response with no external compensation components. The TPS54327 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SPCAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.76 V and 7 V. The device also features an adjustable soft start time. The TPS54327 is available in the 8-pin DDA package and 10-pin DRC, and is designed to operate from –40°C to 85°C. 1 • • • • • • • • • • D-CAP2™ Mode Enables Fast Transient Response Low-Output Ripple and Allows Ceramic Output Capacitor Wide VIN Input Voltage Range: 4.5 V to 18 V Output Voltage Range: 0.76 V to 7 V Highly Efficient Integrated FETs Optimized for Lower Duty Cycle Applications – 100 mΩ (High-Side) and 70 mΩ (Low-Side) High Efficiency, Less Than 10 μA at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start Prebiased Soft Start 700-kHz Switching Frequency (fSW) Cycle-By-Cycle Overcurrent Limit 2 Applications • Wide Range of Applications for Low Voltage System – Digital TV Power Supply – High Definition Blu-ray Disc™ Players – Networking Home Terminal – Digital Set Top Box (STB) Simplified Schematic Device Information(1) PART NUMBER TPS54327 PACKAGE BODY SIZE (NOM) HSOP (8) 4.89 mm × 3.90 mm VSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPS54327 Transient Response Vout (50 mV/div) Iout (2 A/div) 100 ms/div 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 7 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 7.3 Feature Description................................................... 7 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 10 8.1 Application Information............................................ 10 8.2 Typical Application ................................................. 10 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 14 10.1 Layout Guidelines ................................................. 14 10.2 Layout Examples................................................... 15 10.3 Thermal Considerations ........................................ 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2012) to Revision C Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Removed Ordering Information table .................................................................................................................................... 1 Changes from Revision A (October 2011) to Revision B Page • Removed (SWIFT™) from the data sheet title ....................................................................................................................... 1 • Added "and 10-pin DRC" to the DESCRIPTION .................................................................................................................... 1 • Added the DRC-10 Pin package pin out ................................................................................................................................ 3 • Changed the VBST(vs SW) MAX value From: 6V to 6.5V in the Abs Max Ratings table ..................................................... 4 • Changed the VBST(vs SW) MAX value From: 5.7V to 6V in the ROC table......................................................................... 4 • Changed UVLO MIn Value From: 0.19 V To: 0.17 V ............................................................................................................. 5 • Added Added a conditions statement "VIN = 12 V, TA = 25°C" to the TYPICAL CHARACTERISTICS ............................... 6 • Changed Figure 10 title From: 1.05-V, 50-mA to 2-A LOAD TRANSIENT RESPONSE To: 1.05-V, 0-A to 3-A LOAD TRANSIENT RESPONSE .................................................................................................................................................... 12 • Changed Figure 12 Figure Title From: (IO = 2 A) To: (IO = 3 A)........................................................................................... 12 • Changed Figure 13 Figure Title From: (IO = 2 A) To: (IO = 3 A)........................................................................................... 12 • Added Figure 17 ................................................................................................................................................................... 16 Changes from Original (November 2010) to Revision A Page • Changed Pin 6 (SW) Description In the Pin Functions table ................................................................................................ 3 • Changed the VENH Min value From: 2 V To: 1.6 V in the Logic Threshold section ................................................................ 5 • Changed Figure 4................................................................................................................................................................... 6 • Changed Equation 1............................................................................................................................................................... 8 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DDA Package 8-Pin HSOP Top View 1 DRC Package 10-Pin VSON Top View VIN EN 10 VIN EN 1 8 VFB 2 2 VFB TPS54327 (DDA) VBST Exposed Thermal Die PAD on Underside PGND VREG5 3 7 SS 4 3 VREG5 4 SS PowerPAD SW 6 GND 5 GND 5 9 VIN 8 VBST 7 SW 6 SW Pin Functions PIN NAME TYPE DESCRIPTION HSOP VSON EN 1 1 I Enable input control. Active high. VFB 2 2 I Converter feedback input. Connect to output voltage with feedback resistor divider. VREG5 3 3 O 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low. SS 4 4 O Soft-start control. An external capacitor should be connected to GND. GND 5 5 G Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. SW 6 6, 7 O Switch node connection between high-side NFET and low-side NFET. VBST 7 8 I Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. VIN 8 9, 10 P Input voltage supply pin. Back side — G PowerPAD of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. — Back side G Thermal pad of the package. PGND power ground return of internal low-side FET. Must be soldered to achieve appropriate dissipation. PowerPAD Exposed thermal pad Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 3 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Input voltage (1) MIN MAX UNIT VIN, EN –0.3 20 V VBST –0.3 26 V VBST (10 ns transient) –0.3 28 V VBST (vs SW) –0.3 6.5 V VFB, SS –0.3 6.5 V SW –2 20 V SW (10 ns transient) –3 22 V VREG5 –0.3 6.5 V GND –0.3 0.3 V Voltage from GND to thermal pad, Vdiff –0.2 0.2 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C Output voltage (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN VI MIN MAX 4.5 18 VBST –0.1 24 VBST (10 ns transient) –0.1 27 VBST(vs SW) –0.1 6 SS –0.1 5.7 EN –0.1 18 VFB –0.1 5.5 SW –1.8 18 Supply input voltage Input voltage SW (10 ns transient) UNIT V V –3 21 GND –0.1 0.1 –0.1 5.7 V VO Output voltage VREG5 IO Output Current IVREG5 0 10 mA TA Operating free-air temperature –40 85 °C TJ Operating junction temperature –40 150 °C 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 6.4 Thermal Information TPS54327 THERMAL METRIC (1) DDA (HSOP) DRC (VSON) 8 PINS 10 PINS UNIT RθJA Junction-to-ambient thermal resistance 42.1 43.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.9 55.4 °C/W RθJB Junction-to-board thermal resistance 31.8 18.9 °C/W ψJT Junction-to-top characterization parameter 5 0.7 °C/W ψJB Junction-to-board characterization parameter 13.5 19.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 5.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over operating free-air temperature range VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IVIN Operating - non-switching supply current VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V 800 1200 μA IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 1.8 10 μA LOGIC THRESHOLD VENH EN high-level input voltage EN VENL EN low-level input voltage EN 1.6 V 0.45 V 765 781 mV 0 ±0.1 μA 5.5 5.7 V 25 mV 100 mV VFB VOLTAGE AND DISCHARGE RESISTANCE VFBTH VFB threshold voltage TA = 25°C, VO = 1.05 V, continuous mode IVFB VFB input current VFB = 0.8 V, TA = 25°C 749 VREG5 OUTPUT VVREG5 VREG5 output voltage TA = 25°C, 6 V < VIN < 18 V, 0 < IVREG5 < 5 mA VLN5 Line regulation 6 V < VIN < 18 V, IVREG5 = 5 mA VLD5 Load regulation 0 mA < IVREG5 < 5 mA IVREG5 Output current VIN = 6 V, VREG5 = 4 V, TA = 25°C RDS(on)h High-side switch resistance 25°C, VBST - SW = 5.5 V RDS(on)l Low-side switch resistance 25°C 5.2 60 mA 100 mΩ 70 mΩ MOSFET CURRENT LIMIT Iocl Current limit L out = 1.5 μH (1), TA = -20ºC to 85ºC 3.5 4.2 5.7 A THERMAL SHUTDOWN TSDN Thermal shutdown threshold Shutdown temperature Hysteresis (1) 165 (1) °C 30 ON-TIME TIMER CONTROL tON ON-time VIN = 12 V, VO = 1.05 V 150 tOFF(MIN) Minimum OFF-time TA = 25°C, VFB = 0.7 V 260 310 ns 2.6 ns SOFT START ISSC SS charge current VSS = 0 V 1.4 2 ISSD SS discharge current VSS = 0.5 V 0.05 0.1 Wakeup VREG5 voltage 3.45 3.75 4.05 Hysteresis VREG5 voltage 0.17 0.32 0.45 μA mA UVLO UVLO (1) UVLO threshold V Not production tested. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 5 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 6.6 Typical Characteristics VIN = 12 V, TA = 25°C (unless otherwise noted) 1200 10.0 8.0 IVINSDN - Supply Current - µA IVIN - Supply Current - µA 1000 800 600 400 6.0 4.0 2.0 200 0 -50 0 50 100 Tj - Junction Temperature - °C 0 -50 150 Figure 1. VIN Current vs Junction Temperature 50 100 Tj - Junction Temperature - °C 150 Figure 2. VIN Shutdown Current vs Junction Temperature 100 100 VIN = 18 V 90 90 80 70 Efficiency - % EN - Input Current - mA 0 60 50 40 VOUT = 3.3 V 80 VOUT = 2.5 V VOUT = 1.8 V 70 60 30 50 20 10 40 0.0 0 0 2 4 6 8 10 12 14 EN - Input Voltage - V 16 18 0.5 20 IO = 1 A 850 fs - Switching Frequency - kHz 850 fs - Switching Frequency - kHz 3.0 900 900 800 VO = 3.3 V 750 700 VO = 1.8 V 650 600 VO = 1.05 V 550 800 VO = 1.8 V 750 700 650 450 450 10 VIN - Input Voltage - V 15 20 VO = 1.05 V 550 500 5 VO = 3.3 V 600 500 Figure 5. Switching Frequency vs Input Voltage 6 2.5 Figure 4. Efficiency vs Output Current Figure 3. EN Current vs EN Voltage 400 0 1.0 1.5 2.0 IOUT - Output Current - A 400 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 Figure 6. Switching Frequency vs Output Current Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 7 Detailed Description 7.1 Overview The TPS54327 device is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. 7.2 Functional Block Diagram EN 1 EN VIN Logic VIN 8 VREG5 Control Logic Ref + SS + PWM 7 1 shot VFB SW VO 6 - 2 VBST XCON ON VREG5 VREG5 Ceramic Capacitor 3 SGND SS SS 4 5 Softstart GND PGND SGND + OCP - SW PGND VIN UVLO VREG5 UVLO REF TSD Protection Logic Ref 7.3 Feature Description 7.3.1 PWM Operation The main control loop of the TPS54327 is an adaptive ON-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 7 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 mode control. 7.3.2 PWM Frequency and Adaptive ON-Time Control TPS54327 uses an adaptive on-time control scheme and does not have a dedicated on-board oscillator. The TPS54327 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant. 7.3.3 Soft-Start and Prebiased Soft-Start The soft start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 2 μA. t SS (ms) = C6(nF) x V x 1.1 C6(nF) x 0.765 x 1.1 REF = I (mA) 2 SS (1) The TPS54327 contains a unique circuit to prevent current from being pulled from the output during start-up if the output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal mode operation. 7.3.4 Current Protection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOUT. The TPS54327 constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the overcurrent condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the higher value. There are some important considerations for this type of overcurrent protection. The load current one half of the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the overcurrent condition is removed, the output voltage will return to the regulated value. This protection is nonlatching. 8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 Feature Description (continued) 7.3.5 UVLO Protection Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS54327 is shut off. This is protection is non-latching. 7.3.6 Thermal Shutdown TPS54327 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), the device is shut off. This is non-latch protection. 7.4 Device Functional Modes 7.4.1 Normal Operation When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS54327 device operates in normal switching mode. Normal continuous conduction mode(CCM) occurs when the minimum switch current is above 0 A. In CM, the TPS54327 device operates at a quasi-fixed frequency of 650 kHz. 7.4.2 Forced CCM Operation When the TPS54327 device is in normal CCM operating mode and switch current falls below 0 A, the device begins operating in forced CCM. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 9 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS54327 device is used as a step converter that converts a voltage of 4.5 V to 18 V to a lower voltage. WEBENCH software is available to aid in the design and analysis of circuits. 8.2 Typical Application Figure 7. Schematic Diagram 8.2.1 Design Requirements Use the parameters in Table 1 for this application. Table 1. TPS54327EVM-686 Performance Specifications Summary PARAMETERS TEST CONDITIONS Input voltage range (VIN) MIN TYP MAX 4.5 12 18 Output voltage Operating frequency 1.05 VIN = 12 V, IO = 1 A 0 V V 675 Output current range UNIT kHz 3 A 8.2.2 Detailed Design Procedure To • • • • • 10 begin the design process, you must know a few application parameters: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 8.2.2.1 Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT. To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable. æ ö R1÷ V = 0.765 x çç1 + ÷ OUT çè R2 ÷ø (2) 8.2.2.2 Output Filter Selection The output filter used with the TPS54327 is an LC circuit. This LC filter has double pole at: F = P 2p L 1 x COUT OUT (3) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54327. The low-frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high-frequency zero that reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high-frequency zero but close enough that the phase boost provided be the high-frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2 Table 2. Recommended Component Values OUTPUT VOLTAGE (V) R1 (kΩ) R2 (kΩ) L1 (µH) C8 + C9 (µF) 1 6.81 22.1 C4 (pF) 1.5 22 to 68 1.05 8.25 22.1 1.5 22 to 68 1.2 12.7 22.1 1.5 22 to 68 1.8 30.1 22.1 5 - 22 2.2 22 to 68 2.5 49.9 22.1 5 - 22 2.2 22 to 68 3.3 73.2 22.1 5 - 22 2.2 22 to 68 5 124 22.1 5 - 22 3.3 22 to 68 6.5 165 22.1 5 - 22 3.3 22 to 68 Because the DC gain is dependent on the output voltage, the required inductor value will increase as the output voltage increases. For higher output voltages above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor (C4) in parallel with R1 The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for fSW. Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS current of Equation 6. - VOUT V V OUT x IN(max) I = IPP V L x f IN(max) O SW I lpp I =I + Ipeak O = I Lo(RMS) (4) 2 I 2 O (5) + 1 2 I 12 IPP (6) For this design example, the calculated peak current is 3.47 A and the calculated RMS current is 3.01 A. The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11 A. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 11 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com The capacitor value and ESR determines the amount of output voltage ripple. The TPS54327 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 7 to determine the required RMS current rating for the output capacitor. I Co(RMS) VOUT x (VIN - VOUT ) 12 x VIN x LO x fSW = (7) For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.271 A and each output capacitor is rated for 4 A. 8.2.2.3 Input Capacitor Selection The TPS54327 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. TI recommends a ceramic capacitor over 10 μF for the decoupling capacitor. TI also recommends connecting an additional 0.1-µF capacitor from pin 14 to ground to improve the stability of the overcurrent limit function. The capacitor voltage rating must be greater than the maximum input voltage. 8.2.2.4 Bootstrap Capacitor Selection A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI recommends using a ceramic capacitor. 8.2.2.5 VREG5 Capacitor Selection A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. TI recommends using a ceramic capacitor. 1.08 1.08 1.07 1.07 VIN = 18 V VIN = 12 V VO - Output Voltage - V VO - Output Voltage - V 8.2.3 Application Curves VIN = 5 V 1.06 1.05 1.04 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 Figure 8. 1.05-V Output Voltage vs Output Current 12 IO = 0 A 1.06 IO = 1 A 1.05 1.04 0 5 10 VI - Input Voltage - V 15 20 Figure 9. 1.05-V Output Voltage vs Input Voltage Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 Vout (50 mV/div) EN (10 V/div) VREG5 (5 V/div) Iout (2 A/div) Vout (0.5 V/div) 100 ms/div 1 ms/div) Figure 10. 1.05-V, 0-A to 3-A Load Transient Response Figure 11. Start-Up Wave Form VO (10 mV/div) VO = 1.05 V VO = 1.05 V SW (5 V/div) SW (5 V/div) Figure 12. Voltage Ripple at Output (IO = 3 A) Figure 13. Voltage Ripple at Input (IO = 3 A) 100.0 100.0 90.0 90.0 80.0 80.0 VIN = 12 V 70.0 VIN = 5 V VIN = 12 V Efficiency (%) Efficiency (%) 70.0 60.0 50.0 40.0 60.0 50.0 30.0 20.0 20.0 10.0 10.0 0.5 1.0 1.5 Output Current (A) 2.0 2.5 Figure 14. TPS54327EVM-686 Efficiency 3.0 VIN = 5 V 40.0 30.0 0.0 0.0 VIN (50 mV/div) 0.0 0.001 0.01 0.1 Output Current (A) 1 10 Figure 15. TPS54327EVM-686 Light Load Efficiency Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 13 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 9 Power Supply Recommendations The TPS54327 device is designed to operate from input supply voltage in the range of 4.5 V to 18 V. Buck converters require the input voltage to be higher than the output voltage. in this case, the maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input voltage is Vo/0.65. 10 Layout 10.1 Layout Guidelines 1. Keep the input switching current loop as small as possible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device. 3. Keep analog and non-switching components away from switching components. 4. Make a single point connection from the signal ground to power ground. 5. Do not allow switching current to flow under the device. 6. Keep the pattern lines for VIN and PGND broad. 7. Exposed pad of device must be connected to PGND with solder. 8. VREG5 capacitor should be placed near the device, and connected PGND. 9. Output capacitor should be connected to a broad pattern of the PGND. 10. Voltage feedback loop should be as short as possible, and preferably with ground shield. 11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND. 12. Providing sufficient via is preferable for VIN, SW and PGND connection. 13. PCB pattern for VIN, SW, and PGND should be as broad as possible. 14. VIN Capacitor should be placed as near as possible to the device. 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 10.2 Layout Examples VIN FEEDBACK RESISTORS TO ENABLE CONTROL BIAS CAP VIN INPUT BYPASS CAPACITOR VIN HIGH FREQENCY BYPASS CAPACITOR EN VIN VFB VBST VREG5 SW SS GND BOOST CAPACITOR OUTPUT INDUCTOR SLOW START CAP EXPOSED THERMAL PAD AREA Connection to POWER GROUND on internal or bottom layer ANALOG GROUND TRACE VOUT OUTPUT FILTER CAPACITOR POWER GROUND VIA to Ground Plane Figure 16. PCB Layout Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 15 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Layout Examples (continued) VIN FEEDBACK RESISTORS TO ENABLE CONTROL EN VIN HIGH FREQENCY BYPASS VIN CAPACITOR VFB VIN VREG5 BIAS CAP SLOW START CAP ANALOG GROUND TRACE VIN INPUT BYPASS CAPACITOR VBST SS SW GND SW BOOST CAPACITOR OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR EXPOSED THERMAL PAD AREA Connection to POWER GROUND on internal or bottom layer VOUT POWER GROUND VIA to Ground Plane Figure 17. PCB Layout for the DRC Package 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 TPS54327 www.ti.com SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 10.3 Thermal Considerations This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly attached to an external heatsink. The thermal pad must be soldered directly to the printed-circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, see the technical brief, PowerPAD™ Thermally Enhanced Package (SLMA002), and the application brief, PowerPAD™ Made Easy (SLMA004). The exposed thermal pad dimensions for this package are shown in the following illustration. Figure 18. Thermal Pad Dimensions (Top View) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 17 TPS54327 SLVSAG1C – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • PowerPAD™ Thermally Enhanced Package, SLMA002 • PowerPAD™ Made Easy, SLMA004 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks D-CAP2, E2E are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS54327 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS54327DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54327 Samples TPS54327DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54327 Samples TPS54327DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 54327 Samples TPS54327DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 54327 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
TPS54327DDAR 价格&库存

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TPS54327DDAR
  •  国内价格
  • 5+0.85278
  • 20+0.77709
  • 100+0.70140
  • 500+0.62571
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  • 2000+0.56515

库存:2679