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Table of Contents
User’s Guide
TPS54329E Step-Down Converter Evaluation Module
User's Guide
ABSTRACT
This user's guide contains information for the TPS54329EEVM-056 evaluation module as well as for the
TPS54329E. The user's guide also includes the performance specifications, schematic, and the bill of materials
of the TPS54329EEVM-056.
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Performance Specification Summary................................................................................................................................... 3
3 Modifications...........................................................................................................................................................................4
3.1 Output Voltage Setpoint..................................................................................................................................................... 4
3.2 Output Filter and Closed-Loop Response..........................................................................................................................4
4 Test Setup and Results.......................................................................................................................................................... 5
4.1 Input/Output Connections.................................................................................................................................................. 5
4.2 Start-Up Procedure............................................................................................................................................................ 5
4.3 Efficiency............................................................................................................................................................................6
4.4 Load Regulation................................................................................................................................................................. 7
4.5 Line Regulation.................................................................................................................................................................. 7
4.6 Load Transient Response.................................................................................................................................................. 8
4.7 Output Voltage Ripple........................................................................................................................................................ 9
4.8 Input Voltage Ripple......................................................................................................................................................... 10
4.9 Start-Up............................................................................................................................................................................ 11
5 Board Layout.........................................................................................................................................................................13
5.1 Layout.............................................................................................................................................................................. 13
6 Schematic, Bill of Materials, and Reference...................................................................................................................... 16
6.1 Schematic........................................................................................................................................................................ 16
6.2 Bill of Materials.................................................................................................................................................................17
6.3 Reference.........................................................................................................................................................................17
7 Revision History................................................................................................................................................................... 17
List of Figures
Figure 4-1. TPS54329EEVM-056 Efficiency................................................................................................................................6
Figure 4-2. TPS54329EEVM-056 Light-Load Efficiency..............................................................................................................6
Figure 4-3. TPS54329EEVM-056 Load Regulation.....................................................................................................................7
Figure 4-4. TPS54329EEVM-056 Line Regulation...................................................................................................................... 7
Figure 4-5. TPS54329EEVM-056 Load Transient Response, 1-A to 2-A Step........................................................................... 8
Figure 4-6. TPS54329EEVM-056 Load Transient Response, 0.01-A to 1-A Step...................................................................... 8
Figure 4-7. TPS54329EEVM-056 Output Voltage Ripple............................................................................................................ 9
Figure 4-8. TPS54329EEVM-056 Start of Eco-mode Output Voltage Ripple.............................................................................. 9
Figure 4-9. TPS54329EEVM-056 Eco-mode Output Voltage Ripple.........................................................................................10
Figure 4-10. TPS54329EEVM-056 Input Voltage Ripple...........................................................................................................10
Figure 4-11. TPS54329EEVM-056 Start-Up Relative to VIN With SS........................................................................................ 11
Figure 4-12. TPS54329EEVM-056 Start-Up Relative to VIN With VREG5................................................................................ 11
Figure 4-13. TPS54329EEVM-056 Start-Up Relative to EN With SS........................................................................................12
Figure 4-14. TPS54329EEVM-056 Start-Up Relative to EN With VREG5................................................................................ 12
Figure 5-1. Top Assembly.......................................................................................................................................................... 13
Figure 5-2. Top Layer.................................................................................................................................................................14
Figure 5-3. Internal Layer 1....................................................................................................................................................... 14
Figure 5-4. Internal Layer 2....................................................................................................................................................... 15
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Trademarks
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Figure 5-5. Bottom Layer........................................................................................................................................................... 15
Figure 6-1. TPS54329EEVM-056 Schematic Diagram..............................................................................................................16
List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................3
Table 2-1. TPS54329EEVM-056 Performance Specifications Summary.................................................................................... 3
Table 3-1. Output Voltages.......................................................................................................................................................... 4
Table 4-1. Connection and Test Points........................................................................................................................................ 5
Table 6-1. Bill of Materials..........................................................................................................................................................17
Trademarks
D-CAP2™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
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Introduction
1 Introduction
The TPS54329E is a single, adaptive on-time, D-CAP2™-mode, synchronous buck converter requiring a low,
external component count. The D-CAP2 control circuit is optimized for low-ESR output capacitors such as
POSCAP, SP-CAP, or ceramic types and features fast transient response with no external compensation. The
switching frequency is internally set at a nominal 650 kHz. The high-side and low-side switching MOSFETs
are incorporated inside the TPS54329E package along with the gate drive circuitry. The low drain-to-source
on-resistance of the MOSFETs allows the TPS54329E to achieve high efficiencies and helps keep the junction
temperature low at high-output currents. The TPS54329E also features auto-skip Eco-mode operation for
improved light-load efficiency. The TPS54329E DC/DC synchronous converter is designed to provide up to a
2-A output from an input voltage source of 4.5 V to 18 V. The output voltage range is from 0.76 V to 7 V. Table
1-1 provides the rated input voltage and output current range for the EVM.
The TPS54329EEVM-056 evaluation module circuit is a single, synchronous buck converter providing 1.05 V at
3 A from 4.5-V to 18-V input. This user’s guide describes the TPS54329EEVM-056 performance.
Table 1-1. Input Voltage and Output Current Summary
EVM
Input Voltage Range
Output Current Range
TPS54329EEVM-056
VIN = 4.5 V to 18 V
0 A to 3 A
2 Performance Specification Summary
A summary of the TPS54329EEVM-056 performance specifications is provided in Table 2-1. Specifications are
given for an input voltage of VIN = 12 V and an output voltage of 1.05 V, unless otherwise noted. The ambient
temperature is 25°C for all measurement, unless otherwise noted.
Table 2-1. TPS54329EEVM-056 Performance Specifications Summary
Specifications
Test Conditions
Input voltage range (VIN)
MIN
TYP
MAX
4.5
12
18
Output voltage
Operating frequency
VIN = 12 V, IO = 1 A
Output current range
V
1.05
V
650
kHz
0
3
Line regulation
IO = 1.5 A
±0.32%
Load regulation
VIN = 12 V
+1.02/–
0.10%
Over current limit
VIN = 12 V, LO = 1.5 µH
Output ripple voltage
VIN = 12 V, IO = 3 A
15
Maximum efficiency
VIN = 5 V, IO= 0.6 A
86.2%
3.5
Unit
4.2
5.7
A
A
mVPP
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Modifications
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3 Modifications
These evaluation modules are designed to provide access to the features of the TPS54329E. Some
modifications can be made to this module.
3.1 Output Voltage Setpoint
To change the output voltage of the EVMs, change the value of resistor R1. Changing the value of R1 can
change the output voltage above 0.765 V. The value of R1 for a specific output voltage can be calculated using
Equation 1.
For output voltage from 0.76 V to 7 V:
æ R1 ö
VO = 0.765 ´ ç 1+
÷
è R2 ø
(1)
Table 3-1 lists the R1 values for some common output voltages. For higher output voltages of 1.8 V or above, a
feedforward capacitor (C4) can be required to improve phase margin. Pads for this component (C4) are provided
on the printed-circuit board. Note that the resistor values given in Table 3-1 are standard values and not the
exact value calculated using Equation 1.
Table 3-1. Output Voltages
Output Voltage
(V)
R1
(kΩ)
R2
(kΩ)
C4
(pF)
L1
(µH)
C9. C10, C11 Total Capacitance
(µF)
1
6.81
22.1
1.5
20–68
1.05
8.25
22.1
1.5
20–68
1.2
12.7
22.1
1.5
20–68
1.5
21.5
22.1
1.5
20–68
1.8
30.1
22.1
5 –22
2.2
20–68
2.5
49.9
22.1
5 –22
2.2
20–68
3.3
73.2
22.1
5 –22
2.2
20–68
5
124
22.1
5 –22
3.3
20–68
6.5
165
22.1
5 –22
3.3
20–68
3.2 Output Filter and Closed-Loop Response
The TPS54329E relies on the output filter characteristics to ensure stability of the control loop. Table 3-1
provides the recommended output filter components for common output voltages. It is possible for other
output filter component values to provide acceptable closed-loop characteristics. R3 and TP4 are provided for
convenience in breaking the control loop and measuring the closed-loop response.
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Test Setup and Results
4 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54329EEVM-056. The section also
includes test results typical for the evaluation modules and the following:
•
•
•
•
•
•
•
•
Efficiency
Output load regulation
Output line regulation
Load transient response
Output voltage ripple
Input voltage ripple
Start-up
Switching frequency
4.1 Input/Output Connections
The TPS54329EEVM-056 is provided with input and output connectors and test points as shown in Table 4-1. A
power supply capable of supplying 2 A must be connected to J1 through a pair of 20 AWG wires. The load must
be connected to J2 through a pair of 20 AWG wires. The maximum load current capability is 3 A. Wire lengths
must be minimized to reduce losses in the wires. Test point TP1 provides a place to monitor the input voltages
(VIN) with TP2 providing a convenient ground reference. TP8 is used to monitor the output voltage with TP9 as
the ground reference.
Table 4-1. Connection and Test Points
Reference Designator
Function
J1
VIN (see Table 1-1 for VIN range)
J2
VOUT, 1.05 V at 3 A maximum
JP1
EN control. Connect EN to OFF to disable, connect EN to ON to enable.
TP1
VIN test point at VIN connector
TP2
GND test point at VIN connector
TP3
EN test point
TP4
Loop response measurement test point
TP5
VREG5 test point
TP6
Switch node test point
TP7
Analog ground test point
TP8
Output voltage test point at VOUT connector
TP9
Ground test point at VOUT connector
4.2 Start-Up Procedure
1. Ensure that the jumper at JP1 (Enable control) is set from EN to OFF.
2. Apply appropriate VIN voltage to VIN and PGND terminals at J1.
3. Move the jumper at JP1 (Enable control) to cover EN and ON. The EVM enables the output voltage.
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Test Setup and Results
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4.3 Efficiency
Figure 4-1 shows the efficiency for the TPS54329EEVM-056 at an ambient temperature of 25°C.
100
90
80
Efficiency (%)
70
60
50
40
30
20
VIN = 5 V
VIN = 12 V
10
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
2
2.25
2.5
2.75
3
G001
Figure 4-1. TPS54329EEVM-056 Efficiency
Figure 4-2 shows the efficiency at light loads for the TPS54329EEVM-056 at an ambient temperature of 25°C.
100
90
80
Efficiency (%)
70
60
50
40
30
20
VIN = 5 V
VIN = 12 V
10
0
0.001
0.01
0.1
Output Current (A)
1
10
G002
Figure 4-2. TPS54329EEVM-056 Light-Load Efficiency
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Test Setup and Results
4.4 Load Regulation
Figure 4-3 shows the load regulation for the TPS54329EEVM-056.
1.1
VIN = 5 V
VIN = 12 V
0.9
Output Voltage Deviation (%)
0.7
0.5
0.3
0.1
−0.1
−0.3
−0.5
−0.7
−0.9
−1.1
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
2
2.25
2.5
2.75
3
G004
Figure 4-3. TPS54329EEVM-056 Load Regulation
4.5 Line Regulation
Figure 4-4 shows the line regulation for the TPS54329EEVM-056.
0.4
Output Voltage Deviation (%)
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
IOUT = 1.5 A
−0.4
4
8
12
Input Voltage (V)
16
20
G003
Figure 4-4. TPS54329EEVM-056 Line Regulation
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4.6 Load Transient Response
Figure 4-5 shows the TPS54329EEVM-056 response to load transient. The current step is from 1 A to 2 A. Total
peak-to-peak voltage variation is as shown.
VOUT = 100 mV / div (dc coupled, -850 mV offset)
IOUT = 1 A / DIV
Load step = 1 A to 2 A
Slew rate = 1 A / µsec
Time = 50 µsec / div
Figure 4-5. TPS54329EEVM-056 Load Transient Response, 1-A to 2-A Step
Figure 4-6 shows the TPS54329EEVM-056 response to load transient during Eco-mode operation. The initial
load current is 0.01 A, and the TPS54329E is operating in Eco-mode. The load step is to 1 A, taking the
TPS54329E out of Eco-mode operation as shown in the VOUT waveform.
VOUT = 100 mV / div (dc coupled, -850 mV offset)
IOUT = 1 A / DIV
Load step = 0.01 A to 1.0 A
Slew rate = 1 A / µsec
Time = 50 µsec / div
Figure 4-6. TPS54329EEVM-056 Load Transient Response, 0.01-A to 1-A Step
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Test Setup and Results
4.7 Output Voltage Ripple
Figure 4-7 shows the TPS54329EEVM-056 output voltage ripple. The output current is the rated full load of 3 A.
VOUT = 50 mV / div (ac coupled)
PH = 5 V / div
Time = 1 µsec / div
Figure 4-7. TPS54329EEVM-056 Output Voltage Ripple
Figure 4-8 shows the TPS54329EEVM-056 output voltage ripple during the start of Eco-mode operation. The
output current is 30 mA.
VOUT = 50 mV / div (ac coupled)
PH = 5 V / div
Time = 1 µsec / div
Figure 4-8. TPS54329EEVM-056 Start of Eco-mode Output Voltage Ripple
Figure 4-9 shows the TPS54329EEVM-056 output voltage ripple during Eco-mode operation. The output current
is 1 mA.
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VOUT = 20 mV / div (ac coupled)
PH = 5 V / div
Time = 10 µsec / div
Figure 4-9. TPS54329EEVM-056 Eco-mode Output Voltage Ripple
4.8 Input Voltage Ripple
Figure 4-10 shows the TPS54329EEVM-056 input voltage ripple. The output current is the rated full load of 3 A.
VIN = 50 mV / div (ac coupled)
PH = 5 V / div
Time = 1 µsec / div
Figure 4-10. TPS54329EEVM-056 Input Voltage Ripple
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Test Setup and Results
4.9 Start-Up
Figure 4-11 and Figure 4-12 show the TPS54329EEVM-056 start-up waveforms relative to VIN.
VIN = 10 V / div
SS = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 4-11. TPS54329EEVM-056 Start-Up Relative to VIN With SS
VIN = 10 V / div
VREG5 = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 4-12. TPS54329EEVM-056 Start-Up Relative to VIN With VREG5
Figure 4-13 and Figure 4-14 show the TPS54329EEVM-056 start-up waveforms relative to enable (EN).
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EN = 10 V / div
SS = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 4-13. TPS54329EEVM-056 Start-Up Relative to EN With SS
EN = 10 V / div
VREG5 = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 4-14. TPS54329EEVM-056 Start-Up Relative to EN With VREG5
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Board Layout
5 Board Layout
This section provides description of the TPS54329EEVM-056, board layout, and layer illustrations.
5.1 Layout
Figure 5-1 through Figure 5-5 show the board layout of the TPS54329EEVM-056. The top layer contains the
main power traces for VIN, VO, and ground. Also on the top layer are connections for the pins of the TPS54329E
and a large area filled with ground. Many of the signal traces also are located on the top side. The input
decoupling capacitors are located as close to the IC as possible. The input and output connectors, test points,
and all of the components are located on the top side. An analog ground (GND) area is provided on the top
side. Analog ground (GND) and power ground (PGND) are connected at a single point on the top layer near
C6. The two internal layers are completely dedicated to power ground planes. The bottom layer is primarily
power ground. A copper pour area on the bottom layer is used to connect the switching node (SW) to the output
inductor and the boost capacitor. Traces also connect the enable control jumper, EN, VREG5, and LOOP test
points, and the feedback trace from VOUT to the voltage setpoint divider network.
Figure 5-1. Top Assembly
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Board Layout
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Figure 5-2. Top Layer
Figure 5-3. Internal Layer 1
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Board Layout
Figure 5-4. Internal Layer 2
Figure 5-5. Bottom Layer
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Schematic, Bill of Materials, and Reference
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6 Schematic, Bill of Materials, and Reference
6.1 Schematic
Figure 6-1 is the schematic for the TPS54329EEVM-056.
TP1
J1
VIN
1
GND
2
TP2
C1
C2
10uF
10uF
C3
0.1uF
JP1
R3 0
TP4
ON
1
EN
2
OFF
3
TP3
R4 10.0k
U1
TPS54329E
7
R1
8.25k
5
VOUT
C4
6
TP5
1
8
R5
R2
TP7
C5
0
VIN
EN
VBST
VFB
SW
VREG5
GND
SS
THERMAL PAD
2
1
C7
0.1uF
0.47uF
C8
9
8200pF
L1 1.5 uH
TP8
VOUT
4
D1
C6
22.1k
TP6
3
1
C9
C10
C11
10uF
10uF
10uF
J2
TP9
2
VOUT
1
GND
R6
1
1
1
Not Installed
Figure 6-1. TPS54329EEVM-056 Schematic Diagram
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Schematic, Bill of Materials, and Reference
6.2 Bill of Materials
Table 6-1. Bill of Materials
Ref Des
QTY
Value
Description
Size
Part Number
MFR
C1, C2
2
10 μF
Capacitor, Ceramic, 25 V, X5R, 20%
1210
Std
Std
C3, C7
2
0.1 μF
Capacitor, Ceramic, 50 V, X7R, 10%
0603
Std
Std
C4, C8
0
Open
Capacitor, Ceramic
0603
Std
Std
C5
1
0.47 μF
Capacitor, Ceramic, 16 V, X7R, 10%
0603
Std
Std
C6
1
8200 pF
Capacitor, Ceramic, 25 V, X7R , 10%
0603
Std
Std
C9, C10, C11
2
22 μF
Capacitor, Ceramic, 6.3 V, X5R, 20%
1206
C3216X5R0J226M
TDK
D1
0
Open
Diode, 0.5 A, 30 V, 2PIN
TUMD2
RSX051VA-30
Rohm
J1, J2
2
ED555/2DS
Terminal Block, 2-pin, 6-A, 3.5 mm
0.27 × 0.25 inch
ED555/2DS
Sullins
JP1
1
PEC03SAAN
Header, Male 3-pin, 100-mil spacing
0.100 inch × 3
PEC03SAAN
Sullins
L1
1
1.5 μH
Inductor, SMT, 7.3 A, 11 mΩ
0.256 × 0.280 inch
CLF7045T-1R5N
TDK
R1
1
8.25 k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R2
1
22.1 k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R3, R5
2
0
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R4
1
10.0 k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R5
0
Open
Resistor, Chip, 1/16W, 1%
0603
Std
Std
TP1, TP3,
TP4, TP5,
TP6, TP8
3
5000
Test Point, Red, Thru Hole Color Keyed
0.100 × 0.100 inch
5000
Keystone
TP2, TP7, TP9
3
5001
Test Point, Black, Thru Hole Color Keyed
0.100 × 0.100 inch
5001
Keystone
U1
1
TPS54329EDDA
IC, 4.5-18-V Input, 3-A Sync. Step-Down SWIFT
Converter with Eco-Mode
SO8[DDA]
TPS54329EDDA
TI
0.100
929950-00
3M
PWR056
Any
–
1
Shunt, 100-mil, Black
–
1
PCB
6.3 Reference
TPS54329e, 4.5V to 18V Input, 2-A Synchronous Step-Down SWIFT™ Converter With Eco-mode™ Data Sheet
7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2011) to Revision A (October 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................3
• Updated the user's guide title............................................................................................................................. 3
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