User's Guide
SLVU794A – October 2012 – Revised February 2013
Using the TPS54340 Step-Down Converter Evaluation
Module
This user's guide contains information for the TPS54340EVM-182 evaluation module (PWR182) including
the performance specifications, schematic, and the bill of materials.
spacer so the title "List of Tables" will print on page with the list.
1
2
3
4
Contents
Introduction .................................................................................................................. 2
Test Setup and Results .................................................................................................... 5
Board Layout ............................................................................................................... 12
Schematic and Bill of Materials .......................................................................................... 15
List of Figures
................................................................................................
1
TPS54340EVM-182 Board
2
Efficiency Versus Load Current ........................................................................................... 5
3
Light-Load Efficiency
4
Efficiency Versus Load Current ........................................................................................... 6
5
Light Load Efficiency
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
.......................................................................................................
.......................................................................................................
Regulation Versus Output Current ........................................................................................
Regulation Versus Input Voltage..........................................................................................
Load Transient Response .................................................................................................
Loop Response .............................................................................................................
Line Transient Response ..................................................................................................
Output Voltage Ripple CCM ..............................................................................................
Output Voltage Ripple DCM ..............................................................................................
Output Voltage Ripple Eco-mode .........................................................................................
Input Voltage Ripple CCM .................................................................................................
Input Voltage Ripple DCM .................................................................................................
Start Up Relative to VIN ..................................................................................................
Start Up Relative to EN ...................................................................................................
Prebias Start Up Relative to EN .........................................................................................
Shutdown Relative to VIN .................................................................................................
Shutdown Relative to EN .................................................................................................
Low Dropout Operation ...................................................................................................
Low Dropout Start Up and Shutdown ...................................................................................
TPS54340EVM-182 Top Assembly and Silkscreen ..................................................................
TPS54340EVM-182 Top-Side Layout ..................................................................................
TPS54340EVM-182 Layer 2 Layout ....................................................................................
TPS54340EVM-182 Layer 3 Layout ....................................................................................
TPS54340EVM-182 Bottom-Side Layout ..............................................................................
TPS54340EVM-182 Schematic..........................................................................................
2
5
6
6
6
7
7
7
8
8
8
9
9
10
10
10
11
11
11
11
12
13
13
14
14
15
Eco-mode is a trademark of Texas Instruments.
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1
Introduction
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List of Tables
1
1
Input Voltage and Output Current Summary ............................................................................ 3
2
TPS54340EVM-182 Performance Specification Summary ............................................................ 4
3
R5 Values for Common Output Voltages ................................................................................ 4
4
EVM Connectors and Test points ......................................................................................... 5
5
TPS54340EVM-182 Bill of Materials .................................................................................... 16
Introduction
This user's guide contains background information for the TPS54340 as well as support documentation for
the TPS54340EVM-182 evaluation module (PWR182). Also included are the performance specifications,
the schematic, and the bill of materials for the TPS54340EVM-182.
Figure 1. TPS54340EVM-182 Board
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Introduction
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1.1
Background
The TPS54340 DC-DC converter is designed to provide up to a 3.5-A output from an input voltage source
of 4.5 V to 42 V. Rated input voltage and output current range for the evaluation module are given in
Table 1. This evaluation module is designed to demonstrate the small, printed-circuit-board (PCB) areas
that may be achieved when designing with the TPS54340 regulator. The switching frequency is externally
set at a nominal 600 kHz. The high-side MOSFET is incorporated inside the TPS54340 package along
with the gate-drive circuitry. The compensation components are external to the integrated circuit (IC), and
an external resistor divider allows for an adjustable output voltage. Additionally, the TPS54340 provides an
adjustable undervoltage lockout with hysteresis through an external resistor divider. The absolute
maximum input voltage is 42 V for the TPS54340EVM-182.
Table 1. Input Voltage and Output Current Summary
1.2
EVM
Input Voltage Range
Output Current Range
TPS54340EVM-182
VIN = 6 V to 42 V
IOUT = 0 A to 3.5 A
Performance Specification Summary
A summary of the TPS54340EVM-182 (EVM) performance specifications is provided in Table 2.
Specifications are given for an input voltage of VIN = 12 V and an output voltage of 3.3 V, unless otherwise
specified. This EVM is designed and tested for VIN = 6 V to 42 V. The ambient temperature is 25°C for all
measurements, unless otherwise noted.
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Introduction
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Table 2. TPS54340EVM-182 Performance Specification Summary
Specification
Test Conditions
MIN
VIN voltage range
6
Output voltage set point
MAX
12
42
3.3
Output current range
VIN = 6 V to 42 V
Line regulation
IOUT = 3.5 A, VIN = 6 V to 42 V
±0.3%
Load regulation
VIN = 12 V, IOUT = 0.001 A to 3.5 A
±0.6%
IOUT = 0.875 A to 2.625 A
Load transient response
IOUT = 2.625 A to 0.875 A
0
Unit
V
V
3.5
A
Voltage change
–140
mV
Recovery time
300
µs
Voltage change
140
mV
Recovery time
300
µs
39
kHz
Loop bandwidth
VIN = 12 V, IOUT = 3.5 A
Phase margin
VIN = 12 V, IOUT = 3.5 A
59
°
Input voltage ripple
IOUT = 3.5 A
300
mVpp
Output voltage ripple
IOUT = 3.5 A
10
mVpp
Output rise time
Operating frequency
1.3
TYP
Maximum efficiency
TPS54340EVM-182, VIN = 12 V, IOUT = 1.1 A
DCM threshold
VIN = 12 V
Pulse skipping threshold
No load input current
2
ms
600
kHz
88%
342
mA
VIN = 12 V
31
mA
VIN = 12 V
237
µA
UVLO start threshold
5.75
V
UVLO stop threshold
4.5
V
Modifications
These evaluation modules are designed to provide access to the features of the TPS54340. Some
modifications can be made to this module.
1.3.1
Output Voltage Set Point
To change the output voltage of the EVM, it is necessary to change the value of resistor R5. Changing the
value of R5 can change the output voltage above 0.8 V. The value of R5 for a specific output voltage can
be calculated using Equation 1, where RHS is R5 and RLS is R6.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(1)
Table 3 lists the R5 values for some common output voltages assuming R6 = 10.2 kΩ. Note VIN must be in
a range so the minimum on-time is greater than 135 ns. The values given in Table 3 are standard 1%
values, not the exact value calculated using Equation 1.
Table 3. R5 Values for Common Output Voltages
4
Output Voltage (V)
R5 Value (kΩ)
1.8
12.7
2.5
21.5
3.3
31.6
5.0
53.6
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Be aware, changing the output voltage can affect the loop response. It may be necessary to modify the
compensation components. See the data sheet for details.
2
Test Setup and Results
This section describes how to properly connect, set up, and use the EVM. The section also includes test
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up, and shutdown.
2.1
I/O Connections
This EVM includes I/O connectors and test points as shown in Table 4. A power supply capable of
supplying at least 3.5 A must be connected to J2 through a pair of 20-AWG wires. The load must be
connected to J1 through a pair of 20-AWG wires. The maximum load-current capability must be 3.5 A.
Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor
the VIN input voltages with TP2 providing a convenient ground reference. TP3 is used to monitor the output
voltage with TP4 as the ground reference.
Table 4. EVM Connectors and Test points
Reference Designator
2.2
Function
J1
VOUT, 3.3 V at 3.5-A maximum
J2
VIN (see Table 1 for VIN range)
J3
EN jumper. Connect EN to ground to disable, open to enable.
TP1
VIN test point at VIN connector
TP2
GND test point at VIN
TP3
Output voltage test point at VOUT connector
TP4
GND test point at VOUT connector
TP5
SW test point
TP6
VOUT test point used for loop response measurements
TP7
Test point between voltage divider network and output. Used for loop response measurements.
Efficiency
100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
The efficiency of this EVM peaks at a load current of about 1.1 A with VIN = 12 V, and then decreases as
the load current increases towards full load. Figure 2 shows the efficiency for the EVM. Figure 3 shows
the light-load efficiency for the EVM using a semi-log scale. Figure 4 and Figure 5 show the efficiency with
VOUT adjusted to 5.0 V with 600-kHz switching frequency. Measurements are taken at an ambient
temperature of 25°C. The efficiency may be lower at higher ambient temperatures due to temperature
variation in the drain-to-source resistance of the internal MOSFET.
60
50
40
VOUT = 3.3V, fsw = 600 kHz
30
20
VOUT = 3.3V, fsw = 600 kHz
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0
0.5
1.0
1.5
2.0
2.5
3.0
6Vin
12Vin
24Vin
10
3.5
0
0.001
0.01
IO - Output Current - A
Figure 2. Efficiency Versus Load Current
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36Vin
42Vin
0.1
1
IO - Output Current - A
Figure 3. Light-Load Efficiency
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100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
Test Setup and Results
60
50
40
VOUT = 5V, fsw = 600 kHz
30
20
60
50
40
VOUT = 5V, fsw = 600 kHz
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0
0.5
1.0
1.5
2.5
2.0
3.0
3.5
6Vin
12Vin
24Vin
10
0
0.001
4.0
1
IO - Output Current - A
Figure 4. Efficiency Versus Load Current
2.3
0.1
0.01
IO - Output Current - A
36Vin
42Vin
Figure 5. Light Load Efficiency
Output Voltage Regulation
The load regulation for the EVM is shown in Figure 6. The line regulation for the EVM is shown in
Figure 7. Measurements are given for an ambient temperature of 25°C.
0.3
1
Output Voltage Deviation - %
0.8
Output Voltage Deviation - %
VIN = 12V, VOUT = 3.3V,
fsw = 600 kHz
0.6
0.4
0.2
0
-0.2
0.4
-0.6
-0.8
-1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOUT = 3.3V, IOUT = 3.5A
fsw = 600 kHz
0.2
0.1
0
-0.1
0.2
-0.3
5
10
IO - Output Current - A
Figure 6. Regulation Versus Output Current
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15
20
25
30
35
40
45
VIN - Input Voltage - V
Figure 7. Regulation Versus Input Voltage
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2.4
Load Transients and Loop Response
The EVM response to load transients is shown in Figure 8. The current step is from 25% to 75% of the
maximum rated load at 12-V input. The current step slew rate is 100 mA/µs. Total peak-to-peak voltage
variation is as shown, including ripple and noise on the output.
The EVM loop-response characteristics are shown in Figure 9. Gain and phase plots are shown for VIN
voltage of 12 V. Load current for the measurement is 3.5 A.
180
60
40
C4: IOUT
100 mV/div
60
Gain - dB
20
C4
C3
120
C3: VOUT ac coupled
Gain
0
0
-60
-20
VIN = 12V,
VOUT = 3.3V,
IOUT = 3.5A
-40
-60
10
100
Time = 100 ms/div
-120
-180
1000
10000
100000
1000000
Frequency - Hz
Figure 8. Load Transient Response
2.5
Phase - degree
1 A/div
Phase
Figure 9. Loop Response
Line Transients
10 V/div
The EVM response to line transients is shown in Figure 10. The input voltage step is from 8.0 V to 40 V.
Total peak-to-peak voltage variation is as shown, including ripple and noise on the output.
20 mV/div
VIN
VOUT
-3.3 V offset
Time = 4 ms/div
Figure 10. Line Transient Response
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Test Setup and Results
2.6
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Output Voltage Ripple
The EVM CCM output voltage ripple is shown in Figure 11. The output current is the rated full load of 3.5
A and VIN = 12 V. The voltage ripple is measured directly across the output capacitors.
The DCM output voltage ripple is shown in Figure 12. The output current is 0.1 A and VIN = 12 V.
The Pulse Skip Eco-mode™ output voltage ripple is shown in Figure 13. There is no external load on the
output and VIN = 12 V.
10 V/div
C1
500 mA/div
C4: IL
1 A/div
10 V/div
C1: SW
C2: VOUT ac coupled
10 mV/div
20 mV/div
IOUT = 3.5 A
C2
C4
C1: SW
C1
C4: IL
C4
IOUT = 100 mA
C2
C2: VOUT ac coupled
Time = 2 ms/div
Time = 2 ms/div
20 mV/div
200 mA/div
10 V/div
Figure 11. Output Voltage Ripple CCM
Figure 12. Output Voltage Ripple DCM
C1: SW
C1
C4: IL
C4
C2: VOUT ac coupled
C2
No Load
Time = 2 ms/div
Figure 13. Output Voltage Ripple Eco-mode
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2.7
Input Voltage Ripple
The EVM CCM input voltage ripple is shown in Figure 14. The output current is the rated full load of 3.5 A
and VIN = 12 V. The voltage ripple is measured directly across the input capacitors.
10 V/div
C1: SW
C1
1 A/div
C4: IL
IOUT = 3.5 A
50 mV/div
200 mV/div
C3: VIN ac coupled
500 mA/div
10 V/div
The DCM input voltage ripple is shown in Figure 15. The output current is 0.1 A and VIN = 12 V.
C2
C4
C1: SW
C1
C4: IL
C4
IOUT = 100 mA
C3: VIN ac coupled
C3
Time = 2 ms/div
Figure 14. Input Voltage Ripple CCM
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Time = 2 ms/div
Figure 15. Input Voltage Ripple DCM
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Test Setup and Results
2.8
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Start Up
The start up waveforms are shown in Figure 16, Figure 17, and Figure 18. The input voltage for these
plots is 12 V with a 3.5-A resistive load. In Figure 16 the top trace shows VIN, the middle trace shows EN,
and the bottom trace shows VOUT. The input voltage is initially applied, and when the input reaches the
undervoltage lockout threshold, the start up sequence begins and the output ramps up toward the set
value of 3.3 V.
In Figure 17 the input voltage is initially applied with EN held low. When EN is released, the start up
sequence begins and the output ramps up toward the set value of 3.3 V.
5 V/div
5 V/div
In Figure 18 the input voltage is initially applied with EN held low. An external voltage of 1.8 V is supplied
to VOUT. When EN is released, the start up sequence begins and the internal reference ramps up from 0 V
with the internal soft-start. When the internal reference reaches the FB voltage the output begins ramping
toward the set value of 3.3 V.
C1: VIN
C1: VIN
C3: EN
C3
2 V/div
C1
C2: VOUT
2 V/div
2 V/div
2 V/div
C1
C2
C3: EN
C3
C2: VOUT
C2
Time = 2 ms/div
Time = 2 ms/div
1 V/div
2 V/div
5 V/div
Figure 16. Start Up Relative to VIN
Figure 17. Start Up Relative to EN
C1: VIN
C2: EN
C3: VOUT
Time = 2 ms/div
Figure 18. Prebias Start Up Relative to EN
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2.9
Shutdown
The shutdown waveforms are shown in Figure 19 and Figure 20. The input voltage for these plots is 12 V
with a 3.5-A resistive load. The top trace shows VIN, the middle trace shows EN, and the bottom trace
shows VOUT. In Figure 19 the input voltage is removed, and when the input falls below the undervoltage
lockout threshold, the TPS54340 shuts down and the output falls to ground.
5 V/div
5 V/div
In Figure 20, the input voltage is held at 12 V, and EN is shorted to ground. When EN is grounded, the
TPS54340 is disabled, and the output voltage discharges to ground.
C2: EN
2 V/div
C2: EN
2 V/div
C1: VIN
2 V/div
2 V/div
C1: VIN
C3: VOUT
C3: VOUT
Time = 1 ms/div
Time = 200 µs/div
Figure 19. Shutdown Relative to VIN
Figure 20. Shutdown Relative to EN
2.10 Low Dropout Operation
For improved low dropout operation, the TPS54340 includes a small integrated low-side MOSFET to pull
SW to GND when the BOOT to SW voltage drops below 2.1 V. This recharges the BOOT capacitor for
driving the high-side MOSFET. Figure 21 shows the steady state operation and Figure 22 shows the start
up and shutdown in a low dropout condition.
C1: SW
20 mV/div
2 V/div
200 mA/div
2 V/div
IOUT = 1 A
EN Floating
C4
C4: IL
VIN
C3
VOUT
C3: VOUT ac coupled
VIN = 5.5 V
VOUT = 5 V
No Load
EN Floating
Time = 20 ms/div
Figure 21. Low Dropout Operation
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Time = 40 ms/div
Figure 22. Low Dropout Start Up and Shutdown
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Board Layout
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Board Layout
This section provides a description of the EVM, board layout, and layer illustrations.
3.1
Layout
The board layout for the EVM is shown in Figure 23 through Figure 27. The top-side layer of the EVM is
laid out in a manner typical of a user application. The top and bottom layers are 2-oz copper.
The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are connections
for the remaining pins of the TPS54340 and a large area filled with ground. The bottom layer contains
ground and a signal route for the bootstrap capacitor. The top and bottom and internal ground traces are
connected with multiple vias placed around the board including six vias directly under the TPS54340
device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitors (C2 and C3), bootstrap capacitor (C4), and frequency set resistor (R3)
are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components
are also kept close to the IC. The voltage divider network ties to the output voltage at the point of
regulation, the copper VOUT trace past the output connector (J1). For the TPS54340, an additional input
bulk capacitor may be required (C3), depending on the EVM connection to the input supply.
Figure 23. TPS54340EVM-182 Top Assembly and Silkscreen
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Figure 24. TPS54340EVM-182 Top-Side Layout
Figure 25. TPS54340EVM-182 Layer 2 Layout
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Board Layout
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Figure 26. TPS54340EVM-182 Layer 3 Layout
Figure 27. TPS54340EVM-182 Bottom-Side Layout
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Schematic and Bill of Materials
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3.2
Estimated Circuit Area
The estimated printed-circuit-board area for the components used in this design is 1.025 in2 (661 mm2).
This area does not include test points or connectors. This design uses 0603 components for easy
modifications. The area can be reduced by using smaller-sized components.
4
Schematic and Bill of Materials
This section presents the EVM schematic and bill of materials.
4.1
Schematic
Figure 28 is the schematic for the EVM.
0.1uF
C4
2
GND
1
J2
6V to 42V
C3
TP2
1
+
2
C1
2.2uF
3
C2
2.2uF
4
R1
365k
BOOT
SW
VIN
GND
EN
COMP
RT/CLK
PWRPD
VIN
1
FB
L1
5.6 uH
TP5
U1
TPS54340DDA
TP1
TP6
7
C6
D1
6
5
TP3
J1
3.3V @ 3.5A
8
FB
C7
100uF
B560C
1
C9
R7
49.9
+
1
TP4
1
VOUT
2
GND
TP7
9
GND
R4
11.5k
J3
EN
1
GND
2
R2
86.6k
R3
162k
R5
31.6k
C8
FB
47pF
C5
TP8
5600pF
1
R6
10.2k
Not Populated
Figure 28. TPS54340EVM-182 Schematic
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Schematic and Bill of Materials
4.2
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Bill of Materials
Table 5 presents the bill of materials for the EVM.
Table 5. TPS54340EVM-182 Bill of Materials
Count
RefDes
Value
Description
Size
Part Number
MFR
0
C3
open
Capacitor, 100 V
Multi sizes
Engineering Only
STD
1
C4
0.1 µF
Capacitor, ceramic, 10 V, X5R, 10%
0603
STD
STD
1
C5
5600 pF
Capacitor, ceramic, 25 V, X5R, 20%
0603
STD
STD
1
C8
47 pF
Capacitor, ceramic, 50 V, C0G, 5%
0603
STD
STD
0
C7, C9
open
Capacitor
Multi sizes
Engineering Only
STD
2
C1-2
2.2 µF
Capacitor, ceramic, 100 V, X7R, 10%
1210
STD
STD
2
C6
100 µF
Capacitor, ceramic, 6.3 V, X5R, 20%
1210
STD
STD
1
D1
B560C
Diode, 5 A, 60 V
SMC
B560C-13-F
Diodes Inc
1
J3
PEC02SAAN
Header, male 2-pin, 100-mil spacing
0.100 in × 2
PEC02SAAN
Sullins
2
J1-2
ED555/2DS
Terminal block, 2-pin, 6 A, 3.5 mm
0.27 × 0.25 in
ED555/2DS
OST
1
L1
5.6 µH
Inductor, SMT, 6.7A, 20.6 mΩ
0.413 x 0.402 in
7443552560
WE
1
R1
365 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R2
86.6 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R3
162 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R4
11.5 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R5
31.6 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R6
10.2 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R7
49.9 Ω
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
SH1
Short jumper, 100mil
0.100 in
929950-00
3M
1
TP6
5013
Test point, orange, thru hole
0.125 × 0.125 in
5013
Keystone
1
TP7
5014
Test point, yellow, thru hole
0.125 × 0.125 in
5014
Keystone
3
TP1 TP3
TP5
5010
Test point, red, thru hole
0.125 × 0.125 in
5010
Keystone
3
TP2 TP4
TP8
5011
Test point, black, thru hole
0.125 × 0.125 in
5011
Keystone
1
U1
TPS54340DDA
IC, 42 V, 3.5 A, low Iq, current mode, buck
regulator
HSOIC
TPS54340DDA
TI
1
–
PWR182
Any
PCB, 3 in × 3 in × 0.062 in
Notes: 1. These assemblies are ESD sensitive, observe ESD precautions.
2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
16
Using the TPS54340 Step-Down Converter Evaluation Module
SLVU794A – October 2012 – Revised February 2013
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【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
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【ご使用にあたっての注】
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本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
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3.
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