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TPS54340-Q1
SLVSBZ1A – SEPTEMBER 2013 – REVISED NOVEMBER 2015
TPS54340-Q1 4.5-V to 42-V Input, 3.5-A, Step-Down DC-DC Converter With Eco-Mode™
1 Features
3 Description
•
•
The TPS54340-Q1 device is a 42-V, 3.5-A, stepdown regulator with an integrated high-side MOSFET.
The device survives load-dump pulses up to 45 V per
ISO 7637. Current-mode control provides simple
external compensation and flexible component
selection. A low-ripple pulse-skip mode reduces the
no-load supply current to 146 μA. Shutdown supply
current is reduced to 1 μA when the enable pin is
pulled low.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C3B
High Efficiency at Light Loads With Pulse Skipping
Eco-mode™
92-mΩ High-Side MOSFET
146-μA Operating Quiescent Current and 2-µA
Shutdown Current
100-kHz to 2.5-MHz Adjustable Switching
Frequency
Synchronizes to External Clock
Low Dropout at Light Loads With Integrated
BOOT Recharge FET
Adjustable UVLO Voltage and Hysteresis
0.8 V 1% Internal Voltage Reference
8-Pin HSOIC With PowerPAD™ Package
–40°C to 150°C TJ Operating Range
Supported by WEBENCH® Software Tool
Undervoltage lockout is internally set at 4.3 V but can
be increased using an external resistor divider at the
enable pin. The output voltage start-up ramp is
internally controlled to provide a controlled start-up
and eliminate overshoot.
A wide adjustable frequency range allows for
optimization of either efficiency or external
component size. Frequency foldback and thermal
shutdown protects internal and external components
during an overload condition.
The TPS54340-Q1 device is available in an 8-pin
thermally-enhanced HSOIC PowerPAD package.
Device Information(1)
PART NUMBER
TPS54340-Q1
2 Applications
•
•
•
•
Vehicle Accessories: GPS (See SLVA412),
Entertainment, ADAS, eCall
USB Dedicated Charging Ports and Battery
Chargers (See SLVA464)
Industrial Automation and Motor Control
12-V and 24-V Industrial, Automotive, and
Communications Power Systems
SPACE
Simplified Schematic
VIN
PACKAGE
HSOP (8)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Load Current
100
VIN
90
TPS54340-Q1
80
VOUT = 5V
EN
BOOT
RT/CLK
SW
R1
COMP
FB
R3
GND
Efficiency - %
70
VOUT
VOUT = 3.3V
60
50
40
30
20
VIN = 12V
fsw = 600 kHz
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54340-Q1
SLVSBZ1A – SEPTEMBER 2013 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
RT/CLK Timing Requirements ..................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Applications ................................................ 23
9 Power Supply Recommendations...................... 35
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 36
10.3 Estimated Circuit Area .......................................... 36
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2013) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SLVSBZ1A – SEPTEMBER 2013 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
DDA Package
8-Pin HSOP
Top View
8
SW
7
GND
3
6
COMP
4
5
FB
BOOT
1
VIN
2
EN
RT/CLK
Thermal
Pad
9
Pin Functions
PIN
I/O
DESCRIPTION
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the output switches off until the capacitor is refreshed.
COMP
6
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
EN
3
I
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
FB
5
I
Inverting input of the transconductance (gm) error amplifier.
GND
7
—
NAME
NO.
BOOT
Ground
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
reenabled and the operating mode returns to resistor frequency programming.
8
I
The source of the internal high-side power MOSFET and switching node of the converter.
9
—
2
I
RT/CLK
4
SW
Thermal Pad
VIN
GND pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation.
Input supply voltage with 4.5-V to 42-V operating range.
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SLVSBZ1A – SEPTEMBER 2013 – REVISED NOVEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
45
EN
–0.3
8.4
BOOT
Input voltage
53
FB
–0.3
COMP
–0.3
3
RT/CLK
–0.3
3.6
V
3
BOOT-SW
Output voltage
UNIT
8
SW
–0.6
45
–2
45
Operating junction temperature
–40
150
°C
Storage temperature
–65
150
°C
SW, 10-ns Transient
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Supply input voltage
4.5
42
V
VO
Output voltage
0.8
58.8
V
IO
Output current
0
3.5
A
TJ
Junction Temperature
–40
150
°C
6.4 Thermal Information
TPS54340-Q1
THERMAL METRIC
(1) (2)
DDA (HSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance (standard board)
42
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
45.8
°C/W
RθJB
Junction-to-board thermal resistance
23.4
°C/W
ψJT
Junction-to-top characterization parameter
5.9
°C/W
ψJB
Junction-to-board characterization parameter
23.4
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
3.6
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout
threshold
4.5
Rising
4.1
4.3
Internal undervoltage lockout
threshold hysteresis
42
V
4.48
V
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
2.25
4.5
Operating: nonswitching
supply current
FB = 0.9 V, TA = 25°C
146
175
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
1.1
Enable threshold 50 mV
Enable threshold –50 mV
Hysteresis current
Enable to COMP active
V
–4.6
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
VIN = 12 V , TA = 25°C
μA
μA
540
µs
INTERNAL SOFT-START TIME
Soft-Start Time
fSW = 500 kHz, 10% to 90%
2.1
ms
Soft-Start Time
fSW = 2.5 MHz, 10% to 90%
0.42
ms
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
92
190
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier
transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
Error amplifier
transconductance (gM) during
soft-start
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
Error amplifier DC gain
VFB = 0.8 V
nA
350
μS
77
μS
10,000
V/V
2500
kHz
±30
μA
12
A/V
Min unity gain bandwidth
Error amplifier source and
sink
50
V(COMP) = 1 V, 100-mV overdrive
COMP to SW current
transconductance
CURRENT LIMIT
Current limit threshold
All VIN and temperatures, Open Loop (1)
4.5
5.5
6.8
All temperatures, VIN = 12 V, Open Loop (1)
4.5
5.5
6.25
5.2
5.5
5.85
VIN = 12 V, TA = 25°C, Open Loop
(1)
Current limit threshold delay
A
60
ns
176
°C
12
°C
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
1.55
RT/CLK low threshold
(1)
0.5
2
V
1.2
V
Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
6.6 RT/CLK Timing Requirements
MIN
Minimum CLK input pulse width
NOM
MAX
UNIT
15
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SLVSBZ1A – SEPTEMBER 2013 – REVISED NOVEMBER 2015
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2500
kHz
550
kHz
2300
kHz
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT
mode
ƒSW
Switching frequency
100
RT = 200 kΩ
Switching frequency range using
CLK mode
6
450
500
160
RT/CLK falling edge to SW rising
edge delay
Measured at 500 kHz with RT
resistor in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
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6.8 Typical Characteristics
0.25
0.814
VIN = 12 V
VFB − Voltage Reference (V)
RDS(ON) − On-State Resistance (Ω)
BOOT-SW = 3 V
BOOT-SW = 6 V
0.2
0.15
0.1
0.05
0
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
0.809
0.804
0.799
0.794
0.789
0.784
−50
150
Figure 1. ON Resistance vs Junction Temperature
VIN = 12 V
High-Side Switch Current (A)
High-Side Switch Current (A)
150
G002
TJ = −40°C
TJ = 25°C
TJ = 150°C
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
4.5
0
10
5
G003
Figure 3. Switch Current Limit vs Junction Temperature
500
ƒSW − Switching Frequency (kHz)
RT = 200 kΩ, VIN = 12 V
540
530
520
510
500
490
480
470
460
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
35
40
45
G004
ƒSW (kHz) = 92417 × RT (kΩ)−0.991
RT (kΩ) = 101756 × fSW (kHz)−1.008
450
400
350
300
250
200
150
100
50
0
200
G005
Figure 5. Switching Frequency vs Junction Temperature
15
20
25
30
VIN − Input Voltage (V)
Figure 4. Switch Current Limit vs Input Voltage
550
ƒSW − Switching Frequency (kHz)
125
6.5
6.3
450
−50
0
25
50
75
100
TJ − Junction Temperature (°C)
Figure 2. Voltage Reference vs Junction Temperature
6.5
4.5
−50
−25
G001
300
400
500
600
700
800
RT/CLK − Resistance (kΩ)
900
1000
G006
Figure 6. Switching Frequency vs RT/CLK Resistance
Low-Frequency Range
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Typical Characteristics (continued)
2500
500
ƒSW − Switching Frequency (kHz)
VIN = 12 V
450
2000
400
gm (dB)
1500
1000
300
500
0
250
0
50
100
150
RT/CLK − Resistance (kΩ)
200
−50
200
VIN = 12 V
EN − Threshold (V)
100
gm (uA/V)
90
80
70
60
50
40
30
20
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
125
150
G008
VIN = 12 V
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
G010
Figure 10. EN Pin Voltage vs Junction Temperature
−4
−0.5
VIN = 5 V, I EN = Threshold+50mV
−0.7
−0.9
−4.2
−1.1
−4.3
−1.3
−4.4
−1.5
−1.7
−4.5
−4.6
−1.9
−4.7
−2.1
−4.8
−2.3
−4.9
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
VIN = 12 V, I EN = Threshold+50mV
−4.1
IEN (µA)
IEN (µA)
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
−50
G009
Figure 9. EA Transconductance During Soft Start vs
Junction Temperature
−2.5
−50
0
25
50
75
100
TJ − Junction Temperature (°C)
Figure 8. EA Transconductance vs Junction Temperature
120
110
−25
G007
Figure 7. Switching Frequency vs RT/CLK Resistance
High-Frequency Range
150
−5
−50
−25
G011
Figure 11. EN Pin Current vs Junction Temperature
8
350
0
25
50
75
100
Tj − Junction Temperature (°C)
125
150
G012
Figure 12. EN Pin Current vs Junction Temperature
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Typical Characteristics (continued)
100
% of Nominal Switching Frequency
EN PIN Current Hysteresis (µA)
−2.5
−2.7
−2.9
−3.1
−3.3
−3.5
−3.7
−3.9
−4.1
−4.3
−4.5
−50
VIN = 12 V
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
VFB Falling
VFB Rising
75
50
25
0
150
0
0.1
0.2
G112
Figure 13. EN Pin Current Hysteresis vs
Junction Temperature
0.3
0.4
VFB (V)
0.5
0.6
G013
3
VIN = 12 V
TJ = 25°C
Shutdown Supply Current (µA)
Shutdown Supply Current (µA)
0.8
Figure 14. Switching Frequency vs FB
3
2.5
2
1.5
1
0.5
0
−50
0.7
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
2.5
2
1.5
1
0.5
0
150
0
5
10
G014
Figure 15. Shutdown Supply Current vs
Junction Temperature
15
20
25
30
VIN − Input Voltage (V)
35
40
45
G016
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
210
210
VIN = 12 V
190
VIN − Supply Current (µA)
VIN − Supply Current (dB)
190
170
150
130
110
90
70
−50
170
150
130
110
90
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
150
70
0
5
G016
Figure 17. VIN Supply Current vs Junction Temperature
10
15
20
25
30
VIN − Input Voltage (V)
35
40
45
G018
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
2.6
4.4
2.4
4.3
Input Voltage (V)
VIN − (BOOT−SW) (dB)
2.5
4.5
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
2.3
2.2
2.1
4.2
4.1
4
2
3.9
1.9
3.8
1.8
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
3.7
−50
150
Figure 19. BOOT-SW UVLO vs Junction Temperature
5.6
5.4
7
5.3
6
5.2
VIN (V)
8
5.1
4
5.0
3
4.9
2
4.8
1
4.7
0
4.6
100 300 500 700 900 11001300 1500 17001900 2100 2300 2500
Switching Frequency (KHz)
150
G019
Dropout
Voltage
Dropout
Voltage
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
G021
Figure 21. Soft-Start Time vs Switching Frequency
125
Start
Stop
5.5
5
0
25
50
75
100
Tj − Junction Temperature (°C)
Figure 20. Input Voltage UVLO vs Junction Temperature
VIN = 12V,
o
TJ = 25 C
9
Soft-Start Time (ms)
−25
G018
10
10
UVLO Start Switching
UVLO Stop Switching
C026
Figure 22. 5-V Start and Stop Voltage
(see Low Dropout Operation and Bootstrap Voltage (BOOT))
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7 Detailed Description
7.1 Overview
The TPS54340-Q1 device is a 42-V, 3.5-A, step-down (buck) regulator with an integrated high-side N-channel
MOSFET. The device implements constant-frequency current-mode control, which reduces output capacitance
and simplifies external frequency compensation. The wide switching-frequency range of 100 kHz to 2500 kHz
allows for either efficiency or size optimization when selecting the output filter components. The switching
frequency is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phaselocked loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turnon to a falling edge of an
external clock signal.
The TPS54340-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin adjusts the
input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current source
enables operation when the EN pin is floating. The operating current is 146 μA under no load condition (not
switching). When the device is disabled, the supply current is 1 μA.
The integrated 92-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54340-Q1 device reduces the
external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is
monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340-Q1 device to operate at
high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply
voltage of the application. The minimum output voltage is the internal 0.8-V feedback reference.
Output-overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET turns off and remains off until the output voltage is less than
106% of the desired output voltage.
The TPS54340-Q1 device includes an internal soft-start circuit that slows the output rise time during start-up to
reduce in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When
the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the
nominal regulation voltage. A frequency-foldback circuit reduces the switching frequency during start-up and
overcurrent fault conditions to help maintain control of the inductor current.
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7.2 Functional Block Diagram
EN
VIN
Shutdown
OV
Thermal
Shutdown
UVLO
Enable
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
PWM
Comparator
FB
Current
Sense
BOOT
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
GND
Oscillator
with PLL
POWERPAD
RT/ CLK
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54340-Q1 device uses fixed-frequency peak-current-mode control with adjustable switching frequency.
The output voltage is compared through external resistors connected to the FB pin to an internal voltage
reference by an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error
amplifier output at the COMP pin controls the high-side power-switch current. When the high-side MOSFET
switch current reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin
voltage increases and decreases as the output current increases and decreases. The device implements current
limiting by clamping the COMP-pin voltage to a maximum level. The pulse skipping Eco-mode is implemented
with a minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54340-Q1 device adds a compensating ramp to the MOSFET switch-current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.
12
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Feature Description (continued)
7.3.3 Pulse Skip Eco-mode™
The TPS54340-Q1 device operates in a pulse skipping Eco-mode at light-load currents to improve efficiency by
reducing switching and gate-drive losses. If the output voltage is within regulation and the peak-switch current at
the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-mode. The
pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the
falling output voltage by increasing the COMP pin voltage. The high-side MOSFET enables and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at
light-load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54340-Q1 device senses and controls peak switch current, not the average
load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 34 enters Eco-mode at about 31.4-mA output current. As the load current approaches
zero, the device enters a pulse-skip mode during which it draws only 146-μA input quiescent current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54340-Q1 device provides an integrated-bootstrap voltage regulator. A small capacitor between the
BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor refreshes
when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the
BOOT capacitor is 0.1 μF. For stable performance over temperature and voltage, TI recommends a ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher.
When operating with a low-voltage difference from input to output, the high-side MOSFET of the TPS54340-Q1
device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops to less than 2.1 V, the high-side MOSFET turns off and an integrated low-side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at
high-output voltages, it is disabled at 24-V output and reenabled when the output reaches 21.5 V.
Because the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus, the effective duty
cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during
dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the lowside diode voltage, and the printed-circuit-board resistance.
The start and stop voltage for a typical 5-V output application is shown in Figure 22, where the VIN voltage is
plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high-duty-cycle (low-dropout) conditions, the inductor-current ripple increases when the BOOT capacitor
recharges which results in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to ensure a monotonic start-up. Equation 1
calculates the minimum input voltage for this condition.
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Feature Description (continued)
VOmax = Dmax × (VVINmin – IOmax × RDS(on) + Vd) – Vd – IOmax × Rdc
where
•
•
•
•
•
•
Dmax ≥ 0.9
Vd = Forward Drop of the Catch Diode
RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246)
VB2SW = VBOOT + Vd
VBOOT = (1.41 × VVIN – 0.554 – Vd × ƒsw × 10–6 – 1.847 × 103 × IB2SW) / (1.41 + ƒsw × 10-6)
IB2SW = 100 × 10–6 A
(1)
7.3.5 Error Amplifier
The TPS54340-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal softstart voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. TI recommends using divider resistors with a 1% tolerance or better.
Select the low-side resistor RLS for the desired divider current, and use Equation 2 to calculate RHS. To improve
efficiency at light loads, consider using larger value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(2)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54340-Q1 device is enabled when the VIN-pin voltage rises above 4.3 V and the EN-pin voltage
exceeds the enable threshold of 1.2 V. The TPS54340-Q1 device is disabled when the VIN pin voltage falls to
less than 4 V, or when the EN pin voltage is less than 1.2 V. The EN pin has an internal pullup current source,
I1, of 1.2 μA that enables operation of the TPS54340-Q1 device when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled to less than 1.2 V, the
3.4 μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (for example 4.5 V) and withstand high input
voltages (for example 40 V), the EN pin can experience a voltage greater than the absolute maximum voltage of
8.4 V during the high-input voltage condition. TI recommends using a Zener diode to clamp the pin voltage below
the absolute maximum rating.
14
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Feature Description (continued)
VIN
TPS54340-Q1
i1
VIN
ihys
RUVLO1
RUVLO1
EN
EN
Optional
10 kW
Node
VEN
RUVLO2
RUVLO2
Figure 23. Adjustable Undervoltage Lockout
(UVLO)
5.8 V
Figure 24. Internal EN Clamp
- VSTOP
V
RUVLO1 = START
IHYS
(3)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1
(4)
7.3.8 Internal Soft-Start
The TPS54340-Q1 device has an internal digital soft-start that ramps the reference voltage from 0 V to the final
value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 5
1024
tSS (ms) =
fSW (kHz)
(5)
If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft start resets. The
soft start also resets in thermal shutdown.
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54340-Q1 device is adjustable over a wide range from 100 kHz to 2500 kHz
by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 6 or Equation 7 or the curves in Figure 5 and Figure 6. To reduce the solution size one
typically sets the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum
input voltage, and minimum controllable on time must be considered. The minimum-controllable on time is
typically 135 ns which limits the maximum operating frequency in applications with high input-to-output step-down
ratios. The maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed
discussion of the maximum switching frequency is provided in Accurate Current Limit Operation and Maximum
Switchign Frequency.
92417
RT (kW) =
f sw (kHz)0.991
(6)
f sw (kHz) =
101756
RT (kW)1.008
(7)
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Feature Description (continued)
7.3.10 Accurate Current Limit Operation and Maximum Switchign Frequency
The TPS54340-Q1 device implements peak-current-mode control in which the COMP-pin voltage controls the
peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin
voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the highside switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets
the peak switch-current limit. The TPS54340-Q1 device provides an accurate current limit threshold with a typical
current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in Figure 25.
Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 25. current limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54340-Q1 device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as
the FB pin voltage falls from 0.8 V to 0 V. The TPS54340-Q1 device uses a digital-frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short circuit events, the
inductor current exceeds the peak current limit because of the high input voltage and the minimum-controllable
on time. When the shorted load forces the output voltage low, the inductor current decreases slowly during the
switch-off time. The frequency foldback effectively increases the off time by increasing the period of the switching
cycle providing more time for the inductor current to ramp down.
With a maximum frequency-foldback ratio of 8, there is a maximum frequency at which the inductor current is
controlled by frequency-foldback protection. Equation 9 calculates the maximum switching frequency at which the
inductor current remains under control when VOUT is forced to VOUT(SC). The selected operating frequency must
not exceed the calculated value.
Equation 8 calculates the maximum switching-frequency limitation set by the minimum-controllable on time and
the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required at maximum input voltage.
fSW (max skip ) =
16
1
tON
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
ö
÷
÷
ø
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Feature Description (continued)
fSW(shift) =
fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - ICL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
where
•
•
•
•
•
•
•
•
•
•
IO is the output current
ICL is the current limit
Rdc is the inductor resistance
VIN is the maximum input voltage
VOUT is the output voltage
VOUT(SC) is the output voltage during short
Vd is the diode voltage drop
RDS(on) is the switch ON-resistance
tON is the controllable ON-time
fDIV is the frequency divide equals (1, 2, 4, or 8)
(9)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin receives a frequency-synchronization signal from an external system clock. To implement this
synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 26. The square wave applied to the RT/CLK pin must switch lower than 0.5 V but higher than 1.7 V, and it
must have a pulse-width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The
rising edge of the SW synchronizes to the falling edge of RT/CLK pin signal. The external synchronization circuit
must be designed so that the default-frequency set-resistor is connected from the RT/CLK pin to ground when
the synchronization signal is off. When using a low-impedance signal source, the frequency set resistor is
connected in parallel with an AC-coupling capacitor to a termination resistor (for example 50 Ω) as shown in
Figure 26. The two resistors in series provide the default-frequency setting resistance when the signal source is
turned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. TI
recommends to AC-couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin.
The first time that the RT/CLK is pulled above the PLL threshold, the TPS54340-Q1 device switches from the
RT-resistor free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is
removed and the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The
switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device
transitions from the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs.
During the transition from the PLL mode to the resistor-programmed mode, the switching frequency falls to 150
kHz and then increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is
reapplied to the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital-frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 27, Figure 28 and Figure 29 show the device synchronized to an external system clock in
continuous-conduction mode (CCM), discontinuous-conduction mode (DCM), and pulse-skip mode (Eco-Mode).
SPACER
TPS54340-Q1
TPS54340-Q1
RT/CLK
RT/CLK
PLL
PLL
RT
Clock
Source
Hi-Z
Clock
Source
RT
Figure 26. Synchronizing to a System Clock
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Feature Description (continued)
SW
SW
EXT
EXT
IL
IL
Figure 27. Plot of Synchronizing in CCM
Figure 28. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 29. Plot of Synchronizing in Eco-Mode™
7.3.12 Overvoltage Protection
The TPS54340-Q1 device incorporates an output-overvoltage-protection (OVP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients in designs with low-output
capacitance. For example, when the power-supply output is overloaded, the error amplifier compares the actual
output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage
for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the
peak current limit threshold. When the overload condition is removed, the regulator output rises and the error
amplifier output transitions to the normal operating level. In some applications, the power-supply output voltage
increases faster than the response of the error amplifier output resulting in an output overshoot.
18
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Feature Description (continued)
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB-pin
voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB-pin
voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the
internal voltage reference, the high-side MOSFET resumes normal operation.
7.3.13 Thermal Shutdown
The TPS54340-Q1 device provides an internal thermal shutdown to protect the device when the junction
temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the
thermal trip threshold. Once the die temperature falls to less than 164°C, the device reinitiates the power-up
sequence controlled by the internal soft-start circuitry.
7.3.14 Small-Signal Model for Loop Response
Figure 30 shows an equivalent model for the TPS54340-Q1 control loop, which is simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 3350 μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor Ro
and capacitor Co model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage
source between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small-signal response of the frequency compensation. Plotting a/b provides the smallsignal response of the overall loop. The dynamic loop response is evaluated by replacing RL with a current
source with the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
VO
Power Stage
gmps 12 A/V
a
b
RESR
R1
RL
COMP
c
0.8 V
R3
CO
C2
RO
FB
COUT
gmea
350 mA/V
R2
C1
Figure 30. Small-Signal Model for Loop Response
7.3.15 Simple Small-Signal Model for Peak-Current-Mode Control
Figure 31 describes a simple small-signal model that is used to design the frequency compensation. The
TPS54340-Q1 power stage is approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control-to-output transfer function is shown in
Equation 10 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP-pin voltage (node c in Figure 30) is the power-stage transconductance,
gmPS. The gmPS for the TPS54340-Q1 device is 12 A/V. The low-frequency gain of the power stage is the
product of the transconductance and the load resistance as shown in Equation 11.
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Feature Description (continued)
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load is problematic at first glance, but fortunately the dominant pole moves with the load current
(see Equation 12). The combined effect is highlighted by the dashed line in the right half of Figure 31. As the
load current decreases, the gain increases and the pole frequency lowers, which keeps the 0-dB crossover
frequency the same as load conditions vary. The type of output capacitor chosen determines whether the ESR
zero has a profound effect on the frequency compensation design. Because the phase margin is increased by
the ESR zero of the output capacitor (see Equation 13), the use of high-ESR aluminum-electrolytic capacitors
reduces the number frequency compensation components required to stabilize the overall loop.
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 31. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
s
ç1 +
2p ´ fZ
VOUT
= Adc ´ è
VC
æ
s
ç1 +
2p ´ fP
è
Adc = gmps ´ RL
fP =
ö
÷
ø
ö
÷
ø
(10)
(11)
1
COUT ´ RL ´ 2p
(12)
1
fZ =
COUT ´ RESR ´ 2p
(13)
7.3.16 Small-Signal Model for Frequency Compensation
The TPS54340-Q1 device uses a transconductance amplifier for the error amplifier and supports three of the
commonly-used frequency-compensation circuits. The compensation circuits, Type 2A, Type 2B, and Type 1, are
shown in Figure 32. Type 2 circuits are typically implemented in high-bandwidth power-supply designs using low
-ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminumelectrolytic or tantalum capacitors. Equation 14 and Equation 15 relate the frequency response of the amplifier to
the small-signal model in Figure 32. The open-loop gain and bandwidth are modeled using the RO and CO shown
in Figure 32. See Application and Implementation for a design example using a Type-2A network with a low-ESR
output capacitor.
Equation 14 through Equation 23 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
20
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Feature Description (continued)
VO
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 32. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 33. Frequency Response of the Type-2A and Type-2B Frequency Compensation
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
Ro =
CO
(14)
(15)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
A0 = gmea
A1 = gmea
P1 =
(16)
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
(17)
(18)
1
2p ´ Ro ´ C1
(19)
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Feature Description (continued)
Z1 =
P2 =
1
2p ´ R3 ´ C1
(20)
1
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
P2 =
2p ´ R O
1
type 1
´ (C2 + C O )
(21)
(22)
(23)
7.4 Device Functional Modes
The TPS54340-Q1 device is designed to operate with input voltages above 4.5 V. When the VIN voltage is
above the 4.3 V, typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the device
is active. If the VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the
EN voltage falls below the 1.2-V threshold, the device stops switching and enters a shutdown mode with low
supply current of 2 µA typical.
The TPS54340-Q1 device will operate in CCM when the output current is enough to keep the inductor current
above 0 A at the end of each switching period. As a nonsynchronous converter, it will enter DCM at low-output
currents when the inductor current falls to 0 A before the end of a switching period. At very low-output current,
the COMP voltage will drop to the pulse-skipping threshold, and the device operates in a pulse-skipping Ecomode. In this mode, the high-side MOSFET does not switch every switching period. This operating mode
reduces power loss while regulating the output voltage. For more information on Eco-mode see the Pulse Skip
Eco-mode™ section.
22
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54340-Q1 device is a 42-V, 3.5-A, step-down regulator with an integrated high-side MOSFET. This
device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output
current of 3.5 A. Example applications are: 12 V and 24 V industrial, automotive, and communications power
systems. Use the following design procedure to select component values for the TPS54340-Q1 device. This
procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use
the WEBENCH® software to generate a complete design. The WEBENCH software uses an interactive design
procedure, and accesses a comprehensive database of components when generating a design. The Typical
Applications section presents a simplified discussion of the design process.
8.2 Typical Applications
8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 3.5-A Output
L1
5.6uH
3.3V, 3.5A VOUT
C4 0.1uF
U1
TPS54340-Q1 (DDA)
VIN
6V to 42V
2
3
C1
C2
2.2uF
2.2uF
R1
365k
4
BOOT
SW
VIN
GND
EN
COMP
RT/CLK
PWRPD
1
9
GND
R2
86.6k
R3
162k
FB
8
C6
D1
100uF
B560C
7
6
5
GND
FB
R4
11.5k
C8
FB
R6
10.2k
47pF
GND
R5
31.6k
C5
5600pF
GND
GND
Figure 34. 3.3-V Output TPS54340-Q1 Design Example
8.2.1.1 Design Requirements
To start the design process, a few parameters must be known. These requirements are typically determined at
the system level. Table 1 shows the design parameters for this example.
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Typical Applications (continued)
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage
3.3 V
Transient response 0.875-A to 2.625 A-load step
ΔVOUT = 4 %
Maximum output current
3.5 A
Input voltage
12 V nominal, 6 V to 42 V
Output voltage ripple
0.5% of VOUT
Start Input voltage (rising VIN)
5.75 V
Stop Input Voltage (falling VIN)
4.5 V
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible, because this produces the smallest solution size. High switching frequency allows
for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage, and the frequency-foldback protection.
Equation 8 and Equation 9 calculate the upper limit of the switching frequency for the regulator. Choose the
lower value result from the two equations. Switching frequencies higher than these values results in pulse
skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54340-Q1. For this example, the output voltage is 3.3 V
and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid
pulse skipping from Equation 8. To ensure overcurrent runaway is not a concern during short circuits use
Equation 9 to determine the maximum switching frequency for frequency-foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 92
mΩ, a current limit value of 4.7 A, and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 6 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 34. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
1
æ 3.5 A x 21 mW + 3.3 V + 0.7 V ö
fSW(max skip) =
´ ç
÷ = 712 kHz
135ns
è 42 V - 3.5 A x 92 mW + 0.7 V ø
(24)
8
æ 4.7 A x 21 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 1260 kHz
135 ns
è 42 V - 4.7 A x 92 mW + 0.7 V ø
92417
RT (kW) =
= 163 kW
600 (kHz)0.991
fSW(shift) =
(25)
(26)
8.2.1.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 27.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple-current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer, however, the following guidelines can be used.
24
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For designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 is desirable. When
using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of
the current-mode PWM-control system, the inductor ripple current must always be greater than 150 mA for stable
PWM operation. In a wide input voltage regulator, the best choice is a relatively large inductor ripple current
which provides sufficient ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest
standard value is 5.6 μH. Not exceeding the RMS current and saturation current ratings of the inductor is
important. The RMS and peak inductor current are determined by Equation 29 and Equation 30. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE
7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the
regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current increases up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54340-Q1, which is nominally 5.5 A.
LO(min ) =
VIN(max ) - VOUT
IOUT ´ KIND
´
VOUT
42 V - 3.3 V
3.3 V
=
´
= 4.8 mH
VIN(max ) ´ fSW
3.5 A x 0.3
42 V ´ 600 kHz
(27)
spacer
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
=
3.3 V x (42 V - 3.3 V)
= 0.905 A
42 V x 5.6 mH x 600 kHz
(28)
spacer
2
æ
1 ç VOUT ´ VIN(max ) - VOUT
2
´ç
IL(rms ) = (IOUT ) +
12 ç
VIN(max ) ´ LO ´ fSW
è
(
)÷ö
÷ =
÷
ø
2
(3.5 A )2 +
æ 3.3 V ´ (42 V - 3.3 V ) ö
1
´ ç
÷ = 3.5 A
ç 42 V ´ 5.6 mH ´ 600 kHz ÷
12
è
ø
(29)
spacer
IL(peak ) = IOUT +
IRIPPLE
0.905 A
= 3.5 A +
= 3.95 A
2
2
(30)
8.2.1.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance must be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor must supply
the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator generally requires two or more clock cycles for the control loop to sense the change in output voltage
and adjust the peak switch current in response to the higher load. The output capacitance must be large enough
to supply the difference in current for two clock cycles to maintain the output voltage within the specified range.
Equation 31 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒSW
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A – 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a
minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminumelectrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
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The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a highto-low load current. The catch diode of the regulator does not sink current so energy stored in the inductor
produces an output-voltage overshoot when the load current rapidly decreases. A typical load-step response is
shown in Figure 35. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 32
calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO
is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
peak output voltage, and VI is the initial voltage. For this example, the worst-case load step is from 2.625 A to
0.875 A. The output voltage increases during this load transition, and the stated maximum in our specification is
4% of the output voltage, which makes Vf = 1.04 × 3.3 = 3.432. VI is the initial capacitor voltage, which is the
nominal output voltage of 3.3 V. Using these numbers in Equation 32 yields a minimum capacitance of 38.6 μF.
Equation 33 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒSW is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 33 yields 11.4 μF.
Equation 34 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 34 indicates the ESR must be less than 18 mΩ.
The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance deratings for aging, temperature, and DC bias increases this minimum value. For this example, 100μF ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 70 µF, which is well above the
minimum required capacitance of 44.9 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 35 calculates the RMS ripple current that the output capacitor must support. For this example,
Equation 35 yields 261 mA.
2 ´ DIOUT
2 ´ 1.75 A
=
= 44.9 mF
COUT >
fSW ´ DVOUT 600 kHz x 0.13 V
(31)
2
OH
COUT > LO
2
2
2
((I ) - (I ) ) = 5.6 mH x (2.625 A - 0.875 A ) = 38.6 mF
x
(3.432 V - 3.3 V )
((V ) - (V ) )
OL
2
f
2
1
1
´
8 ´ fSW æ VORIPPLE
ç
è IRIPPLE
V
16.5 mV
RESR < ORIPPLE =
IRIPPLE
0.905 A
COUT >
ICOUT(rms) =
2
2
I
(
ö
÷
ø
=
1
1
= 11.4 mF
x
8 x 600 kHz
æ 16.5 mV ö
ç 0.905 A ÷
è
ø
(32)
(33)
= 18 mW
VOUT ´ VIN(max ) - VOUT
(34)
)=
12 ´ VIN(max ) ´ LO ´ fSW
3.3 V ´
(42 V
- 3.3 V )
12 ´ 42 V ´ 5.6 mH ´ 600 kHz
= 261 mA
(35)
8.2.1.2.4 Catch Diode
The TPS54340-Q1 device requires an external catch diode between the SW pin and GND. The selected diode
must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340-Q1
device.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 V at
5 A.
26
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The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 36 is
used to calculate the total power dissipation, including conduction losses and AC losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 36, the total loss in the diode is
2.42 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD =
(V
IN(max ) - VOUT
)´ I
OUT
+
VIN(max )
(42 V
2
´ Vf d
- 3.3 V ) ´ 3.5 A x 0.7 V
42 V
C j ´ fSW ´ (VIN + Vf d)
=
2
+
300 pF x 600 kHz x (42 V + 0.7 V)2
= 2.42 W
2
(36)
8.2.1.2.5 Input Capacitor
The TPS54340-Q1 device requires a high-quality ceramic-type X5R or X7R input-decoupling capacitor with at
least 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance due to DC-bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater
than the maximum input current ripple of the TPS54340-Q1 device. Equation 37 calculates the input ripple
current.
The value of a ceramic capacitor varies significantly with temperature and the DC bias applied to the capacitor.
Selecting a dielectric material that is more stable overtemperature minimizes capacitance variations due to
temperature. X5R and X7R ceramic dielectrics are generally selected for switching regulator capacitors, because
they have a high capacitance-to-volume ratio and are fairly stable over temperature. The input capacitor must
also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC bias
across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support the
maximum input voltage. Common-standard ceramic-capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V, or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. Equation 38 calculates the input
voltage ripple. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒSW = 600 kHz, yields an input
voltage ripple of 331 mV and a RMS input ripple current of 1.74 A.
ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 3.5 A
3.3 V
´
6V
(6 V
- 3.3 V )
6V
= 1.74 A
(37)
´ 0.25
I
3.5 A ´ 0.25
DVIN = OUT
=
= 331 mV
CIN ´ fSW
4.4 mF ´ 600 kHz
(38)
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Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA SIZE
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE (V)
DIALECTRIC
100
COMMENTS
GRM32 series
50
100
GRM31 series
50
50
100
VJ X7R series
50
100
X7R
100
C series C4532
50
100
C series C3225
50
50
100
X7R dielectric series
50
100
8.2.1.2.6 Bootstrap-Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. TI
recommends a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher
voltage rating.
8.2.1.2.7 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) is adjusted using an external voltage divider on the EN pin of the TPS54340Q1 device. The UVLO has two thresholds, one for power up when the input voltage is rising, and one for powerdown or brown-outs when the input voltage is falling. For the example design, the supply turns on and starts
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO-threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN pin. Equation 3 and Equation 4 calculate the necessary resistance values. For the
example application, a 365 kΩ between VIN and EN (RUVLO1) and a 86.6 kΩ between EN and ground (RUVLO2)
are required to produce the 8-V and 6.25-V start and stop voltages.
V
- VSTOP
5.75 V - 4.5 V
=
= 368 kW
RUVLO1 = START
IHYS
3.4 mA
(39)
RUVLO2 =
VENA
1.2 V
=
= 87.8 kW
VSTART - VENA
5.75 V - 1.2 V
+
1.2
m
A
+ I1
365 kW
RUVLO1
(40)
8.2.1.2.8 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Because of the
input current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low-output currents but
can also introduce noise immunity problems.
V
- 0.8 V
æ 3.3 V - 0.8 V ö
= 10.2 kW x ç
RHS = RLS x OUT
÷ = 31.9 kW
0.8 V
0.8 V
è
ø
(41)
28
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8.2.1.2.9 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10-times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1, must be calculated using Equation 42 and
Equation 43. For COUT, use a derated value of 70 μF. Use equations Equation 44 and Equation 45 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz.
Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of
modulator pole and the switching frequency. Equation 44 yields 33.1 kHz and Equation 45 gives 26.9 kHz. Use
the lower value of Equation 44 or Equation 45 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
3.5 A
fP(mod) =
=
= 2411 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 70 mF
(42)
f Z(mod) =
1
1
=
= 455 kHz
2 ´ p ´ RESR ´ COUT
2 ´ p ´ 5 mW ´ 70 mF
fco =
fp(mod) x f z(mod) =
fco =
fp(mod) x
fSW
2
=
2411 Hz x 455 kHz
2411 Hz x
600 kHz
2
(43)
= 33.1 kHz
(44)
= 26.9 kHz
(45)
To determine the compensation resistor, R4, use Equation 46. Assume the power-stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V, and 350 μA/V, respectively. R4 is calculated as 11.6 kΩ, and a standard value of 11.5 kΩ is selected.
Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
ö
VOUT
æ 2 ´ p ´ fco ´ COUT ö æ
ö
3.3 V
æ 2 ´ p ´ 26.9 kHz ´ 70 mF ö æ
R4 = ç
÷ = ç
÷ x ç
÷ x ç 0.8 V x 350 mA / V ÷ = 11.6 kW
gmps
V
x
gmea
12
A
/
V
è
ø è
ø
è
ø è REF
ø
(46)
1
1
=
= 5740 pF
C5 =
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 11.5 kW x 2411 Hz
(47)
A compensation pole is implemented if desired by adding capacitor C8 in parallel with the series combination of
R4 and C5. Use the larger value calculated from Equation 48 and Equation 49 for C8 to set the compensation
pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
70 mF x 5 mW
=
= 30.4 pF
C8 = OUT
R4
11.5 kW
(48)
1
1
=
= 46.1 pF
C8 =
R4 x f sw x p
11.5 kW x 600 kHz x p
(49)
8.2.1.2.10 Power Dissipation Estimate
The following formulas estimate the power dissipation of the TPS54340-Q1 device under continuous-conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuousconduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). For example calculations of the design example with the 12-V typical input voltage, see
Equation 50 through Equation 53.
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æV
ö
3.3 V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 3.5 A 2 ´ 92 mW ´
= 0.31 W
12 V
è VIN ø
(50)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
(51)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 600 kHz = 0.022 W
(52)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
where
•
•
•
•
•
•
•
•
IOUT is the output current (A)
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
ƒSW is the switching frequency (Hz)
trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
(53)
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
(54)
For given TA,
TJ = TA + RTH ´ PTOT
(55)
For given TJ(max) = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
where
•
•
•
•
•
•
Ptot is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance of the package (°C/W)
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C)
(56)
Additional power losses occur in the regulator circuit due to the inductor AC and DC losses, the catch diode, and
PCB trace resistance impacting the overall efficiency of the regulator.
8.2.1.2.11 Discontinuous Conduction Mode and Eco-mode™ Boundary
With an input voltage of 12 V, the power supply enters discontinuous-conduction mode when the output current
is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The
input current draw is 237 μA with no load.
30
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10 V/div
1 A/div
8.2.1.3 Application Curves
C4: IOUT
VIN
20 mV/div
C3: VOUT ac coupled
VOUT
-3.3 V offset
Time = 100 ms/div
Time = 4 ms/div
Figure 35. Load Transient
Figure 36. Line Transient (8 V to 40 V)
5 V/div
C3
5 V/div
100 mV/div
C4
C1: VIN
C1: VIN
C3: EN
C3
2 V/div
C1
C2: VOUT
2 V/div
2 V/div
2 V/div
C1
C2
Time = 2 ms/div
Figure 37. Start-up With VIN
Figure 38. Start-up With EN
10 V/div
500 mA/div
C4: IL
C2: VOUT ac coupled
10 mV/div
10 V/div
C1
1 A/div
C2: VOUT
C2
Time = 2 ms/div
C1: SW
20 mV/div
C3: EN
C3
C2
C4
C1: SW
C1
C4: IL
C4
C2
C2: VOUT ac coupled
Time = 2 ms/div
Time = 2 ms/div
Figure 39. Output Ripple CCM
Figure 40. Output Ripple DCM
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10 V/div
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C1: SW
C1
C1: SW
C1
1 A/div
C4: IL
C4: IL
C4
C2: VOUT ac coupled
C3: VIN ac coupled
C2
200 mV/div
20 mV/div
200 mA/div
10 V/div
SLVSBZ1A – SEPTEMBER 2013 – REVISED NOVEMBER 2015
C2
C4
Time = 2 ms/div
Time = 2 ms/div
Figure 42. Input Ripple CCM
C1: SW
2 V/div
C1: SW
C1
200 mA/div
C4: IL
C4
C3: VIN ac coupled
20 mV/div
50 mV/div
500 mA/div
10 V/div
Figure 41. Output Ripple PSM
C3
C4
C4: IL
C3
C3: VOUT ac coupled
VIN = 5.5 V
VOUT = 5 V
Time = 2 ms/div
Time = 20 ms/div
Figure 43. Input Ripple DCM
Figure 44. Low Dropout Operation
IOUT = 1 A
EN Floating
2 V/div
2 V/div
IOUT = 100 mA
EN Floating
VIN
VIN
VOUT
VOUT
32
No Load
EN Floating
Time = 40 ms/div
Time = 40 ms/div
Figure 45. Low Dropout Operation
Figure 46. Low Dropout Operation
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90
80
80
70
70
Efficiency - %
100
90
Efficiency - %
100
60
50
40
30
20
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0.5
1.0
1.5
2.5
2.0
3.0
0
0.001
3.5
0.1
0.01
IO - Output Current - A
Figure 47. Efficiency vs Load Current
Figure 48. Light-Load Efficiency
90
80
80
70
70
Efficiency - %
100
90
Efficiency - %
36Vin
42Vin
IO - Output Current - A
100
60
50
40
30
20
1
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
6Vin
12Vin
24Vin
10
0
0
0.001
4.0
36Vin
42Vin
0.1
0.01
IO - Output Current - A
IO - Output Current - A
Figure 49. Efficiency vs Load Current
Figure 50. Light-Load Efficiency
0.8
20
60
Gain
0
0
-60
-20
-40
-120
-60
-180
1000
10000
100000
1000000
Output Voltage Deviation - %
120
Phase - degree
Phase
40
100
1
1
180
60
10
6Vin
12Vin
24Vin
10
0
Gain - dB
60
0.6
0.4
0.2
0
-0.2
0.4
-0.6
-0.8
-1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
Frequency - Hz
Figure 51. Overall Loop-Frequency Response
Figure 52. Regulation vs Load Current
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Output Voltage Deviation - %
0.3
0.2
0.1
0
-0.1
0.2
-0.3
5
10
15
20
25
30
35
40
45
VIN - Input Voltage - V
Figure 53. Regulation vs Input Voltage
8.2.2 Inverting Power Supply
The TPS54340-Q1 device can be used to convert a positive input voltage to a negative output voltage. Example
applications are amplifiers requiring a negative power supply. For a more detailed example, see SLVA317.
VIN
+
Cin
Cboot
Lo
Cd
VIN
BOOT
GND
SW
R1
+
GND
TPS54340-Q1
R2
FB
Co
VOUT
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Figure 54. TPS54340-Q1 Inverting Power Supply from Application Note (SLVA317)
34
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8.2.3 Split-Rail Power Supply
The TPS54340-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative
output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and
negative voltage power supply. For a more detailed example, see SLVA369.
VOPOS
+
VIN
Copos
+
Cin
Cboot
BOOT
VIN
GND
SW
Lo
Cd
R1
GND
+
Coneg
R2
TPS54340-Q1
VONEG
FB
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Figure 55. TPS54340-Q1 Split-Rail Power Supply Based on Application Note (SLVA369)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 4.5 V to 42V. This input supply must
remain within this range. If the input supply is located more than a few inches from the TPS54340-Q1 converter,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 56 for a PCB layout example.
•
•
•
•
•
•
•
To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode
of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the output inductor.
Because the SW connection is the switching node, the catch diode and output inductor should be located
close to the SW pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
The GND pin should be tied directly to the power pad under the IC and the PowerPAD™. The PowerPAD
should be connected to internal PCB ground planes using multiple vias directly under the IC.
For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and
routed with minimal lengths of trace.
The additional external components can be placed approximately as shown.
It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout has
been shown to produce good results, and is meant as a guideline.
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10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
BOOT
Catch
Diode
SW
VIN
GND
EN
COMP
RT/CLK
FB
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 56. PCB Layout Example
10.3 Estimated Circuit Area
Boxing in the components in the design of Figure 34, the estimated PCB area is 1.025 in2 (661 mm2). This area
does not include test points or connectors. If the area must be reduced, then this can be done by using a two
sided assembly, and replacing the 0603 sized passives with a smaller-sized equivalent.
36
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Creating GSM Power Supply from TPS54260, SLVA412.
• Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511, SLVA464.
• Create an Inverting Power Supply from a Step-Down Regulator, SLVA317.
• Create a Split-Rail Power Supply with a Wide Input Voltage Buck Regulator, SLVA369.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54340QDDAQ1
NRND
SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54340Q
TPS54340QDDARQ1
NRND
SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54340Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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