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TPS54341
SLVSC61A – NOVEMBER 2013 – REVISED OCTOBER 2016
TPS54341 4.5-V to 42-V Input, 3.5-A Step-Down
DC-DC Converter With Soft-Start And Eco-Mode™
1 Features
3 Description
•
The TPS54341 device is a 42-V, 3.5-A step-down
regulator with an integrated high-side MOSFET. The
device survives load-dump pulses up to 45 V per ISO
7637. Current mode control provides simple external
compensation and flexible component selection. A
low-ripple pulse-skip mode reduces the no-load
supply current to 152 μA. Shutdown supply current is
reduced to 2 μA when the enable pin is pulled low.
1
•
•
•
•
•
•
•
•
•
•
•
•
High Efficiency at Light Loads with Pulse Skipping
Eco-mode™
87-mΩ High-Side MOSFET
152-μA Operating Quiescent Current and
2-μA Shutdown Current
100-kHz to 2.5-MHz Adjustable Switching
Frequency
Synchronizes to External Clock
Low Dropout at Light Loads with Integrated BOOT
Recharge FET
Adjustable UVLO Voltage and Hysteresis
UV and OV Power-Good Output
Adjustable Soft-Start and Sequencing
0.8-V 1% Internal Voltage Reference
10-Pin WSON with Thermal Pad Package
–40°C to 150°C TJ Operating Range
Supported by WEBENCH® Software Tool
2 Applications
•
•
•
•
Industrial Automation and Motor Control
Vehicle Accessories: GPS and Entertainment (see
Creating GSM/GRPS Power Supply from
TPS54260, SLVA412)
USB-Dedicated Charging Ports and Battery
Chargers (see Creating a Universal Car Charger
for USB devices From the TPS54240 and
TPS2511, SLVA464)
12-V and 24-V Industrial, Automotive and
Communications Power Systems
Undervoltage lockout is internally set at 4.3 V but can
increase using an external resistor divider at the
enable pin. The output voltage startup ramp is
controlled by the soft start pin that can also be
configured for sequencing/tracking. An open-drain
power-good signal indicates the output is within 93%
to 106% of the nominal voltage.
A wide adjustable switching-frequency range allows
for optimization of either efficiency or external
component size. Cycle-by-cycle current limit,
frequency foldback and thermal shutdown protects
internal and external components during an overload
condition.
The TPS54341 device is available in a 10-pin 4-mm ×
4-mm WSON package.
Device Information(1)
PART NUMBER
TPS54341
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
PACKAGE
WSON (10)
Efficiency vs Load Current
100
VIN
PWRGD
36 V to 12 V
95
TPS54341
RT/CLK
SS/TR
90
BOOT
SW
VOUT
COMP
FB
Efficiency (%)
EN
85
12 V to 3.3 V
80
12 V to 5 V
75
70
VOUT = 12 V, fsw = 620 kHz,
VOUT = 5 V and 3.3 V, f sw = 400 kHz
65
GND
60
0
Copyright © 2016, Texas Instruments Incorporated
0.5
1
1.5
2
IO - Output Current (A)
2.5
3
3.5
C099
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54341
SLVSC61A – NOVEMBER 2013 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
13
27
8
Application and Implementation ........................ 28
8.1 Application Information .......................................... 28
8.2 Typical Application .................................................. 28
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Example .................................................... 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
43
43
12 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
Changes from Original (November 2013) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SLVSC61A – NOVEMBER 2013 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
DPR Package
10-Pin WSON
Top View
BOOT
1
10
PWRGD
VIN
2
9
SW
EN
3
8
GND
SS/TR
4
7
COMP
RT/CLK
5
6
FB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO
BOOT
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below
the minimum required to operate the high-side MOSFET, the gate drive switches off until the
capacitor refreshes.
COMP
7
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
EN
3
I
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust
the input undervoltage lockout with two resistors. See Enable and Adjusting Undervoltage Lockout
for more information.
Inverting input of the transconductance (gm) error amplifier.
FB
6
I
GND
8
—
Ground
PWRGD
10
O
Power Good is an open drain output that asserts low if the output voltage is out of regulation due to
thermal shutdown, dropout, over-voltage or EN shut down
RT/CLK
5
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when
using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal
amplifier is disabled and the pin is a high-impedance clock input to the internal PLL. If clocking
edges stop, the internal amplifier re-enables and the operating mode returns to resistor frequency
programming.
SS/TR
4
I
Soft-start and tracking. An external capacitor connected to this pin sets the output rise time.
Because the voltage on this pin overrides the internal reference, SS/TR can be used for tracking
and sequencing.
SW
9
I
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad
—
—
VIN
2
I
The GND pin must be electrically connected to the exposed pad on the printed circuit board for
proper operation.
Input supply voltage with 4.5-V to 42-V operating range.
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SLVSC61A – NOVEMBER 2013 – REVISED OCTOBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
45
EN
–0.3
8.4
BOOT
UNIT
53
FB
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
45
–2
45
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Input voltage
BOOT-SW
Output voltage
8
SW
SW, transient (10 ns)
(1)
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
Supply input voltage
4.5
42
V
VO
Output voltage
0.8
41.1
V
IO
Output current
0
3.5
A
TJ
Junction Temperature
–40
150
°C
6.4 Thermal Information
TPS54341
THERMAL METRIC (1) (2)
DPR (WSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
35.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.1
°C/W
RθJB
Junction-to-board thermal resistance
12.3
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
12.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.3
4.48
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout threshold
4.5
Rising
4.1
Internal undervoltage lockout threshold hysteresis
42
V
V
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
2.25
4.5
Operating: nonswitching supply current
FB = 0.9 V, TA = 25°C
152
200
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
Enable threshold = –50 mV
Hysteresis current
Enable to COMP active
1.1
Enable threshold = 50 mV
V
–4.6
–0.58
–1.2
–1.8
–2.2
–3.4
–4.5
VIN = 12 V, TA = 25°C
μA
μA
540
µs
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
87
185
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gm)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
Error amplifier transconductance (gm)
during soft-start
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
Error amplifier DC gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source and sink
V(COMP) = 1 V, 100-mV overdrive
COMP to SW current transconductance
50
nA
350
μMhos
77
μMhos
10000
V/V
2500
kHz
±30
μA
12
A/V
CURRENT LIMIT
Current limit threshold
All VIN and temperatures, open loop (1)
4.5
5.5
6.8
All temperatures, VIN = 12 V, open loop (1)
4.5
5.5
6.3
VIN = 12 V, TA = 25°C, open loop (1)
5.2
5.5
5.9
Current limit threshold delay
A
60
ns
176
°C
12
°C
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
ƒSW
Switching frequency
100
RT = 200 kΩ
Switching frequency range using CLK mode
450
500
160
Minimum CLK input pulse width
2500
kHz
550
kHz
2300
kHz
15
RT/CLK high threshold
1.55
RT/CLK low threshold
0.5
ns
2
V
1.2
V
RT/CLK falling edge to SW rising edge delay
Measured at 500 kHz with RT resistor in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
Charge current
VSS/TR = 0.4 V
1.7
µA
SS/TR-to-FB matching
VSS/TR = 0.4 V
42
mV
SS/TR-to-reference crossover
98% nominal
1.16
V
SS/TR discharge current (overload)
FB = 0 V, VSS/TR = 0.4 V
354
µA
SS/TR discharge voltage
FB = 0 V
54
mV
SOFT START AND TRACKING (SS/TR PIN)
(1)
Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PWRGD PIN)
6
FB threshold for PWRGD low
FB falling
FB threshold for PWRGD high
FB rising
93%
FB threshold for PWRGD low
FB rising
108%
FB threshold for PWRGD high
FB falling
106%
Hysteresis
FB falling
2.5%
Output high leakage
VPWRGD = 5.5 V, TA = 25°C
10
nA
On resistance
IPWRGD = 3 mA, VFB < 0.79 V
45
Ω
Minimum VIN for defined output
VPWRGD < 0.5 V, IPWRGD = 100 µA
0.9
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90%
2
V
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6.6 Typical Characteristics
0.814
VFB - Voltage Reference (V)
RDSON - Static Drain-Source
On-State Resistance ( )
0.25
0.2
0.15
0.1
0.05
BOOT-SW = 3 V
0.809
0.804
0.799
0.794
0.789
V
VIN
12VV
IN ==12
BOOT-SW = 6 V
0
0.784
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
150
±50
±25
Figure 1. On Resistance vs Junction Temperature
25
50
75
100
125
150
C002
Figure 2. Voltage Reference
vs Junction Temperature
6.5
100
6.3
90
6.1
VOUT
9 ¦SW = 600 kHZ
80
5.9
70
5.7
Efficiency (%)
High Slide Switch Current (A)
0
TJ ± Junction Temperature (ƒC)
C001
5.5
5.3
5.1
4.9
60
50
40
30
4.7
4.5
±50
±25
0
25
50
75
100
125
Vin == 77V
V
V
IN
Vin
= 12
12V
V
V
IN =
V
V
Vin
= 24
24V
IN =
V
V
IN =
Vin
= 36
36V
20
VIN ==12
VIN
12VV
10
150
TJ Junction - Temperature (ƒC)
0
0.001
C003
0.01
0.1
1
Output Current (A)
Figure 3. Switch Current Limit
vs Junction Temperature
Figure 4. Switch Current Limit vs Input Voltage
500
550
540
FSW - Switching Frequency (kHz)
FS - Switching Frequency (kHz)
C004
530
520
510
500
490
480
470
460
RT = 200 kkOhm,
, VIN VIN
= 12=V12 V
450
±50
±25
0
25
50
75
100
TJ Junction - Temperature (ƒC)
125
450
400
350
300
250
200
150
150
C005
100
200
300
400
500
600
700
800
900
RT/CLK - Resistance (k )
Figure 5. Switching Frequency
vs Junction Temperature
1000
C006
Figure 6. Switching Frequency vs
RT/CLK Resistance Low Frequency Range
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Typical Characteristics (continued)
500
450
2000
400
gm - uA/V
FSW - Switching Frequency (kHz)
2500
1500
1000
350
300
500
250
VIN
12VV
VIN ==12
0
200
0
50
100
150
200
RT/CLK - Resistance (k )
±50
±25
0
25
50
75
100
125
150
TJ ± Junction Temperature (ƒC)
C007
Figure 7. Switching Frequency vs
RT/CLK Resistance High Frequency Range
C008
Figure 8. EA Transconductance
vs Junction Temperature
120
1.3
110
1.27
EN - Threshold (V)
100
gm - uA/V
90
80
70
60
50
40
VIN
12VV
VIN ==12
VIN
12VV
VIN ==12
20
1.15
±50
±25
0
25
50
75
100
125
150
TJ ± Junction Temperature (ƒC)
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
C009
Figure 9. EA Transconductance During Soft-Start
vs Junction Temperature
150
C010
Figure 10. EN Pin Voltage vs Junction Temperature
±3.5
±0.5
±3.7
±0.7
±3.9
±0.9
±4.1
±1.1
Current IEN (uA)
Current IEN (uA)
1.21
1.18
30
±4.3
±4.5
±4.7
±4.9
±5.1
±1.3
±1.5
±1.7
±1.9
±2.1
±5.3
VIN
12V,
V,IEN
IEN
= Threshold
+ 50
mV
V
= Threshold
+ 50
mV
IN ==12
±5.5
±2.3
VIN
12V,
V,IEN
IEN
Threshold
+ 50
VIN ==12
==
Threshold
- 50
mVmV
±2.5
±50
±25
0
25
50
75
100
TJ ± Junction Temperature (ƒC)
125
150
±50
±25
0
25
50
75
100
TJ ± Junction Temperature (ƒC)
C011
Figure 11. EN Pin Current vs Junction Temperature
8
1.24
125
150
C012
Figure 12. EN Pin Current vs Junction Temperature
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Typical Characteristics (continued)
100.0
±2.5
Nominal Switching Frequency (%)
±2.7
IEN Hysteresis (uA)
±2.9
±3.1
±3.3
±3.5
±3.7
±3.9
±4.1
±4.3
12VV
VVIN
IN ==12
75.0
50.0
25.0
V
Vsense
Falling
SENSE Falling
Vsense
Falling
V
SENSE Rising
0.0
±4.5
±50
±25
0
25
50
75
100
125
0.0
150
TJ ± Junction Temperature (ƒC)
0.2
0.4
0.5
0.6
0.7
0.8
C014
Figure 14. Switching Frequency vs FB
3
2.5
2.5
Supply Current IVIN (uA)
3
2
1.5
1
2
1.5
1
0.5
VIN
T
2512°CV
J ==
0.5
0
VIN
12VV
V
IN ==12
0
5
10
0
15
20
25
30
35
40
VIN - Input Voltage (ƒC)
±50
±25
0
25
50
75
100
125
45
C016
150
TJ ± Junction Temperature (ƒC)
C015
Figure 16. Shutdown Supply Current
vs Input Voltage (VIN)
Figure 15. Shutdown Supply Current
vs Junction Temperature
210
210
190
190
Supply Current IVIN (uA)
Supply Current IVIN (uA)
0.3
VSENSE (V)
Figure 13. EN Pin Current Hysteresis
vs Junction Temperature
Supply Current IVIN (uA)
0.1
C013
170
150
130
170
150
130
110
110
90
90
70
VIN
T
2512°CV
J ==
VIN
12VV
V
IN ==12
0
70
5
10
15
20
25
30
35
40
VIN - Input Voltage (ƒC)
±50
±25
0
25
50
75
100
TJ ± Junction Temperature (ƒC)
Figure 17. VIN Supply Current
vs Junction Temperature
125
45
C018
150
C017
Figure 18. VIN Supply Current vs Input Voltage
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2.6
4.5
2.5
4.4
2.4
4.3
2.3
4.2
VIN (V)
VI(BOOT-PH) (V)
Typical Characteristics (continued)
2.2
4.1
2.1
4
2
3.9
UVLO Start Switching
BOOT-PH UVLO Falling
3.8
1.9
UVLO Stop Switching
BOOT-PH UVLO Rising
3.7
1.8
±50
±25
0
25
50
75
100
125
±50
150
TJ ± Junction Temperature (ƒC)
±25
75
100
125
150
C020
FB
108
Power Good Threshold (%)
70
Power Good Resistance ( )
50
110
80
60
50
40
30
20
106
FB Falling
104
102
100
10
VIN = 12 V
98
96
FB Rising
94
92
90
VIN
12VV
VIN ==12
0
FB Falling
88
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
C021
Figure 21. PWRGD On Resistance
vs Junction Temperature
150
C022
Figure 22. PWRGD Threshold
vs Junction Temperature
60
900
VVIN
1212V,V,2525°C°C
IN = =
55
SS/TR to FB Offset (mV)
800
700
Offset (mV)
25
Figure 20. Input Voltage UVLO
vs Junction Temperature
Figure 19. BOOT-SW UVLO
vs Junction Temperature
600
500
400
300
200
50
45
40
35
30
100
25
0
20
0
100
200
300
400
500
600
700
SS/TR (mV)
800
VIN
12V,
V,FB
FB==0.4
0.4VV
V
IN ==12
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
C024
Figure 23. SS/TR to FB Offset vs FB
10
0
TJ ± Junction Temperature (ƒC)
C019
150
C025
Figure 24. SS/TR to FB Offset vs Temperature
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Typical Characteristics (continued)
5.6
Start
Stop
5.5
5.4
VIN (V)
5.3
5.2
5.1
Dropout
Voltage
5.0
4.9
Dropout
Voltage
4.8
4.7
4.6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
C026
Figure 25. 5-V Start and Stop Voltage (see Low Dropout Operation and Bootstrap Voltage (BOOT))
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7 Detailed Description
7.1 Overview
The TPS54341 device is a 42-V 3.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. The device implements constant-frequency current-mode control which reduces output capacitance
and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz
allows for either efficiency or size optimization when selecting the output filter components. The switching
frequency is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phaselocked loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turn-on to a falling edge of an
external clock signal.
The TPS54341 device has a default input-startup voltage of 4.3 V typical. The EN pin adjusts the input-voltage
undervoltage-lockout (UVLO) threshold with two external resistors. An internal-pullup current source enables
operation when the EN pin is floating. The operating current is 152 μA under a no-load condition when not
switching. When the device is disabled, the supply current is 2 μA.
The integrated 87-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54341 device reduces the
external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is
monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54341 device to operate at high
duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage
of the application. The minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET turns off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft-start/tracking) pin minimizes inrush currents or provides power-supply sequencing during power
up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistor divider can be
connected to the pin for critical power-supply sequencing requirements. The SS/TR pin is discharged before the
output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO fault, or a
disabled condition. When the overload condition is removed, the soft-start circuit controls the recovery from the
fault output level to the nominal regulation voltage. A frequency-foldback circuit reduces the switching frequency
during startup and overcurrent fault conditions to help maintain control of the inductor current.
12
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7.2 Functional Block Diagram
EN
PWRGD
VIN
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Skip
Error
Amplifier
FB
Boot
UVLO
Current
Sense
PWM
Comparator
BOOT
SS/TR
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
10/9/2013 A0272435
GND
POWERPAD
RT/ CLK
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54341 device uses fixed-frequency peak-current-mode control with adjustable switching frequency. The
output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turn-on of the high-side power switch. The error amplifier
output at the COMP pin controls the high-side power switch current. When the high-side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54341 device adds a compensating ramp to the MOSFET switch current-sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.
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Feature Description (continued)
7.3.3 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54341 device provides an integrated bootstrap-voltage regulator. A small capacitor between the BOOT
and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor refreshes when the
high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54341
device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at
high output voltages, the low-side MOSFET is disabled at 24 V output and re-enabled when the output reaches
21.5 V.
Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET remains on for
many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of the
switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is
mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode
voltage, and the printed circuit-board resistance.
The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is
plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty-cycle (low dropout) conditions, inductor current-ripple increases when the BOOT capacitor
recharges resulting in an increase in output-voltage ripple. Increased ripple occurs when the off time required to
recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle PWM control.
At heavy loads, the minimum input voltage must increase to ensure a monotonic startup. Equation 1 calculates
the minimum input voltage for this condition.
VOUT(max) = D(max) x (VIN(min) - IOUT(max) x RDS(on) + Vd ) - Vd + IOUT(max) x Rdc
where
•
•
•
•
•
•
D(max) ≥ 0.9
Vd = forward drop of the catch diode
VBOOT = (1.41 × VIN – 0.554 – Vd × ƒSW – 1.847 × 103 × IB2SW) / (1.41 + ƒSW)
R DS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246)
IB2SW = 100 µA
VB2SW = VBOOT + Vd
(1)
7.3.4 Error Amplifier
A transconductance error amplifier controls the TPS54341 device voltage-regulation loop. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation,
the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.5 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap-reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. Using 1% tolerance or better divider resistors is recommended. Select
the low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors from the FB input current may become noticeable.
14
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Feature Description (continued)
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(2)
7.3.6 Enable and Adjusting Undervoltage Lockout
The TPS54341 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54341 device disables when the VIN pin voltage falls below 4 V or when the
EN pin voltage is below 1.2 V. The EN pin has an internal pullup-current source, I1, of 1.2 μA that enables
operation of the TPS54341 device when the EN pin floats.
If an application requires a higher undervoltage-lockout (UVLO) threshold, use the circuit shown in Figure 26 to
adjust the input-voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin pulls below 1.2 V, the 3.4-μA
IHYS current is removed. This additional current facilitates adjustable input-voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 o 9 V) and withstand high input
voltages (for example, 40 V), the EN pin can experience a voltage greater than the absolute maximum voltage of
8.4 V during the high-input voltage condition. To avoid exceeding this voltage when using the EN resistors, the
EN pin is clamped internally with a 5.8-V Zener diode capable of sinking up to 150 μA.
- VSTOP
V
RUVLO1 = START
IHYS
(3)
RUVLO2 =
VENA
VSTART - VENA
+ I1
RUVLO1
(4)
VIN
TPS54341
i1
TPS54341
VIN
ihys
RUVLO1
R UVLO1
EN
EN
VEN
RUVLO2
10 kW
Node
5.8 V
R UVLO2
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Adjustable UVLO
Figure 27. Internal EN Pin Clamp
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Feature Description (continued)
7.3.7 Soft-Start/Tracking Pin (SS/TR)
The TPS54341 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on the
SS/TR pin to ground implements a soft-start time. The TPS54341 device has an internal pullup-current source of
1.7 μA that charges the external soft-start capacitor. The calculations for the soft-start time (10% to 90%) are
shown in Equation 5. The voltage reference (VREF) is 0.8 V and the soft-start current (ISS) is 1.7 μA. The soft-start
capacitor should remain lower than 0.47 μF and greater than 0.47 nF.
T (ms) ´ ISS (µA)
CSS (nF) = SS
VREF (V) ´ 0.8
(5)
At power up, the TPS54341 device does not start switching until the soft-start pin discharges to less than 54 mV
to ensure a proper power-up, see Figure 28.
Also, during normal operation, the TPS54341 device stops switching and the SS/TR must discharge to 54 mV,
when the VIN UVLO is exceeded, the EN pin pulls below 1.2 V, otherwise a thermal shutdown event occurs.
The FB voltage follows the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).
The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.
Figure 28. Operation of SS/TR Pin When Starting
7.3.8 Sequencing
Many of the common power-supply sequencing methods are implemented using the SS/TR, EN, and PWRGD
pins. The sequential method is implemented using an open-drain output of a power-on reset pin of another
device. The sequential method is illustrated in Figure 29 using two TPS54341 devices. The power good is
connected to the EN pin on the TPS54341 device which enables the second power supply once the primary
supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply
provides a 1-ms startup delay. Figure 30 shows the results of Figure 29.
16
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Feature Description (continued)
TPS54341
EN
TPS54341
PWRGD
EN
SS /TR
SS /TR
PWRGD
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Schematic for Sequential Startup
Sequence
Figure 30. Sequential Startup Using
EN and PWRGD
TPS54160
TPS54341
3
EN
4
SS/TR
6
PWRGD
TPS54341
TPS54160
3
EN
4
SS/TR
6
PWRGD
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Schematic for Ratiometric Startup
Sequence
Figure 32. Ratiometric Startup Using
Coupled SS/TR pins
Figure 31 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the pullup
current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.
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Feature Description (continued)
TPS54341
EN
VOUT 1
SS/TR
PWRGD
TPS54341
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Schematic for Ratiometric and Simultaneous Startup Sequence
Ratiometric and simultaneous power-supply sequencing is implemented by connecting the resistor network of R1
and R2 shown in Figure 33 to the output of the power supply that must be tracked or another voltage reference
source. Using Equation 6 and Equation 7, calculate the tracking resistors to initiate the VOUT2 slightly before,
after, or at the same time as VOUT1. Equation 8 is the voltage difference between VOUT1 and VOUT2 at the 95% of
nominal output regulation.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset
(VSSoffset) in the soft-start circuit and the offset created by the pullup-current source (ISS) and tracking resistors,
the VSSoffset and ISS are included as variables in the equations.
To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in a
positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO, or thermal shutdown
fault, careful selection of the tracking resistors is required to ensure the device restarts after a fault. The
calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9 to ensure the
device recovers from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the VSSoffset becomes larger as
the soft-start circuits gradually hands-off the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference.
V
+ DV VSSoffset
R1 = OUT2
´
VREF
ISS
(6)
R2 =
VREF ´ R1
VOUT2 + DV - VREF
(7)
DV = VOUT1 - VOUT2
18
(8)
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Feature Description (continued)
R1 > 2800 ´ VOUT1 - 180 ´ DV
(9)
Figure 34. Ratiometric Startup With Tracking
Resistors
Figure 35. Ratiometric Startup With Tracking
Resistors
Figure 36. Simultaneous Startup With Tracking Resistor
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54341 device is adjustable over a wide range from 100 to 2500 kHz by
placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size,
one typically sets the switching frequency as high as possible. Tradeoffs of the conversion efficiency, maximum
input voltage, and minimum controllable on time must be considered. The minimum controllable on time is
typically 135 ns which limits the maximum operating frequency in applications with high input-to-output step-down
ratios. The maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed
discussion of the maximum switching frequency is provided in the next section.
101756
RT (kW) =
ƒSW (kHz)1.008
(10)
ƒSW (kHz) =
92417
RT (kW)0.991
(11)
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Feature Description (continued)
7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
The TPS54341 device implements peak-current-mode control in which the COMP pin voltage controls the peak
current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage
are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side
switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The error amplifier output clamps internally at a level which sets the
peak switch current limit. The TPS54341 device provides an accurate current limit threshold with a typical current
limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in Figure 37.
Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 37. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54341
device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin
voltage falls from 0.8 V to 0 V. The TPS54341 device uses a digital frequency foldback to enable synchronization
to an external clock during normal startup and fault conditions. During short-circuit events, the inductor current
can exceed the peak current-limit because of the high input voltage and the minimum controllable on time. When
the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off
time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle
providing more time for the inductor current to ramp down.
With a maximum frequency-foldback ratio of 8, there is a maximum frequency at which frequency-foldback
protection controls the inductor current. Equation 13 calculates the maximum switching frequency at which the
inductor current remains under control when VOUT is forced to VOUT(SC). The selected operating frequency should
not exceed the calculated value.
Equation 12 calculates the maximum switching-frequency limitation set by the minimum controllable on time and
the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output voltage at maximum input voltage.
20
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Feature Description (continued)
ö
÷
÷
tON
ø
æ
ö
´
+
+
I
R
V
V
CL
dc
d
OUT(sc )
ƒ
÷
= DIV ´ ç
tON ç VIN - ICL ´ RDS(on ) + Vd ÷
è
ø
ƒSW (max skip ) =
ƒSW(shift)
1
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
(12)
where
•
•
•
•
•
•
•
•
•
•
IO = output current
ICL = current limit
Rdc = inductor resistance
VIN = maximum input voltage
VOUT = output voltage
VOUT(SC) = output voltage during short
Vd = diode voltage drop
RDS(on) = switch on resistance
tON = controllable on time
ƒDIV, frequency divide equals (1, 2, 4, or 8)
(13)
7.3.11 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V, and
must have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 to 2300 kHz. The rising
edge of the SW synchronizes to the falling edge of RT/CLK pin signal. Design the external synchronization circuit
such that the default-frequency set resistor connects from the RT/CLK pin to ground when the synchronization
signal is off. When using a low-impedance signal source, the frequency-set resistor connects in parallel with an
AC-coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 38. The two resistors in
the series provide the default frequency-setting resistance when the signal source is turned off. The sum of the
resistance sets the switching frequency close to the external CLK frequency. AC-coupling the synchronization
signal the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK pulls above the PLL threshold the TPS54341 device switches from the RT-resistor
free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition
from the PLL mode to the resistor-programmed mode, the switching frequency falls to 150 kHz and then
increases or decreases to the resistor-programmed frequency when the 0.5-V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback which enables synchronization to an external clock during normal startup
and fault conditions. Figure 39, Figure 40 and Figure 41 show the device synchronized to an external system
clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
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Feature Description (continued)
TPS54341
TPS54341
RT/CLK
RT/CLK
PLL
PLL
RT
Hi-Z
Clock
Source
Clock
Source
RT
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Synchronizing to a System Clock
Figure 39. Plot of Synchronizing in CCM
Figure 40. Plot of Synchronizing in DCM
Figure 41. Plot of Synchronizing in Eco-mode
7.3.12 Power Good (PWRGD Pin)
The PWRGD pin is an open-drain output. Once the FB pin is between 93% and 106% of the internal voltage
reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is
5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull up
voltage source when the PWRGD pin is asserted low. A lower pullup resistance reduces the switching noise
seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but
with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input
voltage approaches 3 V.
22
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Feature Description (continued)
The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
7.3.13 Overvoltage Protection
The TPS54341 device incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients in designs with low-output capacitance.
For example, when the power-supply output is overloaded the error amplifier compares the actual output voltage
to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak
current-limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power-supply output voltage increases
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high-side MOSFET disables immediately to minimize output
overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal
voltage reference, the high-side MOSFET resumes normal operation.
7.3.14 Thermal Shutdown
The TPS54341 device provides an internal thermal shutdown to protect the device when the junction
temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the
thermal trip threshold. Once the die temperature falls below 164°C, the device reinitiates the power-up sequence
controlled by discharging the SS/TR pin.
7.3.15 Small-Signal Model for Loop Response
Figure 42 shows a simplified equivalent model for the TPS54341 control loop which is simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 350 μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor RO and
capacitor Co model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage source
between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response is evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for CCM operation.
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Feature Description (continued)
SW
VO
Power Stage
gmps 12 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
RO
FB
COUT
gmea
C2
R2
350 mA/V
C1
Figure 42. Small-Signal Model for Loop Response
7.3.16 Simple Small-Signal Model for Peak-Current-Mode Control
Figure 43 describes a simple small-signal model used to design the frequency compensation. The TPS54341
power stage is approximated by a voltage-controlled current source (duty-cycle modulator) supplying current to
the output capacitor and load resistor. The control to output transfer function is shown in Equation 14 and
consists of a DC gain, one dominant pole, and one equivalent-series-resistor (ESR) zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 42) is the power stage
transconductance, gmPS. The gmPS for the TPS54341 device is 16 A/V. The low-frequency gain of the power
stage is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load seems problematic at first glance, but fortunately the dominant pole moves with the load
current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 43. As
the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same with varying load conditions. The type of output capacitor chosen determines whether the
ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum-electrolytic
capacitors can reduce the number frequency compensation components required to stabilize the overall loop
because the phase margin increases by the ESR zero of the output capacitor (see Functional Block Diagram).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 43. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
24
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Feature Description (continued)
æ
s
ç1 +
2p ´ ƒ Z
VOUT
= Adc ´ è
VC
æ
s
ç1 +
2p ´ ƒP
è
ö
÷
ø
ö
÷
ø
(14)
Adc = gmps ´ RL
ƒP =
ƒZ =
(15)
COUT
1
´ RL ´ 2p
(16)
COUT
1
´ RESR ´ 2p
(17)
7.3.17 Small Signal Model for Frequency Compensation
The TPS54341 device uses a transconductance amplifier for the error amplifier and supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 44. Type 2 circuits are typically implemented in high bandwidth power-supply designs using lowESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminumelectrolytic or tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to
the small signal model in Figure 44. The open-loop gain and bandwidth are modeled using the RO and CO shown
in Figure 44. See the Application Information section for a design example using a Type 2A network with a lowESR output capacitor.
Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power-supply requirements (go to www.ti.com/WEBENCH for more information).
VO
R1
FB
gmea
COMP
Type 2A
Type 2B
Type 1
VREF
R2
RO
CO
R3
C2
C1
R3
C2
C1
Figure 44. Types of Frequency Compensation
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Feature Description (continued)
Aol
A0
P1
Z1
P2
A1
BW
Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation
RO =
Aol (V / V )
gmea
gmea
CO =
2p ´ BW (Hz)
(18)
(19)
æ
ö
s
ç1 +
÷
2p ´ ƒ Z1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2
ƒ
2
ƒ
p
´
p
´
P1 ø è
P2 ø
è
R2
R1 + R2
R2
´ RO P R3 ´
R1 + R2
A0 = gm ea ´ RO ´
A1 = gm ea
P1 =
Z1 =
(21)
(22)
1
2p ´ Ro ´ C1
(23)
1
2p ´ R3 ´ C1
(24)
1
P2 =
Type 2A
2p ´ R3 P RO ´ (C2 + CO )
(25)
1
P2 =
Type 2B
2p ´ R3 P RO ´ CO
(26)
P2 =
26
(20)
1
Type 1
2p ´ RO ´ (C2 + CO )
(27)
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7.4 Device Functional Modes
7.4.1 Pulse Skip Eco-mode
The TPS54341 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency by
reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at
the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The
pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage-control loop responds to
the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET enables and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54341 device senses and controls peak switch current, not the average
load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 46 enters Eco-mode at 30-mA output current. As the load current approaches zero,
the device enters a pulse-skip mode during which it draws only 152-μA input quiescent current.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54341 is a 42 V, 3.5 A, step down regulator with an integrated high side MOSFET. Ideal applications
are: 12 V, 24 V Industrial, Automotive and Communications Power Systems.
8.2 Typical Application
PWRGD
PWRGD PULL UP
R8
+
DNP
DNPC10 DNPC3
2.2µF
2.2µF
C1
2.2µF
C2
2.2µF
R1
365k
5
SS/TR
2
J2
3
4
R3
162k
TP2
7
GND
GND
C13
0.01µF
2
1
J4
GND
R2
88.7k
2
1
EN
GND
R4
11.5k
VIN
EN
RT/CLK
PWRGD
BOOT
SW
SS/TR
FB
COMP
GND
PAD
TPS54341DPR
C8
47pF
10
TP9
C4
1
L1
6
3.3V 3.5A
0.1µF
9
TP5
FB
TP6
7443552560
5.6µH
8
D1
PDS560-13
GND
C6 DNPC7 DNPC9
47µF
100µF 47µF
+
C12
DNP
TP8
1
VOUT
2
GND
J1
GND
TP4
R5
31.6k
C5
5600pF
GND
J3
TP7
R7
49.9
1
C11
2
2
TP1
3
1
TP10 1.00k
2
2
GND
1
VIN
U1
1
6 V to 42 V
FB
R6
10.2k
TP3
GND
GND
2 SS/TR
1
SS/TR
GND
J5
GND
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Figure 46. 3.3-V Output TPS54341 Design Example
8.2.1 Design Requirements
This section illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. The necessary calculations can be done using WEBENCH or the excel spreadsheet
(SLVC452) located on the product. This design starts with the parameters in Table 1.
28
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Typical Application (continued)
Table 1. Design Parameters
PARAMETER
VALUE
Output voltage
3.3 V
Transient response 0.875 A to 2.625 A load step
ΔVOUT = 4%
Maximum output current
3.5 A
Input voltage
12 V nominal 6 V to 42 V
Output voltage ripple
0.5% of VOUT
Start input voltage (rising VIN)
5.75 V
Stop input voltage (falling VIN)
4.5 V
8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible because this produces the smallest solution size. High switching frequency allows
for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency-foldback protection.
Equation 12 and Equation 13 must be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54341 device. For this example, the output voltage is
3.3 V and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to
avoid pulse skipping from Equation 12. To ensure overcurrent runaway is not a concern during short circuits use
Equation 13 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 87
mΩ, a current-limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 46. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
fSW(max skip) =
æ 3.5 A x 21 mW + 3.3 V + 0.7 V ö
1
´ ç
÷ = 712 kHz
135ns
è 42 V - 3.5 A x 87 mW + 0.7 V ø
8
æ 4.7 A x 21 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 1260 kHz
135 ns
è 42 V - 4.7 A x 87 mW + 0.7 V ø
101756
RT (kW) =
= 161 kW
600 (kHz)1.008
fSW(shift) =
(28)
(29)
(30)
8.2.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 31.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer, however, the following guidelines may be used.
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For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest
standard value is 5.6 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE
7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54341 device which is nominally 5.5 A.
VIN(max ) - VOUT
VOUT
42 V – 3.3 V
3.3 V
´
=
´
= 4.8 µH
LO(min ) =
IOUT ´ KIND
VIN(max ) ´ ƒSW
3.5 A ´ 0.3
42 V ´ 600 kHz
(31)
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ ƒSW
(
=
3.3 V ´ (42 V – 3.3 V)
= 0.905 A
42 V ´ 5.6 µH ´ 600 kHz
æ
ç VOUT ´ VIN(max ) - VOUT
1
2
IL(rms ) = (IOUT ) +
´
12 çç VIN(max ) ´ LO ´ ƒSW
è
)÷ö
2
÷ =
÷
ø
(32)
2
(3.5 A )2 +
æ 3.3 V ´ (42 V – 3.3 V ) ö
1
´ ç
÷ = 3.5 A
ç
÷
12
è 42 V ´ 5.6 µH ´ 600 kHz ø
(33)
IL(peak ) = IOUT +
IRIPPLE
0.905 A
= 3.5 A +
= 3.95 A
2
2
(34)
8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for two clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A – 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a
minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 49. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
30
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Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and VI is the initial voltage. For this example, the worst case load step
will be from 2.625 A to 0.875 A. The output voltage increases during this load transition and the stated maximum
in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. VI is the initial capacitor
voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 36 yields a minimum
capacitance of 38.6 μF.
Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 37 yields 11.4 μF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the ESR should be less than 18 mΩ.
The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, a
100-μF ceramic capacitor with 5 mΩ of ESR is used. The derated capacitance is 70 µF, well above the minimum
required capacitance of 44.9 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 39 yields 261 mA.
2 ´ DIOUT
2 ´ 1.75 A
=
= 44.9 mF
COUT >
fSW ´ DVOUT 600 kHz x 0.13 V
(35)
((I ) - (I ) ) = 5.6 mH x (2.625 A - 0.875 A ) = 38.6 mF
x
(3.432 V - 3.3 V )
((V ) - (V ) )
2
OH
COUT > LO
2
2
f
2
2
2
2
I
1
1
´
8 ´ fSW æ VORIPPLE
ç
è IRIPPLE
V
16.5 mV
RESR < ORIPPLE =
IRIPPLE
0.905 A
COUT >
ICOUT(rms) =
2
OL
ö
÷
ø
=
1
1
= 11.4 mF
x
8 x 600 kHz
æ 16.5 mV ö
ç 0.905 A ÷
è
ø
(36)
(37)
= 18 mW
(
VOUT ´ VIN(max ) - VOUT
(38)
)=
12 ´ VIN(max ) ´ LO ´ fSW
3.3 V ´
(42 V
- 3.3 V )
12 ´ 42 V ´ 5.6 mH ´ 600 kHz
= 261 mA
(39)
8.2.2.4 Catch Diode
The TPS54341 device requires an external catch diode between the SW pin and GND. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54341
device.
For the example design, the PDS560 Schottky diode is selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the PDS560 is 0.55 V at 3.5 A.
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The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 is
used to calculate the total power dissipation, including conduction losses and AC losses of the diode.
The PDS560 diode has a junction capacitance of 90 pF at 42 V input voltage. Using Equation 40, the total loss in
the diode is 2.27 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD =
(V
IN(max ) - VOUT
)´ I
OUT
+
VIN(max )
(42 V
2
´ Vf d
- 3.3 V ) ´ 3.5 A x 0.55 V
42 V
C j ´ fSW ´ (VIN + Vf d)
=
2
+
90 pF x 600 kHz x (42 V + 0.55 V)2
= 2.27 W
2
(40)
8.2.2.5 Input Capacitor
The TPS54341 device requires a high-quality ceramic-type X5R or X7R input-decoupling capacitor with at least 3
μF of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater
than the maximum input current ripple of the TPS54341 device. The input ripple current can be calculated using
Equation 41.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V, or 100 V. For this example, two 2.2-μF 100-V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 41. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒSW = 600 kHz, yields
an input voltage ripple of 331 mV and a rms input ripple current of 1.74 A as seen in Equation 42.
ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 3.5 A
3.3 V
´
6V
´ 0.25
I
3.5 A ´ 0.25
DVIN = OUT
=
= 331 mV
CIN ´ fSW
4.4 mF ´ 600 kHz
32
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(6 V
- 3.3 V )
6V
= 1.74 A
(41)
(42)
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Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA SIZE
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE (V)
DIALECTRIC
100
COMMENTS
GRM32 series
50
100
GRM31 series
50
50
100
VJ X7R series
50
100
100
50
100
50
X7R
C series C4532
C series C3225
50
100
50
X7R dielectric series
100
8.2.2.6 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54341 device reach the current limit or excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 43 can be used to find the minimum slow-start time, TSS,
necessary to charge the output capacitor, COUT, from 10% to 90% of the output voltage, VOUT, with an average
slow-start current of ISSavg. In the example, to charge the effective output capacitance of 70 µF up to 3.3 V with
an average current of 1 A requires a 0.2-ms slow-start time.
Once the slow-start time is known, the slow-start capacitor value can be calculated using Equation 43. For the
example circuit, the slow-start time is not too critical because the output capacitor value is 100 μF which does not
require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of
3.5 ms which requires a 9.3-nF slow-start capacitor calculated by Equation 44. For this design, the next larger
standard value of 10 nF is used.
´ VOUT ´ 0.8
C
TSS > OUT
ISSavg
(43)
CSS (nF) =
TSS (ms) ´ ISS (µA)
1.7 µA
= 3.5 ms ´
= 9.3 nF
VREF (V) ´ 0.8
(0.8 V ´ 0.8 )
(44)
8.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor must have a 10 V or higher voltage
rating.
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8.2.2.8 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54341 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts
switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the
example application, a 365 kΩ between Vin and EN (RUVLO1) and a 88.7 kΩ between EN and ground (RUVLO2)
are required to produce the 8-V and 6.25-V start and stop voltages as seen in Equation 45 and Equation 46.
V
- VSTOP
5.75 V - 4.5 V
=
= 368 kW
RUVLO1 = START
IHYS
3.4 mA
(45)
RUVLO2 =
VENA
1.2 V
=
= 87.8 kW
VSTART - VENA
5.75 V - 1.2 V
+ 1.2 mA
+ I1
365 kW
RUVLO1
(46)
8.2.2.9 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain
the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems (see Equation 47).
V
- 0.8 V
æ 3.3 V - 0.8 V ö
= 10.2 kW x ç
RHS = RLS x OUT
÷ = 31.9 kW
0.8 V
0.8 V
è
ø
(47)
8.2.2.10 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least ten-times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 48 and
Equation 49. For COUT, use a derated value of 70 μF. Use equations Equation 50 and Equation 51 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz.
Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of
modulator pole and the switching frequency. Equation 50 yields 33.1 kHz and Equation 51 gives 26.9 kHz. Use
the lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated with Equation 48 through Equation 51. A resistor in series
with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms
the compensating pole.
IOUT(max )
3.5 A
fP(mod) =
=
= 2411 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 70 mF
(48)
f Z(mod) =
34
1
2 ´ p ´ RESR ´ COUT
fco =
fp(mod) x f z(mod) =
fco =
fp(mod) x
fSW
2
=
=
1
= 455 kHz
2 ´ p ´ 5 mW ´ 70 mF
2411 Hz x 455 kHz
2411 Hz x
600 kHz
2
= 33.1 kHz
= 26.9 kHz
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(49)
(50)
(51)
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To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 11.6 kΩ and a standard value of 11.5 kΩ is selected.
Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
æ 2 ´ p ´ ƒco ´ COUT
R4 = ç
ç
gmps
è
ö
æ
ö
VOUT
ö
3.3 V
æ 2 ´ p ´ 26.9 kHz ´ 70 µF ö æ
÷ ´ ç
´ç
÷ = ç
÷ = 11.6 kW
÷
÷
12 A / V
è
ø è 0.8 V ´ 350 µA / V ø
è VREF x gmea ø
ø
(52)
1
1
=
= 5740 pF
C5 =
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 11.5 kW x 2411 Hz
(53)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
70 mF x 5 mW
=
= 30.4 pF
C8 = OUT
R4
11.5 kW
(54)
1
1
C8 =
=
= 46.1 pF
R4 ´ ƒsw ´ p
11.5 kW ´ 600 kHz ´ p
(55)
8.2.2.11 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 340 mA. The power supply enters Eco-mode when the output current is lower than 30 mA. The input
current draw is 260 μA with no load.
8.2.2.12 Estimated Circuit Area
Boxing in the components in the design of Figure 46 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.
VIN
+
Cin
Cboot
Lo
VIN
Cd
BOOT
GND
SW
R1
+
GND
TPS54341
R2
FB
Co
VOUT
EN
COMP
SS/TR
RT/CLK
CSS
RT
Czero
Rcomp
Cpole
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Figure 47. TPS54341 Inverting Power Supply Based on the Application Note, SLVA317
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VOPOS
+
VIN
Copos
+
Cin
Cboot
BOOT
VIN
GND
SW
Lo
Cd
R1
GND
+
Coneg
R2
TPS54341
VONEG
FB
EN
COMP
SS/TR
Rcomp
RT/CLK
CSS
RT
Czero
Cpole
Copyright © 2016, Texas Instruments Incorporated
Figure 48. TPS54341 Split Rail Power Supply Based on the Application Note, SLVA369
8.2.2.13 Power Dissipation Estimate
The following formulas show how to estimate the TPS54341 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown in Equation 56 through Equation 59 with the 12 V typical
input voltage of the design example.
æV
ö
3.3 V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 3.5 A 2 ´ 87 mW ´
= 0.31 W
12 V
è VIN ø
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 600 kHz = 0.022 W
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
(56)
(57)
(58)
where
•
•
•
•
•
•
•
•
IOUT is the output current (A)
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
ƒSW is the switching frequency (Hz)
trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
(59)
Therefore, use Equation 60.
PTOT = PCOND + PSW + PGD + PQ = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
(60)
For given TA, use Equation 61.
TJ = TA + RTH ´ PTOT
(61)
For given TJ(MAX) = 150°C, use Equation 62.
36
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TA (max ) = TJ(max ) - RTH ´ PTOT
where
•
•
•
•
•
•
PTOT is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance (°C/W)
TJ(MAX) is maximum junction temperature (°C)
TA(MAX) is maximum ambient temperature (°C)
(62)
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
10 V/div
1 A/div
8.2.3 Application Curves
C4: IOUT
VIN
C3
C3: VOUT ac coupled
20 mV/div
100 mV/div
C4
-3.3 V offset
Time = 4 ms/div
Figure 50. Line Transient (8 V to 40 V)
Time = 100 ms/div
Figure 49. Load Transient
5 V/div
VOUT
C1: VIN
2 V/div
2 V/div
C1
C3: EN
C3
C2: VOUT
C2
Time = 2 ms/div
Figure 51. Startup With VIN
Figure 52. Startup With EN
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C2: VOUT ac coupled
10 mV/div
20 mV/div
10 V/div
C4: IL
500 mA/div
C1
1 A/div
10 V/div
C1: SW
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C2
C4
C1: SW
C1
C4: IL
C4
C2
C2: VOUT ac coupled
C1
10 V/div
C1: SW
Time = 2 ms/div
Figure 54. Output Ripple DCM
C1: SW
C1
1 A/div
C4: IL
C4: IL
C4
C2: VOUT ac coupled
C2
C3: VIN ac coupled
200 mV/div
20 mV/div
200 mA/div
10 V/div
Time = 2 ms/div
Figure 53. Output Ripple CCM
C2
C4
Time = 2 ms/div
Figure 56. Input Ripple CCM
C1: SW
C1
C4: IL
C4
C3: VIN ac coupled
200 mA/div
2 V/div
C1: SW
20 mV/div
50 mV/div
500 mA/div
10 V/div
Time = 2 ms/div
Figure 55. Output Ripple PSM
C3
C4
C4: IL
C3
C3: VOUT ac coupled
Time = 2 ms/div
Figure 57. Input Ripple DCM
38
VIN = 5.5 V
VOUT = 5 V
No Load
EN Floating
Time = 20 ms/div
Figure 58. Low Dropout Operation
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IOUT = 1 A
EN Floating
2 V/div
2 V/div
IOUT = 100 mA
EN Floating
VIN
VIN
VOUT
VOUT
Time = 40 ms/div
Figure 60. Low Dropout Operation
Time = 40 ms/div
Figure 59. Low Dropout Operation
100
100
VOUT A ïXï sU •SW = 600 kHZ
95
90
9 ¦SW = 600 kHZ
80
90
70
Efficiency (%)
Efficiency (%)
VOUT
85
80
75
65
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (A)
50
40
30
Vin
VIN==6V
6V
Vin
VIN==12V
12 V
VIN==24V
24 V
Vin
VIN==36V
36 V
Vin
70
60
Vin == 66V
V
V
IN
Vin
= 12
12V
V
V
IN =
V
V
Vin
= 24
24V
IN =
V
V
IN =
Vin
= 36
36V
20
10
0
0.001
3.5
0.01
0.1
1
Output Current (A)
C001
Figure 61. Efficiency Versus Load Current
C002
Figure 62. Light Load Efficiency
100
100
VOUT
95
9 ¦SW = 600 kHZ
90
VOUT
9 ¦SW = 600 kHZ
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
65
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (A)
50
40
30
Vin
VIN==7V
7V
Vin
VIN==12V
12 V
VIN==24V
24 V
Vin
VIN==36V
36 V
Vin
70
60
Vin == 77V
V
V
IN
Vin
= 12
12V
V
V
IN =
V
V
Vin
= 24
24V
IN =
V
V
IN =
Vin
= 36
36V
20
10
3.5
0
0.001
C003
Figure 63. Efficiency Versus Load Current
0.01
0.1
Output Current (A)
Figure 64. Light Load Efficiency
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60
180
0.10
VIN = 12 V
VOUT = 3.3 V
fsw = 600 kHz
120
20
60
0
0
±20
±60
VIN = 12 V
VOUT = 3.3 V
IOUT = 3.5 A
fsw = 600 kHz
±40
Gain (dB)
Phase (Deg)
±60
10
100
1k
Output Volttage Deviation (%)
40
Phase (Deg)
Gain (dB)
0.08
±120
0.04
0.02
0.00
±0.02
±0.04
±0.06
±0.08
±0.10
±180
100k
10k
0.06
Frequency (Hz)
0
1
2
3
Output Current (A)
C005
4
C006
Figure 66. Regulation Versus Load Current
Figure 65. Overall Loop Frequency Response
0.10
IOUT = 1.75 V
VOUT = 3.3 V
fsw = 600 kHz
Output Voltage Deviation (%)
0.08
0.06
0.04
0.02
0.00
±0.02
±0.04
±0.06
±0.08
±0.10
0
5
10
15
20
25
30
35
40
Input Voltage (V)
45
C007
Figure 67. Regulation Versus Input Voltage
40
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9 Power Supply Recommendations
The device are designed to operate from an input voltage supply range between 4.5 V and 42 V. If the input
supply is located more than a few inches from the TPS54340 converter additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical
choice.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by
the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 68 for a PCB layout
example. The GND pin should be tied directly to the power pad under the IC and the power pad.
The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC. The
SW pin should be routed to the cathode of the catch diode and to the output inductor. Because the SW
connection is the switching node, the catch diode and output inductor should be located close to the SW pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated
load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise
so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The
additional external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
10.2 Layout Example
VOUT
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
VIN
UVLO
Adjust
Resistors
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
BOOT
Catch
Diode
PWRGD
VIN
SW
EN
GND
SS/TR
RT/CLK
COMP
FB
Compensation
Network
Resistor
Divider
Thermal VIA
Soft-Start
Capacitor
Frequency
Set Resistor
Signal VIA
Figure 68. PCB Layout Example
42
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Creating GSM/GRPS Power Supply from TPS54260, SLVA412
• Creating a Universal Car Charger for USB devices From the TPS54240 and TPS2511, SLVA464
• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54341DPRR
ACTIVE
WSON
DPR
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54341
TPS54341DPRT
ACTIVE
WSON
DPR
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54341
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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