TPS543620
SLUSDR5C – MAY 2020 – REVISED JUNE 2021
TPS543620 4-V to 18-V Input, 6-A Synchronous SWIFT™ Step-Down Converter with
Internally Compensated Advanced Current Mode Control
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fixed-frequency, internally-compensated advanced
current mode (ACM) control
Integrated 25-mΩ and 6.5-mΩ MOSFETs
Input voltage range: 4 V to 18 V
Output voltage range: 0.5 V to 7 V
Three selectable PWM ramp options to optimize
the control loop performance
Five selectable switching frequencies: 500 kHz,
750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz
Synchronizable to an external clock
0.5-V, ±0.5% voltage reference accuracy over full
temperature range
Selectable soft start times: 0.5 ms, 1 ms, 2 ms,
and 4 ms
Monotonic start-up into pre-biased outputs
Selectable current limits to support 6-A and 3-A
operation
Enable with adjustable input undervoltage lockout
Power good output monitor
Output overvoltage, output undervoltage, input
undervoltage, overcurrent, and overtemperature
protection
Pin-to-pin compatible with TPS543820 and
TPS543320
–40°C to 150°C operating junction temperature
2.5-mm × 3-mm, 14-pin VQFN-HR package with
0.5-mm pitch
Wireless infrastructure and wired communications
equipment
Optical and fiber networks
Test and measurement
Medical and healthcare
•
•
•
3 Description
The TPS543620 is a high-efficiency 18-V, 6-A
synchronous buck converter employing an internallycompensated, fixed-frequency Advanced Current
Mode control. It is capable of providing high efficiency
while running at a switching frequency up to 2.2
MHz. The device is in a small 2.5-mm x 3-mm
HotRod™ VQFN package, which coupled with high
efficiency at high frequency, makes it optimal for
designs requiring a small solution size. The fixed
frequency controller can operate from 500 kHz to
2.2 MHz and can be synchronized to an external
clock using the SYNC pin. Additional features include
a high accuracy voltage reference, selectable soft
start times, montonic start-up into pre-biased outputs,
selectable current limits, adjustable UVLO through the
EN pin, and a full suite of fault protections.
Device Information
PACKAGE(1)
PART NUMBER
TPS543620
(1)
VQFN-HR (14)
BODY SIZE (NOM)
2.50 mm x 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN
BOOT
96
BP5
SW
92
SW
EN
TPS543620
PGOOD
SYNC/FSEL
MODE
FB
AGND
VOUT
Efficiency (%)
VIN
88
84
80
76
72
PGND
68
12 V to 0.8 V, 1 MHz
12 V to 1 V, 1 MHz
12 V to 1.8 V, 1 MHz
64
Simplified Schematic
60
0
0.6
1.2
1.8
2.4
3
3.6 4.2
Output Current (A)
4.8
5.4
Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
6
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SLUSDR5C – MAY 2020 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 18
8.1 Application Information............................................. 18
8.2 Typical Applications.................................................. 18
9 Power Supply Recommendations................................37
10 Layout...........................................................................38
10.1 Layout Guidelines................................................... 38
10.2 Layout Example...................................................... 38
11 Device and Documentation Support..........................41
11.1 Receiving Notification of Documentation Updates.. 41
11.2 Support Resources................................................. 41
11.3 Trademarks............................................................. 41
11.4 Electrostatic Discharge Caution.............................. 41
11.5 Glossary.................................................................. 41
12 Mechanical, Packaging, and Orderable
Information.................................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2021) to Revision C (June 2021)
Page
• Changed 10-ns transient to 20-ns transient........................................................................................................4
• Changed VIN to SW, transient 20 ns min value to -6......................................................................................... 4
• Changed SW, transient 20 ns min value to -5.................................................................................................... 4
• Changed max VOUT to 7 V.................................................................................................................................. 4
• Added TOFF(min) max value................................................................................................................................. 5
• Added text for considering minimum off-time for fsw selection.........................................................................19
Changes from Revision A (November 2020) to Revision B (February 2021)
Page
• Added links to TPS543820 and TPS543320 pin-to-pin devices......................................................................... 1
• Added Power Loss vs Output Current – 1.8-V to 5.0-V Output ......................................................................... 7
• Updated Figure 10-1 ........................................................................................................................................38
Changes from Revision * (May 2020) to Revision A (November 2020)
Page
• Changed device status from Advance Information to Production Data.............................................................. 1
2
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FB
PGOOD
MODE
5 Pin Configuration and Functions
4
3
2
AGND
5
1
SYNC/
FSEL
BP5
6
14
BOOT
EN
7
13
SW
VIN
8
12
VIN
PGND
9
11
PGND
10
SW
Figure 5-1. 14-Pin VQFN-HR RPY Package (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SYNC/FSEL
1
I
Frequency select and external clock synchronization. A resistor to ground sets the switching
frequency of the device. An external clock can also be applied to this pin to synchronize the
switching frequency.
MODE
2
I
A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude.
PGOOD
3
O
Open-drain power good indicator
FB
4
I
Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor
divider to set the output voltage.
AGND
5
-
Ground return for internal analog circuits
BP5
6
O
Internal 4.5-V regulator output. Bypass this pin with a 2.2-μF capacitor to AGND.
EN
7
I
Enable pin. Float to enable, enable/disable with an external signal, or adjust the input
undervoltage lockout with a resistor divider.
VIN
8, 12
I
Input power to the power stage. Low impedance bypassing of these pins to PGND is critical.
A 10-nF to 100-nF capacitor from each VIN to PGND close to IC is required.
PGND
9, 11
-
Ground return for the power stage. This pin is internally connected to the source of the
low-side MOSFET.
SW
10
O
Switch node of the converter. Connect this pin to the output inductor.
SW
13
O
Return path for the internal high-side MOSFET gate driver bootstrap capacitor. Connect a
capacitor from BOOT to this pin. The SW pins are connected internally.
BOOT
14
I
Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to
SW.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Input voltage
VIN
-0.3
20
UNIT
V
Input voltage
VIN to SW, DC
-0.3
20
V
Input voltage
VIN to SW, transient 20 ns
-6
25
V
Input voltage
BOOT
-0.3
25
V
Input voltage
BOOT to SW
-0.3
6
V
Input voltage
EN, PGOOD, MODE, SYNC/FSEL, FB
-0.3
6
V
Output voltage
SW, DC
-0.3
20
V
Output voltage
SW, transient 20 ns
-5
22
V
Operating junction
Operating junction temperature, TJ
temperature, TJ
-40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±500
V
(1)
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage
VIN
Output voltage
VOUT
Output current
IOUT
TJ
Operating junction temperature
fSYNC
External clock frequency
NOM
MAX
UNIT
4
18
V
0.5
7
V
6
A
-40
150
°C
400
2600
kHz
6.4 Thermal Information
TPS543620
THERMAL
RPY (QFN, JEDEC)
RPY (QFN, TI EVM)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
58.9
29.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.8
Not applicable (2)
°C/W
RθJB
Junction-to-board thermal resistance
7.3
Not applicable (2)
°C/W
ψJT
Junction-to-top characterization parameter
0.9
1.8
°C/W
ψJB
Junction-to-board characterization parameter
7.2
13.4
°C/W
(1)
(2)
4
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Not applicable to an EVM layout.
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6.5 Electrical Characteristics
TJ = –40 °C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1200
1600
µA
15
25
µA
4
4.1
V
SUPPLY VOLTAGE
IQ(VIN)
VIN operating non-switching supply current
VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1
MHz
ISD(VIN)
VIN shutdown supply current
VEN = 0 V, VVIN = 12 V
VIN UVLO rising threshold
VIN rising
3.9
VIN UVLO hysteresis
150
mV
ENABLE AND UVLO
VEN(rise)
EN voltage rising threshold
EN rising, enable switching
VEN(fall)
EN voltage falling threshold
EN falling, disable switching
VEN(hyst)
EN voltage hysteresis
1.2
1.05
0.4
1.25
V
1.1
V
100
mV
EN pin sourcing current
VEN = 1.1 V
1.5
µA
EN pin sourcing current
VEN = 1.3 V
11.6
µA
Internal LDO BP5 output voltage
VVIN = 12 V
4.5
BP5 dropout voltage
VVIN – VBP5, VVIN = 3.8 V
BP5 short-circuit current limit
VVIN = 12 V
INTERNAL LDO BP5
VBP5
V
350
75
mV
mA
REFERENCE VOLTAGE
VFB
IFB(LKG)
Feedback Voltage
TJ = –40°C to 150°C
Input leakage current into FB pin
VFB = 500 mV, non-switching, VVIN = 12 V,
VEN = 0 V
497.5
500
502.5
1
mV
nA
SWITCHING FREQUENCY AND OSCILLATOR
fSW
Switching frequency
RMODE = 24.3 kΩ
450
500
550
kHz
fSW
Switching frequency
RMODE = 17.4 kΩ
675
750
825
kHz
fSW
Switching frequency
RMODE = 11.8 kΩ
900
1000
1100
kHz
fSW
Switching frequency
RMODE = 8.06 kΩ
1350
1500
1650
kHz
fSW
Switching frequency
RMODE = 4.99 kΩ
1980
2200
2420
kHz
SYNCHRONIZATION
VIH(sync)
High-level input voltage
VIL(sync)
Low-level input voltage
1.8
V
0.8
V
SOFT-START
tSS1
Soft-start time
RMODE = 1.78 kΩ
0.5
ms
tSS2
Soft-start time
RMODE = 2.21 kΩ
1
ms
tSS3
Soft-start time
RMODE = 2.74 kΩ
2
ms
tSS4
Soft-start time
RMODE = 3.32 kΩ
4
ms
RDS(on)HS
High-side MOSFET on-resistance
TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V
25
mΩ
RDS(on)LS1
Low-side MOSFET on-resistance: high
current limit selected
TJ = 25°C, VBP5 = 4.5 V, RMODE = 1.78 kΩ
6.5
mΩ
RDS(on)LS2
Low-side MOSFET on-resistance: low
current limit selected
TJ = 25°C, VBP5 = 4.5 V, RMODE = 22.1 kΩ
13.9
mΩ
VBOOT-SW(UV_r)
BOOT-SW UVLO rising threshold
VBOOT-SW rising
3.2
V
VBOOT-SW(UV_f)
BOOT-SW UVLO falling threshold
VBOOT-SW falling
2.8
TON(min)
Minimum ON pulse width
IOUT > ½ IL_PK-PK
30
37
ns
TOFF(min)
Minimum OFF pulse width (1)
115
140
ns
POWER STAGE
V
CURRENT SENSE AND OVERCURRENT PROTECTION
IOC_HS_pk1
High-side peak current limit
RMODE = 1.78 kΩ
8.6
9
9.6
A
IOC_HS_pk2
High-side peak current limit
RMODE = 22.1 kΩ
4.2
4.5
4.8
A
IOC_LS_src1
Low-side sourcing current limit
RMODE = 1.78 kΩ
6.4
7.3
8.1
A
IOC_LS_src2
Low-side sourcing current limit
RMODE = 22.1 kΩ
3.65
4.2
4.65
A
IOC_LS_snk
Low-side sinking current limit
Current into SW pin
2.95
A
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TJ = –40 °C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
VOVP
Overvoltage-protection (OVP) threshold
voltage
VFB rising
120
% VREF
VUVP
Undervoltage-protection (UVP) threshold
voltage
VFB falling
80
% VREF
PGOOD threshold
VFB rising (Fault)
113
116
119
% VREF
PGOOD threshold
VFB falling (Good)
105
108
111
% VREF
PGOOD threshold
VFB rising (Good)
89
92
95
% VREF
PGOOD threshold
VFB falling (Fault)
81
84
87
% VREF
IPGOOD(LKG)
Leakage current into PGOOD pin when
open drain output is high
VPGOOD = 4.7 V
5
µA
VPG(low)
PGOOD low-level output voltage
IPGOOD = 2 mA, VIN = 12 V
0.5
V
1
V
POWER GOOD
Min VIN for valid PGOOD output
0.9
HICCUP
Hiccup time before re-start
7*tSS
ms
VVIN = 12 V, VSW = 0.5 V, power conversion
disabled.
100
Ω
Temperature rising
165
OUTPUT DISCHARGE
RDischg
Output discharge resistance
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (1)
THYST
Thermal shutdown hysteresis (1)
(1)
6
12
175
°C
°C
Specified by design. Not production tested.
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6.6 Typical Characteristics
TA = 25°C
100
1.2
96
1.1
92
1
0.9
Power Loss (W)
Efficiency (%)
88
84
80
76
72
64
0.8
0.7
0.6
0.5
0.4
12 V to 1 V, 750 kHz
12 V to 1 V, 1 MHz
12 V to 1 V, 1.5 MHz
12 V to 1 V, 2.2 MHz
68
0.3
0.2
60
0.1
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
L = 600 nH, 4.4 mΩ typical
0
0.5
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
Figure 6-2. Power Loss vs Output Current
100
1
96
12 V to 0.8 V, 1 MHz
12 V to 1 V, 1 MHz
12 V to 1.8 V, 1 MHz
0.9
92
0.8
Power Loss (W)
88
84
80
76
72
68
0.6
1.2
1.8
2.4
3
3.6 4.2
Output Current (A)
4.8
5.4
0.6
0.5
0.4
0.2
0.1
60
0
0.7
0.3
12 V to 0.8 V, 1 MHz
12 V to 1 V, 1 MHz
12 V to 1.8 V, 1 MHz
64
0
6
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
L = 600 nH, 4.4 mΩ typical
L = 600 nH, 4.4 mΩ typical
Figure 6-4. Power Loss vs Output Current
Figure 6-3. Efficiency vs Output Current
1.6
100
VOUT = 1.8 V, L = XEL5030-122
VOUT = 2.5 V, L = XEL5030-122
VOUT = 2.5 V, L = XEL5050-182
VOUT = 3.3 V, L = XEL5050-182
VOUT = 5 V, L = XEL5050-182
1.4
95
1.2
90
Power Loss (W)
Efficiency (%)
1
L = 600 nH, 4.4 mΩ typical
Figure 6-1. Efficiency vs Output Current
Efficiency (%)
12 V to 1 V, 750 kHz
12 V to 1 V, 1 MHz
12 V to 1 V, 1.5 MHz
12 V to 1 V, 2.2 MHz
85
80
VOUT = 1.8 V, L = XEL5030-122
VOUT = 2.5 V, L = XEL5030-122
VOUT = 2.5 V, L = XEL5050-182
VOUT = 3.3 V, L = XEL5050-182
VOUT = 5 V, L = XEL5050-182
75
1
0.8
0.6
0.4
0.2
70
0
0
0.5
1
VIN = 12 V
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
fSW = 1.0 MHz
Figure 6-5. Efficiency vs Output Current – 1.8-V to
5.0-V Output
0
0.5
1
VIN = 12 V
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
fSW = 1.0 MHz
Figure 6-6. Power Loss vs Output Current – 1.8-V
to 5.0-V Output
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0.505
3
VIN = 4 V
VIN = 12 V
VIN = 18 V
0.504
EN Pin Output Current (PA)
Voltage Reference (V)
0.503
0.502
0.501
0.5
0.499
0.498
0.497
2.5
2
1.5
1
0.5
0.496
0.495
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
0
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
VEN = 1.1 V
Figure 6-7. Regulated FB Voltage vs Junction
Temperature
Figure 6-8. EN Pin Current vs Junction
Temperature
EN Pin Output Current (PA)
12.5
12
11.5
11
10.5
VIN = 4 V
VIN = 12 V
VIN = 18 V
10
9.5
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
VEN = 1.3 V
Figure 6-9. EN Pin Current vs Junction Temperature
8
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7 Detailed Description
7.1 Overview
The TPS543620 device is a 6-A, high-performance, synchronous buck converter with two integrated N-channel
MOSFETs. The TPS543620 has a maximum operating junction temperature of 150°C, making it suitable for
high-ambient temperature applications such as wireless infrastructure. The input voltage range is 4 V to 18 V
and the output voltage range is 0.5 V to 7 V. The device features a fixed-frequency Advanced Current Mode
control with a switching frequency of 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when
selecting output filter components. The switching frequency of the device can be synchronized to an external
clock applied to the SYNC pin.
Advanced Current Mode (ACM) is an emulated peak current control topology. It supports stable static and
transient operation without complex external compensation design. This control architecture includes an internal
ramp generation network that emulates inductor current information, enabling the use of low-ESR output
capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-tonoise ratio for good noise immunity. The TPS543620 has three ramp options (see Section 7.3.6 for details)
to optimize the internal loop for various inductor and output capacitor combinations with only a single resistor
to AGND. The TPS543620 is easy-to-use and allows low external component count with fast load transient
response. Fixed-frequency operation also provides ease-of-filter design to overcome EMI noise.
7.2 Functional Block Diagram
BP5
BP5_UVLO
SYNC/
FSEL
Oscillator
Pinstrap
Detect
UVLO
UVLO
ILIM
EN_UVLO
UVLO
EN_UVLO
Boot
Charge
Cramp
Soft-Start
Control
VIN_UVLO
Linear Regulator
CLK
MODE
EN
VIN
BOOT
VREF
ACM
Controller
Control
Logic
SW
BP5
FB
OV/UV
Comparators
PGND
Thermal
Shutdown
BOOT
SW
Fault Logic
UVLO
HS and LS
Current Sense
OC_FLT
OC_FLT
VIN_UVLO
AGND
ILIM
BP5_UVLO
PGOOD
7.3 Feature Description
7.3.1 VIN Pins and VIN UVLO
The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the
power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO
circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO
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threshold. The internal VIN UVLO threshold has a hysteresis of 150 mV. A voltage divider connected to the EN
pin can adjust the input voltage UVLO as appropriate. See Section 7.3.2 for more details.
7.3.2 Enable and Adjustable UVLO
The EN pin provides on/off control of the device. Once the EN pin voltage exceeds its threshold voltage, the
device begins its start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters a low operating current state. The EN pin has an internal pullup current source, Ip,
allowing it to be floated to enable the device by default. It is important to ensure that leakage currents of anything
connected to the EN pin do not exceed the minimum EN pullup current or the device may not be able to start. If
an application requires controlling the EN pin, an open drain or open collector output logic can be interfaced with
the pin.
When the EN pin voltage exceeds its threshold voltage and the VIN pin voltage exceeds its VIN UVLO threshold,
the device begins its start-up sequence. First, the BP5 LDO is enabled and charges the external BP5 capacitor.
Once the voltage on the BP5 pin exceeds its UVLO threshold, the device enters a power-on delay. During the
power-on delay, the values of the pinstrap resistors on the MODE pin (see Section 7.3.8) and SYNC/FSEL pin
(see Section 7.3.4) are determined and the control loop is initialized. The power-on delay is typically 600 μs.
After the power-on delay, soft start begins.
4.0V
VIN
EN
1.2V
3.6V
BP5 LDO
BP5 LDO
Startup
Power-on
delay
SW pulses are omitted to
simplify the illustration
««
SW
VOUT
Figure 7-1. Start-up Sequence
An external resistor divider can be added from VIN to the EN pin for adjustable UVLO and hysteresis as shown
in Figure 7-2. The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when
no external components are connected. The pullup current is also used to control the voltage hysteresis for the
UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can
be calculated using Equation 1 and Equation 2. When using the adjustable UVLO function, 500 mV or greater
hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed
from the EN pin to ground to filter any glitches on the input voltage.
10
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VIN
Ip
Ih
RENT
EN
+
±
RENB
Figure 7-2. Adjustable UVLO Using EN
RENT
RENB
§V
·
VSTART u ¨ ENFALLING ¸ VSTOP
© VENRISING ¹
§
·
V
Ip u ¨ 1 ENFALLING ¸ Ih
V
ENRISING ¹
©
(1)
RENT u VENFALLING
VSTOP
VENFALLING
RENT u Ip
Ih
(2)
7.3.3 Adjusting the Output Voltage
The output voltage is programmed with a resistor divider from the output (VOUT) to the FB pin shown in Figure
7-3. It is recommended to use 1% tolerance or better divider resistors. Starting with a fixed value for the bottom
resistor, typically 10 kΩ, use Equation 3 to calculate the top resistor in the divider.
VOUT
RFBT
FB
±
RFBB
0.5 V
+
Figure 7-3. FB Resistor Divider
RFBT
§V
RFBB u ¨ OUT
© VREF
·
1¸
¹
(3)
7.3.4 Switching Frequency Selection
The switching frequency of the device can be selected by connecting a resistor (RFSEL) between the SYNC/
FSEL pin and AGND. The frequency options and their corresponding programming resistors are listed in Table
7-1. It is required to use a 1% tolerance resistor or better.
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Table 7-1. Switching Frequency Selection
RFSEL ALLOWED NOMINAL
RANGE (1%) (kΩ)
RECOMMENDED E96
STANDARD VALUE (1%) (kΩ)
RECOMMENDED E12
STANDARD VALUE (1%) (kΩ)
Fsw (kHz)
≥24.0
24.3
27
500
17.4-18.0
17.4
18
750
11.8-12.1
11.8
12
1000
8.06-8.25
8.06
8.2
1500
≤5.11
4.99
4.7
2200
7.3.5 Switching Frequency Synchronization to an External Clock
The device can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL
pin with a duty cycle from 20% to 80%. The clock can either be applied before the device starts up or during
operation. If the clock is to be applied before the device starts, a resistor between SYNC/FSEL and AGND is
not needed. If the clock is to be applied after the device starts, then the clock frequency should be within ±20%
of the frequency set by the SYNC/FSEL resistor. When the clock is applied after the device starts, the device
will begin synchronizing to this clock after counting four consectutive switching cycles with a clock pulse present.
This is shown in Figure 7-4.
7.3.5.1 Internal PWM Oscillator Frequency
When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the
external clock is not present, the device will default to the internal PWM oscillator frequency.
If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is
set by the RFSEL resistor according to Table 7-1. The device switches at this frequency until the external clock is
applied or anytime the external clock is not present.
If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device will
determine the internal clock frequency by decoding the external clock frequency. Table 7-2 shows the decoding
of the internal PWM oscillator frequency based on the external clock frequency.
Table 7-2. Internal Oscillator Frequency Decode
EXTERNAL SYNC CLOCK FREQUENCY (kHz)
DECODED INTERNAL PWM OSCILLATOR FREQUENCY (kHz)
400 - 600
500
600 - 857
750
857 - 1200
1000
1200 - 1810
1500
1810 - 2640
2200
The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the
external clock frequency is to be within that tolerance range, it is possible for the internal PWM oscillator
frequency to be decoded as either the frequency above or below that threshold. Since the internal frequency is
what is used in case of the loss of the synchronization clock, it is recommended that the output LC filter and
ramp selection are chosen to be stable for either frequency. Table 7-3 shows the tolerance range of the decode
thresholds. If the external clock is to be within any of these ranges, it is recommended to ensure converter
stability for both possible internal PWM oscillator frequencies.
Table 7-3. Frequency Decode Thresholds
12
MINIMUM (kHz)
TYPICAL (kHz)
MAXIMUM (kHz)
570
600
630
814
857
900
1140
1200
1260
1736
1810
1884
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7.3.5.2 Loss of Synchronization
If at any time during operation, there is a loss of synchronization, the device will default to the internal PWM
oscillator frequency until the synchronization clock returns. Once the clock is no longer present, the device will
switch at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without
clock pulses, the device will operate at the normal internal PWM oscillator frequency. This is demonstrated in
Figure 7-4.
SW (5 V/div)
VOUT AC (10 mV/div)
SYNC (5 V/div)
Time (4 µs/div)
Figure 7-4. Clock Synchronization Transitions
7.3.5.3 Interfacing the SYNC/FSEL Pin
If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is
enabled, a high impedance buffer is recommended to ensure proper detection of the RFSEL value. Figure 7-5
shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to
ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its
VCC voltage is available and the buffers output is high impedance before the device tries to detect the RFSEL
value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA.
BP5
OE
VCC
SYNC/FSEL
RFSEL
Figure 7-5. Interfacing the SYNC/FSEL Pin with a Buffer
7.3.6 Ramp Amplitude Selection
The TPS543620 uses VIN, duty cycle, and low-side FET current information to generate an internal ramp. The
ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP
can be selected with a resistor to AGND on the MODE pin (see Section 7.3.8). The capacitor options are 1 pF, 2
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pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop
bandwidth. Figure 7-6 and Figure 7-7 show how the loop changes with each ramp setting for the schematic in
Section 8.2.3.
60
180
150
120
40
20
Phase (°)
Gain (dB)
90
0
60
30
0
-30
-20
-60
Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF
-40
100 200
500 1000
Ramp = 4 pF
Ramp = 2 pF
Ramp = 1 pF
-90
10000
Frequency (Hz)
100000
1000000
Figure 7-6. Loop Gain vs Ramp Settings
-120
100 200
500 1000
10000
Frequency (Hz)
100000
1000000
Figure 7-7. Loop Phase vs Ramp Settings
7.3.7 Soft Start and Prebiased Output Start-up
During start-up, the device softly ramps the reference voltage to reduce inrush currents. There are four options
for the soft-start time, which is the time it takes for the reference to ramp to 0.5 V: 0.5 ms, 1 ms, 2 ms, and 4 ms.
The soft-start time is selected with a resistor to AGND on the MODE pin (see Section 7.3.8).
The device prevents current from being discharged from the output during start-up when a prebiased output
condition exists. It does this by operating in discontinuous conduction mode (DCM) during the first 16 cycles to
prevent the device from sinking current. This ensures the output voltage will be smooth and monotonic during
soft start.
7.3.8 Mode Pin
The ramp amplitude, soft-start time, and current limit settings are programmed with a single resistor, RMODE,
between MODE and AGND. Table 7-4 lists the resistor values for the available options. It is required to use a 1%
tolerance resistor or better. See Section 7.3.10 for the corresponding current limit thresholds for the "High" and
"Low" settings.
Table 7-4. MODE Pin Selection
14
RMODE (kΩ)
CURRENT LIMITS
CRAMP (pF)
SOFT-START TIME (ms)
1.78
High
1
0.5
2.21
High
1
1
2.74
High
1
2
3.32
High
1
4
4.02
High
2
0.5
4.87
High
2
1
5.9
High
2
2
7.32
High
2
4
9.09
High
4
0.5
11.3
High
4
1
14.3
High
4
2
18.2
High
4
4
22.1
Low
1
0.5
26.7
Low
1
1
33.2
Low
1
2
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Table 7-4. MODE Pin Selection (continued)
RMODE (kΩ)
CURRENT LIMITS
CRAMP (pF)
SOFT-START TIME (ms)
40.2
Low
1
4
49.9
Low
2
0.5
60.4
Low
2
1
76.8
Low
2
2
102
Low
2
4
137
Low
4
0.5
174
Low
4
1
243
Low
4
2
412
Low
4
4
7.3.9 Power Good (PGOOD)
The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the
FB pin is between 92% and 108% of the internal voltage reference, soft start is complete, and after a 256-µs
deglitch time, the PGOOD pin is de-asserted and the pin floats. A pullup resistor between the values of 10 kΩ
and 100 kΩ to a voltage source that is 5.5 V or less is recommended. PGOOD is in a defined state once the VIN
input voltage is greater than 1 V but with reduced current sinking capability. When the FB is lower than 84% or
greater than 116% of the nominal internal reference voltage, after a 8-µs deglitch time, the PGOOD pin is pulled
low. PGOOD is immediately pulled low if VIN falls below its UVLO, the EN pin is pulled low or the device enters
thermal shutdown.
7.3.10 Current Protection
The protects against overcurrent events by cycle-by-cycle current limiting both the high-side MOSFET and
low-side MOSFET. In an extended overcurrent condition, the device will enter hiccup. Different protections are
active during positive inductor current and negative inductor current conditions.
7.3.10.1 Positive Inductor Current Protection
The current is sensed in the high-side MOSFET while it is conducting after a short blanking time to allow noise to
settle. Whenever the high-side overcurrent threshold is exceeded, the high-side MOSFET is immediately turned
off and the low-side MOSFET is turned on. The high-side MOSFET does not turn back on until the current falls
below the low-side MOSFET overcurrent threshold. This effectively limits the peak current in the case of a short
circuit condition. If a high-side overcurrent is detected for 15 consecutive cycles, the device enters hiccup.
The current is also sensed in the low-side MOSFET while it is conducting after a short blanking time to allow
noise to settle. If the low-side overcurrent threshold is exceeded when the next incoming PWM signal is received
from the controller, the device skips processing that PWM pulse. The device does not turn the high-side
MOSFET on again until the low-side overcurrent threshold is no longer exceeded. If the low-side overcurrent
threshold remains exceeded for 15 consecutive cycles, the device enters hiccup. There are two separate
counters for the high-side and low-side overcurrent events. If the off-time is too short, the low-side overcurrent
may not trip. The low-side overcurrent will, however, begin tripping after the high-side peak overcurrent limit is hit
as hitting the peak current limit shortens the on-time and lengthens the off-time.
Both the high-side and low-side positive overcurrent thresholds are programmable using the MODE pin. Two
sets of thresholds are available ("High" and "Low"), which are summarized in Table 7-5. The values for these
thresholds are obtained using open-loop measurements with a DC current in order to accurately specify the
values. In real applications, the inductor current will ramp and the ramp rate will be a function of the voltage
across the inductor (VIN - VOUT) as well as the inductance value. This ramp rate combined with delays in
the current sense circuitry can result in slightly different values than specified. The current at which the highside overcurrent limit takes effect can be slightly higher than specified, and the current at which the low-side
overcurrent limit takes effect can be slightly lower than specified.
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Table 7-5. Overcurrent Thresholds
MODE PIN CURRENT LIMIT SETTING
HIGH-SIDE OVERCURRENT TYPICAL
VALUE (A)
LOW-SIDE OVERCURRENT TYPICAL VALUE
(A)
High
9.0
7.3
Low
4.5
4.2
7.3.10.2 Negative Inductor Current Protection
Negative current is sensed in the low-side MOSFET while it is conducting after a short blanking time to allow
noise to settle. Whenever the low-side negative overcurrent threshold is exceeded, the low-side MOSFET is
immediately turned off. The next high-side MOSFET turnon is determined by the clock and PWM comparator.
The negative overcurrent threshold minimum value is 2.95 A. Similar to the positive inductor current protections,
the actual value of the inductor current when the current sense comparators trip will be a function of the current
ramp rate. As a result the current at which the negative inductor current limit takes effect can be slightly more
negative than specified.
7.3.11 Output Overvoltage and Undervoltage Protection
The device incorporates both output overvoltage and undervoltage protection. If an overvoltage is detected, the
device tries to discharge the output voltage to a safe level before attempting to restart. When the overvoltage
threshold is exceeded, the low-side MOSFET is turned on until the low-side negative overcurrent threshold is
reached. At this point, the high-side MOSFET is turned on until the inductor current reaches zero. Then, the
low-side MOSFET is turned back on until the low-side negative overcurrent threshold is reached. This process
repeats until the output voltage falls back into the PGOOD window. Once this happens, the device restarts and
goes through a soft start cycle. The device does not wait the hiccup time before restarting.
When an undervoltage condition is detected, the device will enter hiccup where it waits seven soft-start cycles
before restarting. Undervoltage protection is enabled after soft start is complete.
7.3.12 Overtemperature Protection
When the die temperature exceeds 165°C, the device turns off. Once the die temperatures falls below the
hysteresis level, typically 12°C, the device restarts. While waiting for the temperature to fall below the hysteresis
level, the device does not switch or attempt to hiccup to restart. Once the temperature falls below this level, the
device restarts without going through hiccup.
7.3.13 Output Voltage Discharge
When the device is enabled, but the high-side FET and low-side FET are disabled due to a fault condition,
the output voltage discharge mode is enabled. This mode turns on the discharge FET from SW to PGND to
discharge the output voltage. The discharge FET is turned off when the converter is ready to resume switching,
either after the fault clears or after the wait time before hiccup is over.
The output voltage discharge mode is activated by any of below fault events:
1.
2.
3.
4.
High-side or low-side positive overcurrent
Thermal shutdown
Output voltage undervoltage
VIN UVLO
7.3.14 Low-Side MOSFET Resistance Scaling
When the "low" current limit is selected as described in Section 7.3.10.1, a smaller portion of the low-side
MOSFET is used while the rest of the FET remains off. This increases the light-load efficiency for the lower
current limits by removing a portion of the low-side MOSFET switching loss.
Table 7-6. Low-Side MOSFET Resistance
MODE PIN CURRENT LIMIT SETTING
16
LOW-SIDE MOSFET RDS(on) (mΩ)
High
6.5
Low
13.9
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7.4 Device Functional Modes
7.4.1 Forced Continuous-Conduction Mode
The TPS543620 operates in forced continuous-conduction mode (FCCM) throughout normal operation.
7.4.2 Discontinuous Conduction Mode during Soft Start
During soft start, the converter operates in discontinuous conduction mode (DCM) during the first 16 PWM
cycles. During this time, a zero-cross detect comparator is used to turn off the low-side MOSFET when the
current reaches zero amps. This prevents the discharge of any pre-biased conditions on the output. After 16
cycles of DCM, the converter enters FCCM mode.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS543620 is a synchronous buck regulator designed for 4-V to 18-V input and 6-A load. This procedure
illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
8.2 Typical Applications
8.2.1 1.0-V Output, 1-MHz Application
VIN
VIN
CI1
0805
25V
10uF
CBULK
35V
100uF
PGND
CI2
0805
25V
10uF
CHF1
0402
50V
0.1uF
CHF2
0402
50V
0.1uF
U2
8
12
VIN
VIN
SW
SW
10
13
EN
7
EN
BOOT
14
FSEL
1
VIN
RENT
16.9k
MODE
SYNC/FSEL
2
BP5
RPG
10k
RENB
6.04k
RFSEL
11.8k
FB
AGND
5
PGND
PGND
9
11
PGOOD
6
BP5
CBT
XEL5030-601MEC
600nH
CO1
0805
10V
22uF
FB 0402
50V
0.1uF
4
MODE
PGOOD 3
VOUT
LO
SW
CO3
1210
6.3V
47µF
CO4
1210
6.3V
47µF
Net-Tie
VO_SNS
VO_SNS
PGND
Net-Tie
RBODE
10.0
CFF
180pF
TPS543620RPY
RMODE
4.87k
CO2
0805
10V
22uF
BODE
CBP5
0603
2.2µF
10V
PGND
AGND
RFBT
FB
4.99k
Note: RBODE for measurement purposes only
RFBB
4.99k
AGND
AGND
Figure 8-1. 12-V Input, 1.0-V Output, 1-MHz Schematic
8.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 8-1.
Table 8-1. Design Parameters
18
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
4.5 to 13.2 V, 12 V nominal
Output voltage (VOUT)
1.0 V
Output current rating (IOUT)
6A
Switching frequency (fSW)
1000 kHz
Steady state output ripple voltage
10 mV
Output current load step
3A
Transient response
± 30 mV (± 3%)
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switching Frequency
The first step is to decide on a switching frequency. The TPS543620 can operate at five different frequencies
from 500 kHz to 2.2 MHz. The fSW is set by the resistor value from the FSEL pin to ground. Typically the
highest switching frequency possible is desired because it produces the smallest solution size. A high switching
frequency allows for smaller inductors and output capacitors compared to a power supply that switches at a
lower frequency. The main tradeoff made with selecting a higher switching frequency is extra switching power
loss, which hurts the efficiency of the regulator.
The maximum switching frequency for a given application can be limited by the minimum on-time of the
regulator. The maximum fSW can be estimated with Equation 4. Using the maximum minimum on-time of 40
ns and 13.2-V maximum input voltage for this application, the maximum switching frequency is 1890 kHz. The
selected switching frequency must also consider the tolerance of the switching frequency. A switching frequency
of 1000 kHz was selected for a good balance of solution size and efficiency. To set the frequency to 1000 kHz,
the selected FSEL resistor is 11.8 kΩ per Table 7-1.
fSW max
VOUT
1
u
tonmin VIN max
(4)
Figure 8-2 shows the maximum recommended input voltage versus output voltage for each FSEL frequency.
This graph uses a minimum on-time of 45 ns and includes the 10% tolerance of the switching frequency. A
minimum on-time of 45 ns is used in this graph to provide margin to the minimum controllable on-time to ensure
pulses are not skipped at no load. At light loads, the dead-time between the low-side MOSFET turning off and
high-side MOSFET turning on contributes to the minimum SW node pulse-width.
Figure 8-2. Maximum Input Voltage vs Output Voltage
In high output voltage applications, the minimum off-time must also be considered when selecting the switching
frequency. When hitting the minimum off-time limits, the operating duty cycle will max out and the output voltage
will begin to drop with the input voltage. Equation 5 calculates the maximum switching frequency to avoid this
limit. This equation requires the DC resistance of the inductor, RDCR, selected in the following step. A preliminary
estimate of 10 mΩ can be used but this should be recalculated based on the specifications of the inductor
selected. If operating near the maximum f SW limited by the minimum off-time, the increase in resistance at higher
temperature must be considered.
fSW :max; =
VIN :min; F VOUT F IOUT :max; × kR DCR + R DS :ON ;_HS o
t OFF _MIN :max; × @VIN :min; F IOUT :max; × kR DS :ON ;_HS F R DS :ON ;_LS oA
(5)
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8.2.1.2.2 Output Inductor Selection
To calculate the value of the output inductor, use Equation 6. KIND is a ratio that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the
output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor
since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.
Choosing small inductor ripple currents can degrade the transient response performance. The inductor ripple,
KIND, is normally from 0.1 to 0.4 for the majority of applications giving a peak to peak ripple current range of 0.6
A to 2.4 A. The recommended minimum target Iripple is 0.3 A or larger.
For this design example, KIND = 0.3 is used and the inductor value is calculated to be 0.51 µH. An inductor with
an inductance of 0.6 µH is selected. It is important that the RMS (Root Mean Square) current and saturation
current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation
8 and Equation 9. For this design, the RMS inductor current is 6 A, and the peak inductor current is 6.8 A. The
chosen inductor is a XEL5030-601. It has a saturation current rating of 22 A, an RMS current rating of 21.4 A,
and a typical DC series resistance of 4.44 mΩ.
The peak current through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated in Equation 9. In transient conditions, the inductor current can increase up to the switch current
limit of the device. For this reason, the most conservative approach is to specify the current ratings of the
inductor based on the switch current limit rather than the steady-state peak inductor current.
L1 =
Vinmax - Vout
Vout
´
Io ´ Kind
Vinmax ´ ¦ sw
(6)
vertical spacer
Iripple =
Vinmax - Vout
Vout
´
L1
Vinmax ´ ¦ sw
(7)
vertical spacer
ILrms =
Io 2 +
æ Vo ´ (Vinmax - Vo) ö
1
´ ç
÷
12
è Vinmax ´ L1 ´ ¦ sw ø
2
(8)
vertical spacer
ILpeak = Iout +
Iripple
2
(9)
Table 8-2 shows recommended E6 standard inductor values for other common output voltages with a 1-MHz
fSW. Using an inductance outside this recommended range typically works but the performance can be affected
and should be evaluated. The recommended value is calculated for a nominal input voltage of 12 V. The
minimum values are calculated with the maximum input voltage of 18 V. The maximum values are calculated
with with an input voltage of 5-V for all but the 5-V output. For the 5-V output, an 8-V input is used.
20
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Table 8-2. Recommended Inductor Values
OUTPUT
VOLTAGE (V)
SWITCHING
FREQUENCY (kHz)
MINIMUM
INDUCTANCE (µH)
RECOMMENDED
INDUCTANCE FOR 6 A
(µH)
RECOMMENDED
INDUCTANCE FOR 3 A
(µH)
MAXIMUM
INDUCTANCE (µH)
0.33
0.47
1
2.2
0.68
1
2.2
3.3
1
1.5
2.2
3.3
1.5
2.2
3.3
4.7
1
1.8
1000
3.3
5
8.2.1.2.3 Output Capacitor
There are two primary considerations for selecting the value of the output capacitor: the output voltage ripple
and how the regulator responds to a large change in load current. The output capacitance needs to be selected
based on the more stringent of these criteria.
The desired response to a large change in the load current is the first criteria and is typically the most stringent.
A regulator does not respond immediately to a large, fast increase or decrease in load current. The output
capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to
sense the change in the output voltage then adjust the peak switch current in response to the change in load.
The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically the loop
bandwidth is near fSW / 10. Equation 10 estimates the minimum output capacitance necessary, where ΔIOUT is
the change in output current and ΔVOUT is the allowable change in the output voltage.
For this example, the transient load response is specified as a 3% change in VOUT for a load step of 3 A.
Therefore, ΔIOUT is 3 A and ΔVOUT is 30 mV. Using this target gives a minimum capacitance of 159 μF. This
value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic
capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum
capacitors have higher ESR that must be considered for load step response.
COUT !
'IOUT
u
'VOUT
1
f
2S u SW
10
(10)
In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator
responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp
down after a load step down can be the limiting factor. Equation 11 estimates the minimum output capacitance
necessary to limit the change in the output voltage after a load step down. Using the 0.6-µH inductance selected
gives a minimum capacitance of 90 µF.
COUT !
LOUT u 'IOUT 2
2 u 'VOUT u VOUT
(11)
Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
In this case, the target maximum steady state output voltage ripple is 10 mV. Under this requirement, Equation
12 yields 19 µF.
Co >
1
´
8 ´ ¦ sw
1
Voripple
Iripple
(12)
where
•
•
•
ΔIOUT is the change in output current
ΔVOUT is the allowable change in the output voltage
fsw is the regulators switching frequency
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•
•
Voripple is the maximum allowable steady state output voltage ripple
Iripple is the inductor ripple current
Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum
amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on
the MODE pin. Equation 13 estimates the minimum capacitance needed for loop stability. This equation sets the
minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum
value. See Figure 8-3 for the limit versus output voltage with the lowest gain ramp setting of 1 pF. With a 1-V
output, the minimum ratio is 35 and with this ratio, Equation 13 gives a minimum capacitance of 52 µF.
2
COUT
§ Ratio ·
1
!¨
¸ u
© 2S u fSW ¹ LOUT
(13)
Equation 14 calculates the maximum combined ESR the output capacitors can have to meet the output voltage
ripple specification and this shows the ESR should be less than 6 mΩ. In this case, ceramic capacitors are used
and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple.
Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and
failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data
sheet specifies the RMS value of the maximum ripple current. Equation 15 can be used to calculate the RMS
ripple current the output capacitor needs to support. For this application, Equation 15 yields 445 mA and ceramic
capacitors typically have a ripple current rating much higher than this.
Resr <
Voripple
Iripple
(14)
vertical spacer
Icorm s =
Vout ´ (Vinm ax - Vout)
12 ´ Vinm ax ´ L1 ´ ¦ sw
(15)
Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors since they have a high
capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected
with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic
capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's
website. For this application example, two 22-µF, 10-V, X7S, 0805 and two 47-µF, 6.3-V, X7R, 1210 ceramic
capacitors each with 2 mΩ of ESR are used. The two 22-µF capacitors are used since they have a higher
resonance frequency and can help reduce the output ripple caused by parasitic inductance. With the four parallel
capacitors, the estimated effective output capacitance after derating using the capacitor manufacturer's website
is 142 µF. There is almost no DC bias derating at 1 V. This design was able to use less than the calculated
minimum because the loop crossover frequency was above the fSW / 10 estimate as shown in the Load Transient
graph in the Application Curves.
22
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8.2.1.2.4 Input Capacitor
Input decoupling ceramic capacitors type X5R, X7R, or similar from VIN to PGND that are placed as close as
possible to the IC are required. A total of at least 10 µF of capacitance is required and some applications can
require a bulk capacitance. At least 1 µF of bypass capacitance is recommended as close as possible to each
VIN pin to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed as close as possible to
both VIN pins 8 and 12 on the same side of the board of the device to provide high frequency bypass to reduce
the high frequency overshoot and undershoot on VIN and SW pins. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater
than the maximum RMS input current. The RMS input current can be calculated using Equation 16.
For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the
maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel have
been selected to be placed on both sides of the IC near both VIN pins to PGND pins. Based on the capacitor
manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input voltage of 12
V. A 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top power supply.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can
be calculated using Equation 17. The maximum input ripple occurs when operating nearest to 50% duty cycle.
Using the nominal design example values of Ioutmax = 6 A, C IN = 5.4 μF, and fSW = 1000 kHz, the input voltage
ripple with the 12 V nominal input is 85 mV and the RMS input ripple current with the 4.5 V minimum input is 4.9
A.
Icirms = Iout ´
Vout
´
Vinmin
(Vinmin
- Vout )
Vinmin
(16)
vertical spacer
'Vin
Vout · Vout
§
u
Iout maxu ¨ 1
Vin ¸¹ Vin
©
Cin u fSW
(17)
8.2.1.2.5 Adjustable Undervoltage Lockout
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB.
The UVLO has two thresholds: one for power up when the input voltage is rising and one for power down
or brownouts when the input voltage is falling. For the example design, the supply is set to turn on and start
switching once the input voltage increases above 4.5 V (UVLO start or enable). After the regulator starts
switching, it continues to do so until the input voltage falls below 3.95 V (UVLO stop or disable). In this example,
these start and stop voltages set by the EN resistor divider were selected to have more hysteresis than the
internally fixed VIN UVLO.
Equation 1 and Equation 2 can be used to calculate the values for the upper and lower resistor values. For
these equations to work, VSTART must be 1.1 × VSTOP due to the EN pin's voltage hysteresis. For the voltages
specified, the standard resistor value used for RENT is 16.9 kΩ and for RENB is 6.04 kΩ.
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8.2.1.2.6 Output Voltage Resistors Selection
The output voltage is set with a resistor divider created by RFBT and RFBB from the output node to the FB pin.
It is recommended to use 1% tolerance or better resistors. For this example design, 4.99 kΩ was selected for
RFBB. Using Equation 18, RFBT is calculated as 4.99 kΩ. This is a standard 1% resistor.
RFBT
§V
RFBB u ¨ OUT
© VREF
·
1¸
¹
(18)
If the PCB layout does not use the recommended AGND to PGND connection in Section 10.1, noise on the
feedback pin can degrade the output voltage regulation at max load. Use a smaller RFBB of 1.00 kΩ minimizes
the impact of this noise.
8.2.1.2.7 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. The
capacitor must be rated for at least 10-V to minimize DC bias derating.
A resistor can be added in series with the BOOT capacitor to slow down the turnon of the high-side MOSFET
and rising edge overshoot on the SW pin. This comes with the trade off of more power loss and lower efficiency.
As a best prectice, include a 0-Ω placeholder in all prototype designs in case parasitic inductance in the PCB
layout results in more voltage overshoot at the SW pin than is normal. This helps keep the voltage within the
ratings of the device and reduces the high frequency noise on the SW node. The recommended BOOT resistor
value to decrease the SW pin overshoot is 2.2 Ω.
8.2.1.2.8 BP5 Capacitor Selection
A 2.2-µF ceramic capacitor must be connected between the BP5 pin and AGND for proper operation. The
capacitor must be rated for at least 10 V to minimize DC bias derating.
8.2.1.2.9 PGOOD Pullup Resistor
A 10-kΩ resistor is used to pull up the power good signal when FB conditions are met. The pullup voltage source
must be less than the 6-V absolute maximum of the PGOOD pin.
8.2.1.2.10 Current Limit Selection
The MODE pin is used to select between two current limit settings. Select the current limit setting whose
minimum is greater than at least 1.1 times the maximum steady state peak current. This is to provide margin for
component tolerance and load transients. For this design, the minimum current limit should be greater than 7.45
A so the high current limit setting is selected.
8.2.1.2.11 Soft-Start Time Selection
The MODE pin is used to select between four different soft-start times. This is useful if a load has specific
timing requirements for the output voltage of the regulator. A longer soft-start time is also useful if the output
capacitance is very large and would require large amounts of current to quickly charge the output capacitors
to the output voltage level. The large currents necessary to charge the capacitor can reach the current limit or
cause the input voltage rail to sag due excessive current draw from the input power supply. Limiting the output
voltage slew rate solves both of these problems. The example design has the soft-start time set to 1.0 ms. With
this soft-start time the current required to charge the output capacitors to the nominal output voltage is only 0.14
A.
24
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8.2.1.2.12 Ramp Selection and Control Loop Stability
The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends
on VOUT, fSW, LOUT, and COUT. To get started, calculate LC double pole frequency using Equation 19. The ratio
between fSW and fLC should then be calculated. Based on this ratio and the output voltage, the recommended
ramp setting should be selected using Figure 8-3. With a 1-V output, the 1-pF ramp is recommended for ratios
between approximately 35 and 58, the 2-pF ramp is recommended for ratios between approximately 58 and 86,
and the 4-pF ramp is recommended for ratios greater than approximately 86. In general, it is best to use the
largest ramp capacitor the design will support. Increasing the ramp capacitor improves transient response but
can reduce stability margin or increase on-time jitter.
For this design, fLC is 17.5 kHz and the ratio is 57 which is on the border of the 1-pF and 2-pF ramp settings.
Through bench evaluation, it was found that the design had sufficient stability margin with the 2-pF ramp so
this setting was selected for the best transient response. The recommended ramp settings given by Figure 8-3
include margin to account for potential component tolerances and variations across operating conditions so it is
possible to use a higher ramp setting as shown in this example.
fLC
1
2 u S u LOUT u COUT
(19)
5.5
5
Output Voltage (V)
4.5
4 pF
4
3.5
2 pF
3
2.5
2
1 pF
1.5
1
0.5
20
30
40
50
60
fSW/fLC
70
80
90
100
Figure 8-3. Recommended Ramp Settings
Use a feedforward capacitor (CFF) in parallel with the upper feedback resistor (RFBT) to add a zero into the
control loop to provide phase boost. Include a placeholder for this capacitor as the zero it provides can be
required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the
zero. The pole and zero frequency are not independent so as a result, once the zero location is chosen, the pole
is fixed as well. The zero is placed at 1/4 the fSW by calculating the value of CFF with Equation 20. The calculated
value is 128 pF — round this down to the closest standard value of 120 pF.
Using bench measurements of the AC response, the feedforward capacitor for this example design was
increased to 180 pF to improve the transient response.
CFF
1
S u RFBT u
fSW
2
(20)
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It is possible to use larger feedforward capacitors to further improve the transient response but take care to
ensure there is a minimum of -9-dB gain margin in all operating conditions. The feedforward capacitor injects
noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node.
Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 100-Ω resistor in series
with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB
layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer
together degrading the phase boost the feedforward capacitor provides.
When using higher ESR output capacitors, such as polymer or tantalum, their ESR zero (fESR) should be
accounted for. The ESR zero can be calculated using Equation 21. If the ESR zero frequency is less than the
estimated bandwidth of 1/10th the fSW, it can affect the gain margin and phase margin. A series R-C from the FB
pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this
design so the effect of the ESR zero is ignored.
fESR
1
2 u S u COUT u RESR
(21)
8.2.1.2.13 MODE Pin
The MODE resistor is set to 4.87 kΩ to select the high current limit setting, 1.0-ms soft-start and the 2 pF ramp.
See Table 7-4 for the full list of the MODE pin settings.
26
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8.2.1.3 Application Curves
100
1.008
95
1.007
1.006
1.005
Output Voltage (V)
85
80
75
70
1.004
1.003
1.002
1.001
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 18 V
65
1
VIN = 5 V
VIN = 12 V
VIN = 18 V
0.999
60
0.998
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
0
Figure 8-4. Efficiency
IOUT = 0 A
IOUT = 3 A
IOUT = 6 A
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
60
180
40
120
20
60
0
0
1.005
1.004
Gain (dB)
Output Voltage (V)
1.006
1
Figure 8-5. Load Regulation
1.008
1.007
0.5
1.003
1.002
Phase (°)
Efficiency (%)
90
1.001
1
-20
-60
Gain
Phase
0.999
0.998
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Input Voltage (V)
Figure 8-6. Line Regulation
-40
100 200
500 1000
10000
Frequency (Hz)
VIN = 12 V
100000
-120
1000000
ROUT = 0.3 Ω
Figure 8-7. Bode Plot
EN (2 V/div)
VOUT AC (20 mV/div)
BP5 (5 V/div)
VOUT (500 mV/div)
IOUT (1 A/div)
PGOOD (5 V/div)
Time (100 µs/div)
VIN = 12 V
IOUT(DC) = 1.5 A
Time (400 µs/div)
ISTEP = 3 A at 1A/µs
Figure 8-8. Load Transient
VIN = 12 V
IOUT = 0 A
Figure 8-9. EN Start-up – Measuring BP5
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EN (2 V/div)
EN (2 V/div)
SW (10 V/div)
SW (10 V/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (400 µs/div)
VIN = 12 V
Time (400 µs/div)
IOUT = 0 A
VIN = 12 V
Figure 8-10. EN Startup – Measuring SW
IOUT = 0 A
Figure 8-11. EN Shutdown
EN (2 V/div)
EN (2 V/div)
SW (10 V/div)
IOUT (5 A/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (400 µs/div)
VIN = 12 V
Time (400 µs/div)
ROUT = 0.2 Ω
Figure 8-12. EN Start-up – With Load
VIN = 12 V
IOUT = 0 A
Figure 8-13. EN Start-up – 0.5-V Prebias
VIN (10 V/div)
VIN (10 V/div)
EN (2 V/div)
EN (2 V/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (400 µs/div)
Time (1 ms/div)
ROUT = 0.3 Ω
ROUT = 0.3 Ω
Figure 8-14. VIN Start-up
28
Figure 8-15. VIN Shutdown
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VOUT AC (10 mV/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
VIN = 12 V
Time (1 µs/div)
IOUT = 0 A
Figure 8-16. Output Ripple – No Load
VIN = 12 V
IOUT = 6 A
Figure 8-17. Output Ripple – 6-A Load
VIN AC (10 mV/div)
VIN AC (50 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
VIN = 12 V
Time (1 µs/div)
IOUT = 0 A
Figure 8-18. Input Ripple – No Load
VIN = 12 V
IOUT = 6 A
Figure 8-19. Input Ripple – 6-A Load
SW (5 V/div)
SW (5 V/div)
VOUT (500 mV/div)
VOUT (500 mV/div)
IL (5 A/div)
IL (5 A/div)
Time (20 µs/div)
Time (10 µs/div)
VIN = 12 V
VIN = 12 V
Figure 8-20. Overcurrent Protection – Overload
Figure 8-21. Overcurrent Protection – Short
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SW (5 V/div)
VOUT (500 mV/div)
IL (5 A/div)
Time (2 ms/div)
VIN = 12 V
Figure 8-22. Overcurrent Protection – Hiccup and Recover
30
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8.2.2 1.0-V Output, 1.5-MHz Application
VIN
VIN
CBULK
35V
100uF
CI1
0805
25V
10uF
CI2
0805
25V
10uF
CHF1
0402
50V
0.1uF
CHF2
0402
50V
0.1uF
PGND
U2
VIN
VIN
SW
SW
10
13
EN
7
EN
BOOT
14
FSEL
1
SYNC/FSEL
MODE
2
BP5
RFSEL
8.06k
4
AGND
5
PGND
PGND
9
11
PGOOD
6
BP5
VOUT
SW
CBT
XEL4030-471MEB
470nH
CO1
0805
10V
47µF
FB 0402
50V
0.1uF
FB
MODE
PGOOD 3
RPG
10k
LO
8
12
Net-Tie
VO_SNS
VO_SNS
PGND
Net-Tie
RBODE
10.0
CFF
470pF
TPS543620RPY
RMODE
4.87k
CO2
0805
10V
47µF
BODE
CBP5
0603
2.2µF
10V
PGND
AGND
RFBT
FB
1.00k
Note: RBODE for measurement purposes only
RFBB
1.00k
AGND
AGND
Figure 8-23. 12-V Input, 1.0-V Output, 1.5-MHz Schematic
8.2.2.1 Design Requirements
Table 8-3. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
4 to 13.2 V, 12 V nominal
Output voltage (VOUT)
1.0 V
Output current rating (IOUT)
6A
Switching frequency (fSW)
1500 kHz
Steady state output ripple voltage
10 mV
Output current load step
3A
Transient response
± 30 mV (± 3%)
8.2.2.2 Detailed Design Procedure
Follow the design procedure in Section 8.2.1.2 for selecting the external components in this example application.
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8.2.2.3 Application Curves
100
95
VOUT AC (20 mV/div)
Efficiency (%)
90
85
80
75
70
IOUT (1 A/div)
65
VIN = 5 V
VIN = 12 V
60
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
Time (40 µs/div)
VIN = 12 V
Figure 8-24. Efficiency
ISTEP = 3 A at 1A/µs
Figure 8-25. Load Transient
1.01
VIN = 5 V
VIN = 12 V
VIN = 15 V
1.009
1.008
60
180
40
120
20
60
0
0
1.006
1.005
Phase (°)
1.007
Gain (dB)
Output Voltage (V)
IOUT(DC) = 1.5 A
1.004
1.003
-20
-60
1.002
Gain
Phase
1.001
-40
100 200
1
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
500 1000
10000
Frequency (Hz)
VIN = 12 V
Figure 8-26. Load Regulation
100000
-120
1000000
ROUT = 0.3 Ω
Figure 8-27. Bode Plot
VOUT AC (10 mV/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
VIN = 12 V
Time (1 µs/div)
IOUT = 0 A
Figure 8-28. Output Ripple – No Load
32
VIN = 12 V
IOUT = 6 A
Figure 8-29. Output Ripple – 6-A Load
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8.2.3 3.3-V Output, 1.0-MHz Application
VIN
VIN
CI1
0805
25V
10uF
CBULK
35V
100uF
PGND
CI2
0805
25V
10uF
CHF1
0402
50V
0.1uF
CHF2
0402
50V
0.1uF
U2
8
12
VIN
VIN
SW
SW
10
13
EN
7
EN
BOOT
14
FSEL
1
SYNC/FSEL
VIN
RENT
16.9k
MODE
2
BP5
RPG
10k
RENB
6.04k
RFSEL
11.8k
4
AGND
5
PGND
PGND
9
11
PGOOD
6
BP5
CBT
XEL5050-182MEC
1.8µH
CO1
0805
10V
47µF
FB 0402
50V
0.1uF
FB
MODE
PGOOD 3
VOUT
LO
SW
Net-Tie
VO_SNS
VO_SNS
PGND
Net-Tie
RBODE
10.0
CFF
33pF
TPS543620RPY
RMODE
11.3k
CO2
0805
10V
47µF
BODE
CBP5
0603
2.2µF
10V
PGND
AGND
RFBT
FB
28.0k
Note: RBODE for measurement purposes only
RFBB
4.99k
AGND
AGND
Figure 8-30. 12-V Input, 3.3-V Output, 1.0-MHz Schematic
8.2.3.1 Design Requirements
For this design example, use the parameters shown in Table 8-4.
Table 8-4. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
4 to 18 V, 12 V nominal
Output voltage (VOUT)
3.3 V
Output current rating (IOUT)
6A
Switching frequency (fSW)
1000 kHz
Steady state output ripple voltage
10 mV
Output current load step
3A
Transient response
± 99 mV (± 3%)
8.2.3.2 Detailed Design Procedure
Follow the design procedure in Section 8.2.1.2 for selecting the external components in this example application.
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8.2.3.3 Application Curves
100
95
VOUT AC (100 mV/div)
Efficiency (%)
90
85
80
75
70
IOUT (1 A/div)
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 18 V
65
Time (100 µs/div)
60
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
VIN = 12 V
6
IOUT(DC) = 1.5 A ISTEP = 3 A at 1A/µs
Figure 8-32. Load Transient
Figure 8-31. Efficiency
0.5
60
180
40
120
20
60
0
0
0.2
Gain (dB)
Output Regulation (%)
0.3
0.1
0
-0.1
-20
-0.2
-0.4
-40
100 200
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
5001000
VIN = 12 V
-0.5
0
-60
Gain
Phase
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 18 V
-0.3
Phase (°)
0.4
6
10000
Frequency (Hz)
100000
-120
1000000
ROUT = 1.1 Ω
Figure 8-34. Bode Plot
Figure 8-33. Load Regulation
VOUT AC (10 mV/div)
VOUT AC (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (1 µs/div)
VIN = 12 V
Time (1 µs/div)
IOUT = 0 A
VIN = 12 V
Figure 8-35. Output Ripple – No Load
34
IOUT = 6 A
Figure 8-36. Output Ripple – 6-A Load
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8.2.4 1.8-V Output, 1.0-MHz Typical Application
VIN
VIN
BOOT
BP5
SW 13
EN
SW 10
0.1 µF
2×0.1 µF
2.2 µF
VOUT = 1.8 V
68 pF
SYNC/FSEL
4.87 k
11.8 k
MODE
13.0 k
1.0 µH
TPS543620
PGOOD
2×47 µF
FB
AGND
4.99 k
2×10 µF
PGND
Figure 8-37. 12-V Input, 1.8-V Output, 1.0-MHz Schematic
8.2.4.1 Design Requirements
Table 8-5. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
4 to 18 V, 12 V nominal
Output voltage (VOUT)
1.8 V
Output current rating (IOUT)
6A
Switching frequency (fSW)
1000 kHz
8.2.4.2 Detailed Design Procedure
Follow the design procedure in Section 8.2.1.2 for selecting the external components in this example application.
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8.2.5 5.0-V Output, 1.0-MHz Typical Application
VIN
VIN
BOOT
BP5
SW 13
EN
SW 10
0.1 µF
2×0.1 µF
2.2 µF
VOUT = 5.0 V
22 pF
SYNC/FSEL
11.3 k
11.8 k
MODE
45.3 k
2.2 µH
TPS543620
PGOOD
2×22 µF
FB
AGND
4.99 k
2×10 µF
PGND
Figure 8-38. 12-V Input, 5.0-V Output, 1.0-MHz Schematic
8.2.5.1 Design Requirements
Table 8-6. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
8 to 18 V, 12 V nominal
Output voltage (VOUT)
5V
Output current rating (IOUT)
6A
Switching frequency (fSW)
1000 kHz
8.2.5.2 Detailed Design Procedure
Follow the design procedure in Section 8.2.1.2 for selecting the external components in this example application.
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9 Power Supply Recommendations
The TPS543620 is designed to operate from an input voltage supply range between 4 V and 18 V. This supply
voltage must be well regulated. Proper bypassing of the input supply is critical for proper electrical performance,
as is the PCB layout and the grounding scheme. A minimum of 4 μF (after derating) ceramic capacitance, type
X5R or better, must be placed near the device. TI recommends splitting the ceramic input capacitance equally
between the VIN and PGND pins on each side of the device resulting in at least 2 µF of ceramic capacitance on
each side of the device.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. See Figure 10-1 for a PCB layout example. Key
guidelines to follow for the layout are:
• VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat
dissipation.
• Place a 10-nF to 100-nF capacitor from each VIN to PGND pin and place them as close as possible to
the device on the same side of the PCB. Place the remaining ceramic input capacitance next to these high
frequency bypass capacitors. The remaining input capacitance can be placed on the other side of the board
but use as many vias as possible to minimize impedance between the capacitors and the pins of the IC.
• Use multiple vias near the PGND pins and use the layer directly below the device to connect them together.
This helps to minimize noise and can help heat dissipation.
• Use vias near both VIN pins and provide a low impedance connection between them through an internal
layer.
• Place the inductor as close as possible to the device to minimize the length of the SW node routing.
• Place the BOOT-SW capacitor as close as possible to the BOOT and SW pins.
• Place the BP5 capacitor as close as possible to the BP5 and AGND pins.
• Place the bottom resistor in the FB divider as close as possible to the FB and AGND pins of the IC. Also keep
the upper feedback resistor and the feedforward capacitor near the IC. Connect the FB divider to the output
voltage at the desired point of regulation.
• Use multiple vias in the AGND island to connect it back to internal PGND layers. Do not place these vias
between the BP5 capacitor and the AGND pin. These vias will conduct switching currents between the BP5
capacitor and PGND. Placing the vias near the AGND pin can add noise to the FB divider.
• Return the FSEL and MODE resistors to a quiet AGND island.
10.2 Layout Example
PGND
1210
0805
VIN
0805
0402
0402
VIN
PGND
SW
SYNC
/FSEL
0402
BOOT
0402
SW
MODE
0402
PGOOD
4mm x 4mm
VOUT
Avoid vias
here
PGND
VIN
EN
AGND
BP5
0402
0402
AGND
0402
FB
0402
0402
0402
0805
Connect AGND to PGND
near the BP5 cap
VIN
1210
0805
0402
PGND
Figure 10-1. Example PCB Layout
38
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10.2.1 Thermal Performance
Test Conditions: fSW = 1 MHz, Vin = 12 V, Vout = 1 V, Iout = 6 A, Inductor = 600 nH (4.44 mΩ typ), Ambient
temperature = 25°C
Figure 10-2. Thermal Image at 25°C Ambient
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Test Conditions: fSW = 1 MHz, Vin = 12 V, Vout = 3.3 V, Iout = 6 A, Inductor = 1.8 μH (9.6 mΩ typ), Ambient
temperature = 25°C
Figure 10-3. Thermal Image at 25°C Ambient
40
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS543620RPYR
ACTIVE
VQFN-HR
RPY
14
3000
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 150
543620
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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