TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
4.5V to 18V Input, 4-A Synchronous Step-Down SWIFT™ Converter with Eco-Mode™
Check for Samples: TPS54426
FEATURES
DESCRIPTION
•
The TPS54426 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54426
enables system designers to complete the suite of
various end equipment’s power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54426 uses the D-CAP2™ mode control which
provides a very fast transient response with no
external compensation components. The adaptive
on-time control supports seamless transition between
PWM mode at higher load conditions and
Eco-mode™ operation at light loads. Eco-mode™
allows the TPS54426 to maintain high efficiency
during lighter load conditions. The TPS54426 also
has a proprietary circuit that enables the device to
adopt to both low equivalent series resistance (ESR)
output capacitors, such as POSCAP, SP-CAP, and
ultra-low ESR ceramic capacitors. The device
operates from 4.5-V to 18-V VIN input. The output
voltage can be programmed between 0.76 V and 5.5
V. The device also features an adjustable soft start
time and a power good function. The TPS54426 is
available in the 14-pin HTSSOP package and the 16
pin QFN package, designed to operate from –40°C to
85°C.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 5.5 V
Highly Efficient Integrated FET’s Optimized
for Lower Duty Cycle Applications
– 65 mΩ (High Side) and 55 mΩ (Low Side)
High Efficiency, less than 10 μA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
700-kHz Switching Frequency (fSW)
Cycle By Cycle Over Current Limit
Power Good Output
Auto-Skip Eco-mode™ for High Efficiency at
Light Load
APPLICATIONS
•
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
Vout (50 mV/div)
Iout (2 A/div)
100 ms/div
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
PACKAGE
(2) (3)
ORDERABLE PART NUMBER
PowerPAD™
(HTSSOP) – PWP
Plastic Quad Flat Pack (QFN)
(2)
(3)
TRANSPORT MEDIA
Tube
14
TPS54426PWPR
–45°C to 85°C
(1)
PIN
TPS54426PWP
TPS54426RSAT
Tape and Reel
Tape and Reel
16
TPS54426RSAR
Tape and Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range
VALUE
UNIT
VIN1, VIN2, EN
–0.3 to 20
V
VBST
–0.3 to 26
V
VBST (10 ns transient)
–0.3 to 28
V
VFB, VO, SS, PG
–0.3 to 6.5
V
SW1, SW2
–2 to 20
V
SW1, SW2 (10 ns transient)
–3 to 22
V
VREG5
–0.3 to 6.5
V
PGND1, PGND2
–0.3 to 0.3
V
–0.2 to 0.2
V
2
kV
VO
Output voltage range
Vdiff
Voltage from GND to POWERPAD
ESD rating
Electrostatic
discharge
TJ
Tstg
(1)
(1)
Human Body Model (HBM)
Charged Device Model (CDM)
500
V
Operating junction temperature
–40 to 150
°C
Storage temperature
–55 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS54426
PWP (14) PINS
RSA (16) PINS
θJA
Junction-to-ambient thermal resistance
55.6
37.3
θJCtop
Junction-to-case (top) thermal resistance
51.3
42.5
θJB
Junction-to-board thermal resistance
36.4
14.9
ψJT
Junction-to-top characterization parameter
1.8
0.8
ψJB
Junction-to-board characterization parameter
20.6
14.8
θJCbot
Junction-to-case (bottom) thermal resistance
4.3
4.9
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VIN
Supply input voltage range
VI
Input voltage range
MIN
MAX
4.5
18
VBST
–0.3
24
VBST (10 ns transient)
–0.3
27
SS, PG
–0.1
5.7
EN
–0.1
18
VO, VFB
–0.1
5.5
SW1, SW2
–1.8
18
UNIT
V
V
–3
21
PGND1, PGND2
–0.1
0.1
–0.1
5.7
V
SW1, SW2 (10 ns transient)
VO
Output voltage range
VREG5
IO
Output Current range
IVREG5
0
10
mA
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
TYP
MAX
UNIT
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
850
1300
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
1.8
10
μA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
2
V
0.4
V
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB voltage light load mode, TA = 25°C,
VO = 1.05 V, IO = 10mA
VFBTH
VFB threshold voltage
771
TA = 25°C, VO = 1.05 V, continuous mode
757
TA = 0°C to 85°C, VO = 1.05 V, continuous
mode (1)
753
777
TA = –40°C to 85°C, VO = 1.05 V, continuous
mode (1)
751
779
IVFB
VFB input current
VFB = 0.8 V, TA = 25°C
RDischg
VO discharge resistance
EN = 0 V, VO = 0.5 V, TA = 25°C
765
773
mV
0
±0.1
μA
50
100
Ω
5.5
5.7
V
20
mV
100
mV
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VLN5
Line regulation
6.0 V < VIN < 18 V, IVREG5 = 5 mA
VLD5
Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
Output current
VIN = 6 V, VREG5 = 4 V, TA = 25°C
70
mA
Rdsonh
High side switch resistance
25°C, VBST - SW1,2 = 5.5 V
63
mΩ
Rdsonl
Low side switch resistance
25°C
55
mΩ
5.3
MOSFET
(1)
Not production tested.
3
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SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.7
5.4
7.5
UNIT
CURRENT LIMIT
Iocl
Current limit
LOUT = 1.5 μH (2), TA = -20 ºC to 85 ºC
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(2)
165
(2)
°C
30
ON-TIME TIMER CONTROL
TON
On time
VIN = 12 V, VO = 1.05 V
145
ns
TOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
260
310
ns
2.6
μA
SOFT START
ISSC
SS charge current
VSS = 0 V
1.4
2.0
ISSD
SS discharge current
VSS = 0.5 V
0.1
0.2
VFB rising (good)
85
90
mA
POWER GOOD
VTHPG
PG threshold
IPG
PG sink current
VFB falling (fault)
95
%
85
%
2.5
5
mA
OVP detect
115
120
UVP detect
60
PG = 0.5 V
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
TOVPDEL
Output OVP prop delay
VUVP
Output UVP trip threshold
TUVPDEL
Output UVP delay
TUVPEN
Output UVP enable delay
125
μs
10
Hysteresis
Relative to soft-start time
65
%
70
%
10
%
0.25
ms
x 1.7
UVLO
VUVLO
(2)
UVLO threshold
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.5
3.8
4.1
0.23
0.35
0.47
V
Not production tested.
4
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SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
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DEVICE INFORMATION
VO
1
14
VIN2
VFB
2
13
VIN1
VREG5
3
12
VBST
SS
4
11
SW2
2
VIN2
VIN1
14
13
12
VBST
11
SW3
POWER PAD
SS
3
10
SW2
GND
4
9
SW1
PG
6
9
PGND2
EN
7
8
PGND1
5
6
7
8
PGND2
SW1
PGND1
10
VREG5
15
EN
5
1
16
PG
GND
POWER PAD
VFB
VIN3
PWP PACKAGE
(TOP VIEW)
VO
RSA PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
NAME
DESCRIPTION
NUMBER
PWP 14
RSA 16
VO
1
16
Connect to output of converter. This terminal is used for On-Time Adjustment.
VFB
2
1
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
2
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not
active when EN is low.
SS
4
3
Soft-start control. A external capacitor should be connected to GND.
GND
5
4
Signal ground pin.
PG
6
5
Open drain power good output.
EN
7
6
Enable control input. EN is active high and must be pulled up to enable the device.
8, 9
7, 8
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect
PGND and GND strongly together near the IC.
10, 11
9, 10, 11
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to
current comparators.
12
12
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
13, 14
13, 14, 15
Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator
for the control circuitry.
Back side
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be
connected to PGND.
PGND1,
PGND2
SW1, SW2
VBST
VIN1, VIN2
PowerPAD™
5
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FUNCTIONAL BLOCK DIAGRAM
-35%
UV
14
OV
13
1
VO
VIN2
VIN
VIN1
+20%
VREG5
12
Control logic
VBST
Ref
SS
1 shot
SW
VFB
SGND
10
XCON
VREG5
VREG5
Ceramic
Capacitor
3
SS
1mF
VO
11
2
9
4
8
SW
Softstart
SS
PGND
5
PGND
ZC
PGND
GND
SW
OCP
SGND
PG
PGND
Ref
VCC
6
-10%
UV
VREG5
EN
7
A.
EN
Logic
OV
UVLO
UVLO
Protection
Logic
TSD
REF
Ref
The block diagram shown is for the PWP 14 pin package. The QFN 16 pin package block diagram is identical except
for the pin out.
6
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TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
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OVERVIEW
The TPS54426 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and
auto-skip Eco-mode™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54426 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal
one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,
to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below
the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54426 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54426 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-Mode™ Control
The TPS54426 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
(VIN - VOUT )×VOUT
1
I OUT ( LL ) =
=
VIN
2 × L × fsw
(1)
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
2 μA.
C6(nF) • Vref
C6(nF) • 0.765
Tss(ms) = − = −
Iss(µA)
2
(2)
The TPS54426 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
7
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Power Good
The TPS54426 has power-good open drain output. The power good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is
within -10% of the target value, internal comparators detect power good state and the power good signal
becomes high. Rpg resister value ,which is connected between PG and VREG5, is required from 20kΩ to 150kΩ.
If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 5 μs
internal delay.
VREG5
VREG5 is an internally generated voltage source used by the TPS54425. It is derived directly from the input
voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5
regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage
(3.8 V typical) for the TPS54425 to function. Connect a 1.0 µF capacitor between pin 3 of the TPS54425 and
power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external use
and can typically source up to 70 mA. The VREG5 output is disabled when the TPS54425 EN pin is open or
pulled low.
Output Discharge Control
TPS54426 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected
from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to
avoid the possibility of causing negative voltage at the output.
Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the measured voltage is
above the voltage proportional to the current limit. Then, the device constantly monitors the low-side FET switch
voltage, which is proportional to the switch current, during the low-side on-time.
The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to
the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current one half of the
peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output under-voltage protection circuit to be activated. When the overcurrent
condition is removed, the output voltage will return to the regulated value. This protection is non-latching.
Over/Under Voltage Protection
TPS54426 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback
voltage becomes lower than 65% of the target voltage, the UVP comparator output goes high and an internal
UVP delay counter begins. After 250 μs, the device latches off both internal top and bottom MOSFET. This
function is enabled approximately 1.7 x softstart time.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54426 is shut off. This is protection is non-latching.
8
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Thermal Shutdown
TPS54426 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
SPACER
TYPICAL CHARACTERISTICS
Vin CURRENT
vs
JUNCTION TEMPERATURE
Vin SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
1200
8
Ivccsdn - Shutdown Current - mA
ICC - Supply Current - mA
1000
800
600
400
6
4
2
200
0
-50
0
50
100
TJ - Junction Temperature - °C
0
-50
150
0
150
Figure 1.
Figure 2.
EN CURRENT
vs
EN VOLTAGE
1.05V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.1
100
VI = 18 V
80
1.075
VO - Output Voltage -V
EN Input Current - mA
50
100
TJ - Junction Temperature - °C
60
40
VI = 12 V
1.05
VI = 5 V
1.025
20
1
0
0
5
10
EN Input Voltage - V
15
20
0
Figure 3.
1
2
IO - Output Current - A
3
4
Figure 4.
9
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TYPICAL CHARACTERISTICS (continued)
1.05V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.05V 50mA to 4A LOAD TRANSIENT RESPONSE
1.1
Vout (50 mV/div)
VO - Output Voltage -V
1.075
IO = 10 mA
IO = 1 A
1.05
Iout (2 A/div)
1.025
1
0
5
10
VI - Input Voltage - V
15
20
100 ms/div
Figure 5.
Figure 6.
STARTUP WAVEFORM
EFFICIENCY
vs
OUTPUT CURRENT
100
VO = 3.3 V
90
EN - 10 V/div
VOUT - 0.5 V/div
Efficiency - %
80
VO = 1.8 V
VO = 2.5 V
70
60
50
PG - 5 V/div
40
0
1
2
IO - Output Current - A
3
4
400 ms/div
Figure 7.
Figure 8.
10
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TYPICAL CHARACTERISTICS (continued)
LIGHT LOAD EFFICIENCY
vs
OUTPUT CURRENT
SWITCHING FREQUENCY
vs
INPUT VOLTAGE (IO=1A)
100
800
VO = 3.3 V
VO = 2.5 V
fsw - Switching Frequency - kHz
Efficiency - %
80
VO = 1.8 V
60
40
20
0
0.001
0.01
IO - Output Current - A
VO = 1.8 V
700
600
VO = 3.3 V
500
400
0.1
0
5
10
VI - Input Voltage - V
15
Figure 9.
Figure 10.
WITCHING FREQUENCY
vs
OUTPUT CURRENT
VOLTAGE RIPPLE AT OUTPUT (IO=4A)
20
800
fsw - Switching Frequency - kHz
700
VO (10 mV/div)
600
VO = 1.8 V
500
400
VO = 2.5 V
300
SW (5 V/div)
200
100
0
0.001
0.01
0.1
IO - Output Current - A
1
10
Figure 11.
Figure 12.
VOLTAGE RIPPLE AT INPUT (IO=4A)
VIN (50 mV/div)
SW (5 V/div)
Figure 13.
11
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54426
TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
DESIGN GUIDE
Step By Step Design Procedure
To
•
•
•
•
•
begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
Figure 14. Schematic Diagram for This Design Example
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 and Equation 4 to calculate VOUT
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable
For output voltage from 0.76 V to 2.5 V:
(
R1
VOUT = 0.765 • 1 + −
R2
)
(3)
For output voltage over 2.5 V:
(
R1
¾
VOUT = (0.763 + 0.0017 · VOUT_SET) · 1 + R2
)
(4)
Where:
VOUT_SET = Target VOUT voltage
Output Filter Selection
The output filter used with the TPS54426 is an LC circuit. This LC filter has double pole at:
FP =
1
2p LOUT ´ COUT
(5)
12
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54426
TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54426. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 5 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
Table 1. Recommended Component Values
C4 (pF) (1)
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
C8 + C9 (µF)
1
6.81
22.1
1.5
22 - 68
1.05
8.25
22.1
1.5
22 - 68
1.2
12.7
22.1
1.5
22 - 68
1.8
30.1
22.1
10 - 22
2.2
22 - 68
2.5
49.9
22.1
10 - 22
2.2
22 - 68
3.3
73.2
22.1
10 - 22
2.2
22 - 68
5
121
22.1
10 - 22
3.3
22 - 68
(1)
Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1.
Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output
voltage increases. For higher output voltages above 1.8 V, additional phase boost can be achieved by adding a
feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 6,
Equation 7 and Equation 8. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
VOUT VIN (max) - VOUT
•
Ilp - p = V
L •f
IN (max)
O
(6)
SW
Ilp - p
Ilpeak = IO +
2
−
1 Ilp - p2
ILo(RMS) = IO2 + −
12
(7)
√
(8)
For this design example, the calculated peak current is 4.47A and the calculated RMS current is 4.009 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54426 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 9 to
determine the required RMS current rating for the output capacitor
VOUT • (VIN - VOUT)
ICO(RMS) =−
−
√12 • VIN • LO • fSW
(9)
For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is .271A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS54426 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 uF. is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.
13
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54426
TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
Bootstrap Capacitor Selection
A 0.1 μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 1.0 μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
THERMAL INFORMATION
This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
14
Thermal Pad
2.46
°
7
1
2.31
Figure 15. Thermal Pad Dimensions
14
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54426
TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
VIN
Additional
Thermal
Vias
FEEDBACK
RESISTORS
VOUT
BIAS
CAP
Connection to
POWER GROUND
on internal or
bottom layer
SLOW
START
CAP
ANALOG
GROUND
TRACE
To Enable
Control
VIN
INPUT
BYPASS
CAPACITOR
VIN OVER
CURRENT
STABILITY
CAPACITOR
EXPOSED
POWERPAD
AREA
VIN2
VFB
VIN1
VREG5
VBST
SS
SW1
GND
SW2
PG
PGND1
EN
PGND2
BOOST
CAPACITOR
OUTPUT
INDUCTOR
VOUT
OUTPUT
FILTER
CAPACITOR
Additional
Thermal
Vias
POWER GROUND
VIA to Ground Plane
Etch on Bottom Layer
or Under Component
Figure 16. PCB Layout
15
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54426
TPS54426
SLVSAD6C – AUGUST 2010 – REVISED JULY 2011
www.ti.com
REVISION HISTORY
Changes from Revision # (August 2010) to Revision A
•
Page
Added VIN = 12V to condition in Electrical Characteristics table .......................................................................................... 3
Changes from Revision A (November 2010) to Revision B
Page
•
Added the RSA (16 pin QFN package) to: DESCRIPTION, ORDERING INFORMATION, THERMAL
INFORMATION, and DEVICE INFORMATION sections ...................................................................................................... 1
•
Changed the Functional Block Diagram ............................................................................................................................... 6
•
Changed the Power Good and Current Protection sections ................................................................................................. 8
•
Added Note 1 to Table 1 ..................................................................................................................................................... 13
Changes from Revision B (November 2010) to Revision C
•
Page
Changed ELEC CHAR table, UVLO threshold MIN from 3.55 V to 3.5 V, MAX from 4.05 V to 4.1 V ................................. 4
16
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54426
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54426PWP
ACTIVE
HTSSOP
PWP
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54426
TPS54426PWPR
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54426
TPS54426RSAR
ACTIVE
QFN
RSA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54426
TPS54426RSAT
ACTIVE
QFN
RSA
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54426
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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