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Table of Contents
User’s Guide
TPS54429 Step-Down Converter Evaluation Module User's
Guide
ABSTRACT
This user's guide contains information for the TPS54429 as well as support documentation for the
TPS54429EVM-608 evaluation module. Included are the performance specifications, schematic, and the bill
of materials of the TPS54429EVM-608.
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Performance Specification Summary................................................................................................................................... 3
3 Modifications...........................................................................................................................................................................4
3.1 Output Voltage Setpoint..................................................................................................................................................... 4
4 Test Setup and Results.......................................................................................................................................................... 4
4.1 Input/Output Connections.................................................................................................................................................. 5
4.2 Start-Up Procedure............................................................................................................................................................ 5
4.3 Efficiency............................................................................................................................................................................6
4.4 Load Regulation................................................................................................................................................................. 7
4.5 Line Regulation.................................................................................................................................................................. 7
4.6 Load Transient Response.................................................................................................................................................. 8
4.7 Output Voltage Ripple........................................................................................................................................................ 8
4.8 Input Voltage Ripple........................................................................................................................................................... 9
4.9 Start-Up..............................................................................................................................................................................9
5 Board Layout......................................................................................................................................................................... 11
5.1 Layout...............................................................................................................................................................................11
6 Schematic, Bill of Materials, and Reference...................................................................................................................... 15
6.1 Schematic........................................................................................................................................................................ 15
6.2 Bill of Materials.................................................................................................................................................................15
6.3 Reference.........................................................................................................................................................................15
7 Revision History................................................................................................................................................................... 15
List of Figures
Figure 4-1. TPS54429EVM-608 Efficiency.................................................................................................................................. 6
Figure 4-2. TPS54429EVM-608 Light Load Efficiency................................................................................................................ 6
Figure 4-3. TPS54429EVM-608 Load Regulation....................................................................................................................... 7
Figure 4-4. TPS54429EVM-608 Line Regulation........................................................................................................................ 7
Figure 4-5. TPS54429EVM-608 Load Transient Response........................................................................................................ 8
Figure 4-6. TPS54429EVM-608 Output Voltage Ripple.............................................................................................................. 8
Figure 4-7. TPS54429EVM-608 Input Voltage Ripple................................................................................................................. 9
Figure 4-8. TPS54429EVM-608 Start-Up Relative to VIN ........................................................................................................... 9
Figure 4-9. TPS54429EVM-608 Start-Up Relative to EN.......................................................................................................... 10
Figure 5-1. Top Assembly.......................................................................................................................................................... 11
Figure 5-2. Top Layer.................................................................................................................................................................12
Figure 5-3. Internal Layer 1....................................................................................................................................................... 12
Figure 5-4. Internal Layer 2....................................................................................................................................................... 13
Figure 5-5. Bottom Layer........................................................................................................................................................... 13
Figure 5-6. Bottom Assembly.................................................................................................................................................... 14
Figure 6-1. TPS54429EVM-608 Schematic Diagram................................................................................................................ 15
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Trademarks
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List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................3
Table 2-1. TPS54429EVM-608 Performance Specifications Summary.......................................................................................3
Table 3-1. Output Voltages.......................................................................................................................................................... 4
Table 4-1. Connection and Test Points........................................................................................................................................ 5
Table 6-1. Bill of Materials..........................................................................................................................................................15
Trademarks
D-CAP2™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
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Introduction
1 Introduction
The TPS54429 is a single, adaptive on-time, D-CAP2™-mode, synchronous buck converter that requires a very
low external component count. The D-CAP2 control circuit is optimized for low-ESR output capacitors such as
POSCAP, SP-CAP, or ceramic types and features fast transient response with no external compensation. The
switching frequency is internally set at a nominal 700 kHz. The high-side and low-side switching MOSFETs
are incorporated inside the TPS54429 package along with the gate drive circuitry. The low drain-to-source on
resistance of the MOSFETs allows the TPS54429 to achieve high efficiencies and helps keep the junction
temperature low at high output currents. The TPS54429 dc/dc synchronous converter is designed to provide up
to a 4.5-A output from an input voltage source of 7 V to 18 V. The output voltage range is from 0.76 V to 5.5 V.
Rated input voltage and output current range for the evaluation module are given in Table 1-1.
The TPS54429EVM-608 evaluation module is a single, synchronous buck converter providing 1.05 V at 4.5 A
from 7-V to 18-V input. This user’s guide describes the TPS54429EVM-608 performance.
Table 1-1. Input Voltage and Output Current Summary
EVM
INPUT VOLTAGE RANGE
OUTPUT CURRENT RANGE
TPS54429EVM-608
VIN = 7 V to 18 V
0 A to 4.5 A
2 Performance Specification Summary
A summary of the TPS54429EVM-608 performance specifications is provided in Table 2-1. Specifications are
given for an input voltage of VIN = 12 V and an output voltage of 1.05 V, unless otherwise noted. The ambient
temperature is 25°C for all measurement, unless otherwise noted.
Table 2-1. TPS54429EVM-608 Performance Specifications Summary
SPECIFICATIONS
TEST CONDITIONS
Input voltage range (VIN)
MIN
TYP
MAX
7
12
18
Output voltage
Operating frequency
CH1
VIN = 12 V, IO = 1 A
Output current range
UNIT
V
1.05
V
700
kHz
0
4.5
A
Overcurrent limit
VIN = 12 V, LO = 1.5 µH
5.9
A
Output ripple voltage
VIN = 12 V, IO = 4.5 A
10
mVPP
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Modifications
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3 Modifications
These evaluation modules are designed to provide access to the features of the TPS54429. Some modifications
can be made to this module.
3.1 Output Voltage Setpoint
To change the output voltage of the EVMs, it is necessary to change the value of resistor R1. Changing the
value of R1 can change the output voltage above 0.765 V. The value of R1 for a specific output voltage can be
calculated using Equation 1 and Equation 2.
For output voltage from 0.76 V to 2.5 V:
æ R1 ö
VO = 0.765 ´ ç 1+
÷
è R2 ø
(1)
For output voltage over 2.5 V:
R1 ö
æ
VO = (0.763 + 0.0017 ´ VO) ´ ç 1+
÷
è R2 ø
(2)
Table 3-1 lists the R1 values for some common output voltages. For higher output voltages of 1.8 V or above, a
feedforward capacitor (C2) can be required to improve phase margin. Pads for this component (C2) are provided
on the printed-circuit board. Note that the values given in Table 3-1 are standard values and not the exact value
calculated using Table 3-1.
Table 3-1. Output Voltages
OUTPUT VOLTAGE
(V)
R1
(kΩ)
R2
(kΩ)
C2
(pF)
L1
(µH)
1.0
6.81
22.1
1.5
1.05
8.25
22.1
1.5
1.2
12.7
22.1
1.5
1.5
23.2
22.1
1.5
1.8
30.1
22.1
10 -22
2.2
2.5
49.9
22.1
10 -22
2.2
3.3
73.2
22.1
10 -22
2.2
5.0
121
22.1
10 -22
3.3
4 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54429EVM-608. The section also
includes test results typical for the following:
•
•
•
•
•
•
•
•
4
Evaluation modules and efficiency
Output load regulation
Output line regulation
Load transient response
Output voltage ripple
Input voltage ripple
Start-up
Switching frequency
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Test Setup and Results
4.1 Input/Output Connections
The TPS54429EVM-608 is provided with input/output connectors and test points as shown in Table 4-1. A power
supply capable of supplying 3 A must be connected to J1 through a pair of 20 AWG wires. The load must be
connected to J2 through a pair of 20 AWG wires. The maximum load current capability is 4.5 A. Wire lengths
must be minimized to reduce losses in the wires. Test point TP1 provides a place to monitor the VIN input
voltages with TP2 providing a convenient ground reference. TP7 is used to monitor the output voltage with TP8
as the ground reference.
Table 4-1. Connection and Test Points
REFERENCE DESIGNATOR
FUNCTION
J1
VIN (see Table 1-1 for VIN range)
J2
VOUT, 1.05 V at 4.5-A maximum
JP1
EN control. Connect EN to OFF to disable, connect EN to ON to enable.
TP1
VIN test point at VIN connector
TP2
GND test point at VIN
TP3
EN test point
TP4
Analog ground test point
TP5
Switch node test point
TP6
Power-good test point
TP7
Output voltage test point
TP8
Ground test point at output connector
4.2 Start-Up Procedure
1. Ensure that the jumper at JP1 (Enable control) is set from EN to OFF.
2. Apply appropriate VIN voltage to VIN and PGND terminals at J1.
3. Move the jumper at JP1 (Enable control) to cover EN and ON. The EVM enables the output voltage.
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Test Setup and Results
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4.3 Efficiency
Figure 4-1 shows the efficiency for the TPS54429EVM-608 at an ambient temperature of 25°C. The input
voltage is 12 V.
100
90
80
Efficiecny - %
70
60
50
40
30
20
10
0
0
0.5
1.5
1
2.5
2
3
3.5
4
4.5
Output Current - A
Figure 4-1. TPS54429EVM-608 Efficiency
Figure 4-2 shows the efficiency at light loads for the TPS54429EVM-608 at an ambient temperature of 25°C. The
input voltage is 12 V.
100
90
80
Efficiecny - %
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
10
Output Current - A
Figure 4-2. TPS54429EVM-608 Light Load Efficiency
6
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Test Setup and Results
4.4 Load Regulation
The load regulation for the TPS54429EVM-608 is shown in Figure 4-3.
1
0.8
Output Voltage Deviation - %
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
0.5
1.5
1
2.5
2
Output Current - A
3
3.5
4
4.5
Figure 4-3. TPS54429EVM-608 Load Regulation
4.5 Line Regulation
The line regulation for the TPS54429EVM-608 is shown in Figure 4-4. The load current is 2.25 A.
1
0.8
Output Voltage Deviation - %
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
6
9
12
Input Voltage - V
15
18
Figure 4-4. TPS54429EVM-608 Line Regulation
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4.6 Load Transient Response
The TPS54429EVM-608 response to load transient is shown in Figure 4-5. The current step is from 1.25 A to
3.25 A. Total peak-to-peak voltage variation is as shown.
VOUT = 20 mV / div (dc coupled, -1.013 V offset)
IOUT = 2 A / div
Load step = 1.25 A to 3.25 A Slew rate = 100 mA / µsec
Time = 100 µsec / div
Figure 4-5. TPS54429EVM-608 Load Transient Response
4.7 Output Voltage Ripple
The TPS54429EVM-608 output voltage ripple is shown in Figure 4-6. The output current is the rated full load of
4.5 A.
VOUT = 20 mV / div (ac coupled)
PH = 5 V / div
Time = 500 nsec / div
Figure 4-6. TPS54429EVM-608 Output Voltage Ripple
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Test Setup and Results
4.8 Input Voltage Ripple
The TPS54429EVM-608 input voltage ripple is shown in Figure 4-7. The output current is the rated full load of 4
A.
VIN = 100 mV / div (ac coupled)
PH = 5 V / div
Time = 500 nsec / div
Figure 4-7. TPS54429EVM-608 Input Voltage Ripple
4.9 Start-Up
The TPS54429EVM-608 start-up waveform relative to VIN is shown in Figure 4-8.
VIN = 5 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 4-8. TPS54429EVM-608 Start-Up Relative to VIN
The TPS54429EVM-608 start-up waveform relative to enable (EN) is shown in Figure 4-9.
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VIN = 5 V / div
EN = 10 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 4-9. TPS54429EVM-608 Start-Up Relative to EN
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Board Layout
5 Board Layout
This section provides description of the TPS54429EVM-608, board layout, and layer illustrations.
5.1 Layout
The board layout for the TPS54429EVM-608 is shown in Figure 5-1 through Figure 5-6. The top layer contains
the main power traces for VIN, VO, and ground. Also on the top layer are connections for the pins of the
TPS54429 and a large area filled with ground. Most of the signal traces also are located on the top side. The
input decoupling capacitors are located as close to the IC as possible. The input and output connectors, test
points, and most of the components are located on the top side. R4, the power-good pullup, is located on the
back side. Analog ground and power ground are connected at a single point on the top layer near pin 5 of the
TPS54429. The internal layer 1 is a split plane containing analog and power grounds. The internal layer 2 is
primarily power ground but also has a fill area of VIN and a trace routing VIN to the enable control jumper JP1.
The bottom layer is primarily analog ground but also has traces to connect VIN, traces for the power-good signal,
and the feedback trace from VOUT to the voltage setpoint divider network.
Figure 5-1. Top Assembly
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Figure 5-2. Top Layer
Figure 5-3. Internal Layer 1
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Board Layout
Figure 5-4. Internal Layer 2
Figure 5-5. Bottom Layer
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Figure 5-6. Bottom Assembly
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Schematic, Bill of Materials, and Reference
6 Schematic, Bill of Materials, and Reference
6.1 Schematic
Figure 6-1 is the schematic for the TPS54429EVM-608.
Figure 6-1. TPS54429EVM-608 Schematic Diagram
6.2 Bill of Materials
Table 6-1. Bill of Materials
REFDES
QTY
VALUE
DESCRIPTION
C1, C3
2
SIZE
PART NUMBER
MFR
10 μF
Capacitor, Ceramic, 25 V, X5R, 20%
1210
C3225X5R1E106M
C11
TDK
0
Open
Capacitor, Ceramic
1206
Std
Std
C2, C8
0
Open
Capacitor, Ceramic
0603
Std
Std
C5
1
3300 pF
Capacitor, Ceramic, 25 V, X7R , 10%
0603
Std
Std
C6
1
1.0 μF
Capacitor, Ceramic, 16 V, X7R, 10%
0603
Std
Std
C4, C7
1
0.1 μF
Capacitor, Ceramic, 50 V, X7R, 10%
0603
Std
Std
C9, C10
2
22 μF
Capacitor, Ceramic, 6.3 V, X5R, 20%
1206
C3216X5R0J226M
TDK
J1, J2
2
ED555/2DS
Terminal Block, 2-pin, 6-A, 3.5 mm
0.27 × 0.25 inch
ED555/2DS
Sullins
JP1
1
PEC03SAAN
Header, Male 3-pin, 100-mil spacing
0.100 inch × 3
PEC03SAAN
Sullins
L1
1
1.5 μH
Inductor, SMT, 11 A, 9.7 mΩ
0.256 × 0.280 inch
SPM6530T-1R5M100
TDK
R1
1
8.25 k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R2
1
22.1 k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R3
1
0
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R4
1
100 k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
R5
0
Open
Resistor, Chip, 1/16W, 1%
0603
Std
Std
TP1, TP3,
TP4, TP6,
TP7, TP8, TP9
3
5000
Test Point, Red, Thru Hole Color Keyed
0.100 × 0.100 inch
5000
Keystone
TP2, TP5, TP9
3
5001
Test Point, Black, Thru Hole Color Keyed
0.100 × 0.100 inch
5001
Keystone
U1
1
TPS54429PWP
IC, 4.5-A Output Single Sync. Step-Down
TPS54429PWP
TI
929950-00
3M
HPA608
Any
–
1
Shunt, 100-mil, Black
–
1
PCB, 2.76 In x 1.97 In × 0.062 In
0.100
6.3 Reference
Texas Instruments, TPS54429, 7V to 18V Input, 4.5-A Synchronous Step-Down SWIFT™ Converter Data Sheet
7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2011) to Revision A (September 2011)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................3
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Revision History
•
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Updated the user's guide title ............................................................................................................................ 3
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