TPS54526
SLVSB84D – MAY 2012 – REVISEDTPS54526
APRIL 2021
SLVSB84D – MAY 2012 – REVISED APRIL 2021
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TPS54526 4.5-V to 18-V Input, 5.5-A Synchronous Step-Down Converter with Ecomode™
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
3 Description
D-CAP2™
mode enables fast transient response
Low output ripple and allows ceramic output
capacitor
Wide VIN input voltage range: 4.5 V to 18 V
Output voltage range: 0.76 V to 5.5 V
Highly efficient integrated FETs optimized
for lower duty cycle applications
– 63 mΩ (high side) and 33 mΩ (low side)
High efficiency, less than 10 μA at shutdown
High initial bandgap reference accuracy
Adjustable soft start
Pre-biased soft start
650-kHz switching frequency (fSW)
Cycle-by-cycle over current limit
Power good output
Auto-skip Eco-mode™ for high efficiency at light
load
2 Applications
•
Wide range of applications for low voltage system
– Digital TV power supply
– High definition Blu-ray Disc™ players
– Networking home terminal
– Digital set top box (STB)
The TPS54526 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54526
enables system designers to complete the suite
of various end equipment’s power bus regulators
with a cost effective, low component count, low
standby current solution. The main control loop for
the TPS54526 uses the D-CAP2™ mode control
which provides a very fast transient response with
no external compensation components. The adaptive
on-time control supports seamless transition between
PWM mode at higher load conditions and Ecomode™ operation at light loads. Eco-mode™ allows
the TPS54526 to maintain high efficiency during
lighter load conditions. The TPS54526 also has a
proprietary circuit that enables the device to adopt
to both low equivalent series resistance (ESR) output
capacitors, such as POSCAP, SP-CAP, and ultra-low
ESR ceramic capacitors. The device operates from
4.5-V to 18-V VIN input. The output voltage can be
programmed between 0.76V and 5.5V. The device
also features an adjustable soft start time and a power
good function. The TPS54526 is available in the 14pin HTSSOP package and the 16 pin QFN package,
designed to operate from –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS54526
(1)
PACKAGE
BODY SIZE (NOM)
HTSSOP (14)
5.00mm x 4.40mm
VQFN (16)
4.00mm x 4.00mm
For all available packages, see the orderable addendum at
the end of the datasheet.
U1
TPS54526PWP
VO (50 mV/div ac coupled)
IOUT (2A/div)
Slew Rate (0.35A/µsec)
Time Scale (100µsec/div)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Handling Ratings.........................................................4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Typical Characteristics................................................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................11
8 Application and Implementation.................................. 12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................21
11.1 Receiving Notification of Documentation Updates.. 21
11.2 Support Resources................................................. 21
11.3 Trademarks............................................................. 21
11.4 Electrostatic Discharge Caution.............................. 21
11.5 Glossary.................................................................. 21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
12.1 Thermal Information................................................22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2014) to Revision D (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Updated Equation 3 ......................................................................................................................................... 13
Changes from Revision B (January 2014) to Revision C (June 2014)
Page
• Changed the data sheet to the new TI standard format .................................................................................... 1
• Added the Handling Ratings table...................................................................................................................... 4
• Added the Timing Requirements table................................................................................................................6
• Added the Power Supply Recommendations section.......................................................................................17
Changes from Revision A (July 2013) to Revision B (January 2014)
Page
• Change the data sheet Title From: 4.5-V to 18-V Input, 5.5-A Synchronous Step-Down Converter with Ecomode™ To: 4.5-V to 18-V Input, 3-A Synchronous Step-Down Converter with Eco-mode™.............................1
Changes from Revision * (May 2012) to Revision A (May 2013)
Page
• Changed the Over/Under Voltage Protection section. From: "as the high-side MOSFET driver turns off and
the low-side MOSFET turns on" To: "as both the high-side and low-side MOSFET drivers turn off"............... 10
2
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VFB
2
13
VREG5
3
12
VIN1
VIN2
VIN2
14
1
VIN3
VO
VO
5 Pin Configuration and Functions
16
15
14
13
VIN1
VFB
1
VREG5
2
12
VBST
11
SW3
VBST
POWER PAD
SW2
5
10
SW1
PG
6
9
PGND2
EN
7
8
PGND1
3
10
SW2
GND
4
9
SW1
5
6
7
8
PGND2
GND
SS
PGND1
11
EN
POWER PAD
4
PG
SS
Figure 5-2. RSA PACKAGE (TOP VIEW)
Figure 5-1. PWP PACKAGE (TOP VIEW)
Table 5-1. Pin Functions
PIN
NAME
NUMBER(1)
PWP 14
RSA 16
DESCRIPTION
VO
1
16
Connect to output of converter. This pin is used for output discharge function.
VFB
2
1
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
2
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not
active when EN is low.
SS
4
3
Soft-start control. An external capacitor should be connected to GND.
GND
5
4
Signal ground pin.
PG
6
5
Open drain power good output.
EN
7
6
Enable control input. EN is active high and must be pulled up to enable the device.
8, 9
7, 8
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect
PGND and GND strongly together near the IC.
10, 11
9, 10, 11
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to
current comparators.
12
12
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
VIN1, VIN2,
VIN3(1)
13, 14
13, 14, 15
Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator
for the control circuitry.
PowerPAD™
Back side
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be
connected to PGND.
PGND1,
PGND2
SW1, SW2,
SW3(1)
VBST
(1)
SW3, VIN3 applies to 16 pin package only.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN1, VIN2, EN
–0.3
20
V
VBST
–0.3
26
V
VBST (10 ns transient)
–0.3
28
V
VBST (vs Sw1, SW2)
–0.3
6.5
V
VFB, VO, SS, PG
–0.3
6.5
V
SW1, SW2
–2
20
V
SW1, SW2 (10 ns transient)
–3
22
V
VREG5
–0.3
6.5
V
PGND1, PGND2
–0.3
0.3
V
Voltage from GND to PowerPAD™, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Input voltage range
Output voltage range
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
MIN
MAX
UNIT
–55
150
°C
–2
2
kV
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
VI
Supply input voltage range
Input voltage range
4.5
18
VBST
–0.3
24
VBST (10 ns transient)
–0.3
27
VBST (vs Sw1, SW2)
–0.3
5.7
SS, PG
–0.3
5.7
EN
–0.3
18
VO, VFB
–0.3
5.5
SW1, SW2
–1.8
18
–3
21
SW1, SW2 (10 ns transient)
4
MAX
UNIT
V
V
PGND1, PGND2
–0.3
0.1
VO
Output voltage range
VREG5
–0.3
5.7
IO
Output Current range
IVREG5
0
5
mA
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
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V
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6.4 Thermal Information
TPS54526
THERMAL METRIC(1)
PWP (14) PINS
RSA (16) PINS
Junction-to-ambient thermal resistance
43.7
35.2
RθJCtop
Junction-to-case (top) thermal resistance
33.1
40.6
RθJB
Junction-to-board thermal resistance
28.4
12.3
ψJT
Junction-to-top characterization parameter
1.3
0.8
ψJB
Junction-to-board characterization parameter
28.2
12.4
RθJCbot
Junction-to-case (bottom) thermal resistance
4.7
3.6
RθJA
UNITS
°C/W
6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VVFB = 0.8 V
900
1400
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3.6
10
μA
LOGIC THRESHOLD
VENH
EN high-level input voltage
VENL
EN low-level input voltage
REN
EN pin resistance to GND
1.6
VEN = 12 V
220
V
440
0.6
V
880
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB voltage light load mode, TA = 25°C,
VO = 1.05 V, IO = 10mA
VFBTH
VFB threshold voltage
771
TA = 25°C, VO = 1.05 V, continuous mode
757
TA = 0°C to 85°C, VO = 1.05 V, continuous
mode(1)
753
777
TA = –40°C to 85°C, VO = 1.05 V, continuous
mode(1)
751
779
IVFB
VFB input current
VVFB = 0.8 V, TA = 25°C
RDischg
VO discharge resistance
VEN = 0 V, VO = 0.5 V, TA = 25°C
765
773
mV
0
±0.15
μA
50
100
Ω
5.5
5.7
V
20
mV
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VVREG5
VREG5 Line regulation
6.0 V < VIN < 18 V, IVREG5 = 5 mA
VVREG5
VREG5 Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
VREG5 Output current
VIN = 6 V, VVREG5 = 4 V, TA = 25°C
60
mA
Rdsonh
High side switch resistance
TA = 25°C, VBST - VSW1,2 = 5.5 V
63
mΩ
Rdsonl
Low side switch resistance
TA = 25°C
33
mΩ
5.2
100
mV
MOSFET
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over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.1
6.9
8.4
UNIT
CURRENT LIMIT
Iocl
Current limit
LOUT = 1.5 μH(1),
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature (1)
165
Hysteresis (1)
°C
35
SOFT START
ISSC
SS charge current
VSS = 1.0 V
4.2
6.0
ISSD
SS discharge current
VSS = 0.5 V
0.1
0.2
VVFB rising (good)
85
90
7.8
μA
mA
POWER GOOD
VTHPG
PG threshold
IPG
PG sink current
VVFB falling (fault)
95
%
85
%
2.5
5
mA
OVP detect
120
125
130
UVP detect
60
65
70
VPG = 0.5 V
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
VUVP
Output UVP trip threshold
Hysteresis
10
%
%
%
UVLO
Wake up VREG5 voltage
VUVLO
(1)
UVLO threshold
3.31
3.61
3.91
Fall VREG5 voltage
2.82
3.12
3.42
Hysteresis VREG5 voltage
0.37
0.49
0.61
MIN
TYP
MAX
V
Not production tested.
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
UNIT
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
155
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
260
ns
330
ns
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
6
tOVPDEL
Output OVP prop delay
tUVPDEL
Output UVP delay
tUVPEN
Output UVP enable delay
Relative to soft-start time
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10
μs
0.25
ms
x 1.7
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6.7 Typical Characteristics
1200
12
1000
10
Supply Current−Shutdown Current (µA)
Supply Current (µA)
VIN = 12 V, TA = 25 °C (unless otherwise noted)
800
600
400
200
8
6
4
2
VIN = 12 V
0
−50
0
50
100
Junction Temperature (°C)
VIN = 12 V
0
−50
150
0
50
100
Junction Temperature (°C)
150
G006
Figure 6-1. VIN Current vs Junction Temperature
G005
Figure 6-2. VIN Shutdown Current vs Junction Temperature
800
50
45
40
Switching Frequency (kHz)
700
EN Input Current (µA)
35
30
25
20
15
600
500
10
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
5
VIN = 12 V
0
0
5
10
EN Input Voltage (V)
15
400
0
5
20
10
Input Voltage (V)
15
20
G004
G002
IO = 1A
Figure 6-4. Switching Frequency vs Input Voltage
Figure 6-3. EN Current vs EN Voltage
900
6
800
5
600
Output Current (A)
Switching Frequency (kHz)
700
500
400
300
4
3
2
200
0
0.01
1
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
100
0.1
1
Output Current (A)
VIN = 12 V
0
−50
10
G007
Figure 6-5. Switching Frequency vs Output Current
−25
VOUT = 1.0 − 4.5 V
VOUT = 5.0 V
VOUT = 5.5 V
0
25
50
Ambient Temperature (°C)
75
100
G008
Figure 6-6. Output Current vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The TPS54526 is a 5.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs
and auto-skip Eco-mode™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
7.2 Functional Block Diagram
-35%
UV
14
OV
13
1
VO
VIN
VIN2
VIN1
+25%
VREG5
12
Control logic
VBST
Ref
SS
1 shot
11
2
VFB
SGND
XCON
10
SW2
VREG5
VREG5
Ceramic
Capacitor
3
SS
1mF
VO
SW1
9
PGND2
4
SW
Softstart
5
PGND1
ZC
SS
PGND
8
PGND
GND
SW
OCP
SGND
PG
Ref
PGND
VIN
6
-10%
UV
VREG5
EN
7
A.
8
EN
Logic
OV
UVLO
UVLO
Protection
Logic
TSD
REF
Ref
The block diagram shown is for the PWP 14 pin package. The QFN 16 pin package block diagram is identical except for the pin out.
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7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS54526 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal
one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,
to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below
the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2™ mode control.
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS54526 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54526 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
6 μA.
t
SS
(ms) =
CSS (nF) x VREF ´1.1
I (mA)
SS
=
CSS (nF) x 0.765 ´1.1
6
(1)
The TPS54526 contains a unique circuit to prevent current from being pulled from the output during startup if
the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft
start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
7.3.4 Power Good
The TPS54526 has power-good open drain output. The power good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage
is within -10% of the target value, internal comparators detect power good state and the power good signal
becomes high. Rpg resister value ,which is connected between PG and VREG5, is required from 25kΩ to
150kΩ. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a 5
μs internal delay.
7.3.5 VREG5
VREG5 is an internally generated voltage source used by the TPS54526. It is derived directly from the input
voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5
regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage
(3.6 V typical) for the TPS54526 to function. Connect a 1 µF capacitor between pin 3 of the TPS54526 and
power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external
use. It is recommended to use no more than 5 mA for external loads. The VREG5 output is disabled when the
TPS54526 EN pin is open or pulled low.
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7.3.6 Output Discharge Control
TPS54526 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected
from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to
avoid the possibility of causing negative voltage at the output.
7.3.7 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit.
The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND.
This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the measured voltage is
above the voltage proportional to the current limit. Then, the device constantly monitors the low-side FET switch
voltage, which is proportional to the switch current, during the low-side on-time.
The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to
the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current one half of
the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from
the converter. This may cause the output under-voltage protection circuit to be activated. When the overcurrent
condition is removed, the output voltage will return to the regulated value. This protection is non-latching.
7.3.8 Over/Under Voltage Protection
TPS54526 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high and the circuit
latches as both the high-side and low-side MOSFET drivers turns off. When the feedback voltage becomes
lower than 65% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter
begins. After 250 μs, the device latches off both internal top and bottom MOSFET. This function is enabled
approximately 1.7 x softstart time.
7.3.9 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54526 is shut off. This is protection is non-latching.
7.3.10 Thermal Shutdown
TPS54526 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
10
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7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-Mode™ Control
The TPS54526 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 2.
IOUT(LL) =
(V -V )×VOUT
1
× IN OUT
2×L×fSW
VIN
(2)
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
The TPS54526 is an adaptive on-time D-CAP2™ mode synchronous buck converter. Idea applications are:
Digital TV Power Supply, High Definition Blu-ray Disc™ Player, Networking Home Terminal and Digital Set Top
Box.
U1
TPS54526PWP
Figure 8-1. Schematic Diagram for This Design Example
8.2.1 Design Requirements
For this design example, use the following input parameters.
Table 8-1. Design Parameters
DESIGN PARAMETERS
VALUES
Input voltage range
4.5V – 18 V
Output voltage
1.05 V
Output current rating
0 – 5.5 A
Output voltage ripple
7 mVPP (12 VIN / 5.5 A)
8.2.2 Detailed Design Procedure
8.2.2.1 Step By Step Design Procedure
To begin the design process, the designer must know a the following application parameters:
•
•
•
12
Input voltage range
Output voltage
Output current
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•
•
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Output voltage ripple
Input voltage ripple
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable
§
0.0011 u VOUT _ SET u ¨ 1
©
where VOUT _ SET is t arget VOUT voltage
V OUT
0.7651
R1 ·
R2 ¸¹
(3)
8.2.2.3 Output Filter Selection
The output filter used with the TPS54526 is an LC circuit. This LC filter has double pole at:
FP =
1
2p LOUT ´ COUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54526. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above
the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double
pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be
the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 8-2
Table 8-2. Recommended Component Values
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
(1)
C4 (pF)(1)
L1 (µH)
C8 + C9 (µF)
1
6.81
22.1
1.0 - 1.5
22 - 68
1.05
8.25
22.1
1.0 - 1.5
22 - 68
1.2
12.7
22.1
1.0 - 1.5
22 - 68
1.5
21.5
22.1
1.5
22 - 68
1.8
30.1
22.1
5 - 22
1.5
22 - 68
2.5
49.9
22.1
5 - 22
2.2
22 - 68
3.3
73.2
22.1
5 - 22
2.2
22 - 68
5
124
22.1
5 - 22
3.3
22 - 68
Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1.
Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages above 1.8 V, additional phase boost can be achieved by adding a
feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
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VOUT VIN (max) - VOUT
•
Ilp - p = V
L •f
(5)
Ilp - p
Ilpeak = IO +
2
(6)
IN (max)
ILo(RMS) =
O
SW
−
1
√I
O
2
+ − Ilp - p2
12
(7)
For this design example, the calculated peak current is 6.01 A and the calculated RMS current is 5.5 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating
of 11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54526 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 8 to
determine the required RMS current rating for the output capacitor
VOUT • (VIN - VOUT)
ICO(RMS) =−
−
√12 • VIN • LO • fSW
(8)
For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is .284 A and each output capacitor is rated for 4 A.
8.2.2.4 Input Capacitor Selection
The TPS54526 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 uF. is recommended for the decoupling capacitor. An additional 0.1
µF capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.
8.2.2.5 Bootstrap Capacitor Selection
A 0.1 μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.2.6 VREG5 Capacitor Selection
A 1.0 μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
14
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8.2.3 Application Curve
1.09
1.10
VO = 1.05 V
1.09
1.08
1.07
1.07
Output Voltage (V)
Output Voltage (V)
1.08
1.06
1.05
1.05
1.04
1.03
1.02
1.04
1.03
0.0
1.06
VIN = 5 V
VIN = 12 V
VIN = 18 V
0.5
1.0
1.5
2.0 2.5 3.0 3.5
Output Current (A)
4.0
4.5
5.0
1.01
1.00
5.5
IO = 10 mA
IO = 1 A
0
5
10
Input Voltage (V)
15
G007
G007
Figure 8-3. 1.05V Output Voltage vs Input Voltage
100
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
Figure 8-2. 1.05V Output Voltage vs Output Current
50
40
30
50
40
30
20
20
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
10
0
0.0
20
0.5
1.0
1.5
2.0 2.5 3.0 3.5
Output Current (A)
4.0
4.5
5.0
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
10
5.5
0
0.001
0.01
0.1
Output Current (A)
1
G000
Figure 8-4. Efficiency vs Output Current
10
G001
Figure 8-5. Light Load Efficiency vs Output Current
EN (10 V/div)
VO (50 mV/div ac coupled)
VREG5 (5 V/div)
VO (500 mV/div)
IOUT (2A/div)
PG (5 V/div)
Slew Rate (0.35A/µsec)
Time Scale (100µsec/div)
1.05 V
50 mA to 5.5 A
Figure 8-7. Startup Waveform
Figure 8-6. Load Transient Response
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VO = 1.05 V
VO = 1.05 V
IO = 30 mA
VO (10 mV/div ac coupled)
VO (20 mV/div ac coupled)
SW (5 V/div)
SW (5 V/div)
IO = 30 mA
IO= 5.5A
Figure 8-8. Voltage Ripple at Output
VO = 1.05 V
Figure 8-9. Eco-mode Voltage Ripple at Output
VIN (50 mV/div ac coupled)
SW (5 V/div)
IO= 5.5A
Figure 8-10. Voltage Ripple at Input
16
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 V and 18 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS54526 converter
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
•
•
18
Keep the input switching current loop as small as possible.
Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to
the feedback pin of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
VREG5 capacitor should be placed near the device, and connected PGND.
Output capacitor should be connected to a broad pattern of the PGND.
Voltage feedback loop should be as short as possible, and preferably with ground shield.
Lower resistor of the voltage divider which is connected to the VFB pin should be tied to AGND.
Providing sufficient via is preferable for VIN, SW and PGND connection.
PCB pattern for VIN and SW should be as broad as possible.
VIN Capacitor should be placed as near as possible to the device.
The top side power ground (PGND) copper fill area near the IC should be as large as possible. This will aid in
thermal dissipation as well lower conduction losses in the ground return
Exposed pad of device must be connected to PGND with solder. The PGND area under the IC should be
as large as possible and completely cover the exposed thermal pad. The bottom side of the board should
contain a large copper area under the device that is directly connected to the exposed area with small
diameter vias. Small diameter vias will prevent solder from being drawn away from the exposed thermal pad.
Any additional internal layers should also contain copper ground areas under the device and be connected to
the thermal vias.
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10.2 Layout Example
VIN
Additional
Thermal
Vias
FEEDBACK
RESISTORS
VOUT
BIAS
CAP
Connection to
POWER GROUND
on internal or
bottom layer
SLOW
START
CAP
ANALOG
GROUND
TRACE
VIN
INPUT
BYPASS
CAPACITOR
VIN OVER
CURRENT
STABILITY
CAPACITOR
EXPOSED
POWERPAD
AREA
VIN2
VFB
VIN1
VREG5
VBST
SS
SW1
GND
SW2
PG
PGND1
EN
PGND2
BOOST
CAPACITOR
OUTPUT
INDUCTOR
VOUT
OUTPUT
FILTER
CAPACITOR
Additional
Thermal
Vias
To Enable
Control
POWER GROUND
VIA to Ground Plane
Etch on Bottom Layer
or Under Component
Figure 10-1. PCB Layout for PWP Package
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VIN
VIA to Ground Plane
VIN1
15
14
13
EXPOSED THERMAL
PAD AREA
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
POWER
GROUND
VBST
VFB
1
VREG5
2
11 SW3
SS
3
10
SW2
GND
4
9
SW1
5
6
7
8
PGND1
PGND2
12
EN
SLOW
START
CAP
ANALOG
GROUND
TRACE
Connection to
POWER GROUND
on internal or
bottom layer
16
PG
BIAS
CAP
VIN2
FEEDBACK
RESISTORS
VIN3
Etch on Bottom Layer
or Under Component
VO
VIN
INPUT
BYPASS
CAPACITOR
BOOST
CAPACITOR
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
To Enable
Control
VOUT
Figure 10-2. PCB Layout for RSA Package
20
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
D-CAP2™, Eco-mode™, TI E2E™ are trademarks of Texas Instruments.
Blu-ray Disc™ is a trademark of Blu-ray Disc Association.
is a trademark of TI.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Thermal Information
This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can
be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to
the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to
a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
14
Thermal Pad
2.46
°
7
1
2.31
Figure 12-1. Thermal Pad Dimensions
22
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PACKAGE OPTION ADDENDUM
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29-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54526PWP
ACTIVE
HTSSOP
PWP
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54526
TPS54526PWPR
ACTIVE
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54526
TPS54526RSAR
ACTIVE
QFN
RSA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54526
TPS54526RSAT
ACTIVE
QFN
RSA
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54526
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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