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TPS54527
SLVSAY5D – JULY 2011 – REVISED AUGUST 2016
TPS54527 4.5-V to 18-V Input, 5-A Synchronous Step-Down Converter
1 Features
3 Description
•
The TPS54527 is an adaptive on-time D-CAP2 mode
synchronous buck converter. The TPS54527 enables
system designers to complete the suite of various
end equipment’s power bus regulators with a cost
effective, low component count, low standby current
solution. The main control loop for the TPS54527
uses the D-CAP2 mode control which provides a fast
transient response with no external compensation
components. The TPS54527 also has a proprietary
circuit that enables the device to adopt to both low
equivalent series resistance (ESR) output capacitors,
such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors. The device operates from a 4.5-V
to 18-V input. The output voltage can be programmed
from 0.76 V to 6 V. The device also features an
adjustable soft-start time. The TPS54527 is available
in the 8-pin DDA package, and designed to operate
from –40°C to 85°C.
1
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 6 V
Highly Efficient Integrated FETs Optimized for
Lower Duty Cycle Applications: 65 mΩ (High Side)
and 36 mΩ (Low Side)
High Efficiency: Less Than 10 µA at Shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Prebiased Soft Start
650-kHz Switching Frequency
Cycle-by-Cycle Overcurrent Limit
Device Information(1)
2 Applications
•
PART NUMBER
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
Simplified Schematic
TPS54527
TPS54527
PACKAGE
SO PowerPAD (8)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Load Transient Response
Vout (50 mV/div)
Iout (2 A/div)
Copyright © 2016, Texas Instruments Incorporated
t - Time - 100 ms/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54527
SLVSAY5D – JULY 2011 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
10.3 Thermal Consideration.......................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2012) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
Changes from Revision B (January 2012) to Revision C
•
Changed tOFF(MIN) From: 310 ns To: 330 ns............................................................................................................................ 5
Changes from Revision A (November 2011) to Revision B
•
2
Page
Changed equation 1 denominator from 2 to 6........................................................................................................................ 8
Changes from Original (July 2011) to Revision A
•
Page
Page
Changed pinout drawing to correct pins 5, 6, 7, 8 location .................................................................................................... 3
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5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
EN
1
VFB
2
8
VIN
7
VBST
Thermal Pad
VREG5
3
6
SW
SS
4
5
GND
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
I
Enable input control. EN is active high and must be pulled up to enable the device.
VFB
2
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
O
5.5-V power supply output. A capacitor (typically 1 µF) must be connected to GND. VREG5 is not active
when EN is low.
SS
4
I
Soft-start control. An external capacitor must be connected to GND.
GND
5
—
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a
single point.
SW
6
O
Switch node connection between high-side NFET and low-side NFET.
VBST
7
O
Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST and SW pins.
An internal diode is connected between VREG5 and VBST.
8
I
Input voltage supply pin.
Back
side
—
VIN
Thermal
Pad
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
VIN, EN
–0.3
20
VBST
–0.3
26
VBST (10-ns transient)
–0.3
28
VBST (vs SW)
–0.3
6.5
VFB, SS
–0.3
6.5
SW
–2
20
SW (10-ns transient)
–3
22
VREG5
–0.3
6.5
GND
–0.3
0.3
UNIT
V
V
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Supply input voltage
Input voltage
MIN
MAX
4.5
18
VBST
–0.1
24
VBST (10 ns transient)
–0.1
27
VBST(vs SW)
–0.1
5.7
SS
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
SW (10 ns transient)
UNIT
V
V
–3
21
GND
–0.1
0.1
–0.1
5.7
0
5
mA
VOUT
Output voltage
VREG5
IOUT
Output current
IVREG5
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
6.4 Thermal Information
TPS54527
THERMAL METRIC
(1)
DDA (SO PowerPAD)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
43.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.4
°C/W
RθJB
Junction-to-board thermal resistance
25.6
°C/W
ψJT
Junction-to-top characterization parameter
7.4
°C/W
ψJB
Junction-to-board characterization parameter
25.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating non-switching supply current
VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V
900
1400
µA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3.6
10
µA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
1.6
V
0.6
V
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VOUT = 1.05 V, continuous mode
757
765
773
mV
VFBTH
VFB threshold voltage
TA = –40°C to 85°C , VOUT = 1.05 V, continuous
mode (1)
751
765
779
mV
IVFB
VFB input current
VFB = 0.8 V, TA = 25°C
0
±0.15
µA
5.5
5.7
V
25
mV
100
mV
VREG5 OUTPUT
VREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN < 18 V, 0 < IVREG5 < 5 mA
VLN5
Line regulation
6 V < VIN < 18 V, IVREG5 = 5 mA
5.2
VLD5
Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
Output current
VIN = 6 V, VREG5 = 4 V, TA = 25°C
60
mA
RDS(ON)H
High side switch resistance
TA = 25°C, VBST – SW = 5.5 V
65
mΩ
RDS(ON)L
Low side switch resistance
TA = 25°C
36
mΩ
MOSFET
CURRENT LIMIT
Iocl
L out = 1.5 µH (1)
Current limit
5.6
6.4
7.9
A
THERMAL SHUTDOWN
TSDN
Shutdown temperature
Thermal shutdown threshold
Hysteresis
(1)
165
(1)
°C
35
SOFT START
ISSC
SS charge current
VSS = 1 V
4.2
6
ISSD
SS discharge current
VSS = 0.5 V
0.1
0.2
7.8
Wake up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.19
0.32
0.45
µA
mA
UVLO
UVLO
(1)
UVLO threshold
V
Not production tested.
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
ON-TIME TIMER CONTROL
tON
ON time
VIN = 12 V, VOUT = 1.05 V
150
tOFF(MIN)
Minimum OFF time
TA = 25°C, VFB = 0.7 V
260
ns
330
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5
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6.7 Typical Characteristics
VIN = 12 V, TA = 25°C (unles otherwise noted)
7
1200
6
VIN = 12 V
Ivccsdn - Shutdown Current - mA
ICC - Supply Current - mA
1000
800
600
400
5
VIN = 12 V
4
3
2
1
200
0
-50
0
50
100
TJ - Junction Temperature - °C
0
-50
150
0
50
100
TJ - Junction Temperature - °C
150
Figure 2. VIN Shutdown Current vs Junction Temperature
Figure 1. VIN Current vs Junction Temperature
50
0.78
VIN = 18 V
45
0.775
VFBTH - Vfb Voltage - V
EN - Input Current - mA
40
35
30
25
20
15
10
0.77
0.765
0.76
0.755
5
0.75
-50
0
0
5
10
EN - Input Voltage - V
15
1.07
150
1.07
VIN = 18 V
VIN = 12 V
VIN = 5 V
IO = 0 A
1.06
1.06
VO - Output Voltage - V
VO - Output Voltage - V
50
100
TJ - Junction Temperature - °C
Figure 4. VFB Voltage vs Junction Temperature
Figure 3. EN Current vs EN Voltage
1.05
1.04
IO = 1 A
1.05
1.04
1.03
1.03
0
1
2
3
IO - Output Current - A
4
Figure 5. 1.05-V Output Voltage vs Output Current
6
0
20
5
0
5
10
VI - Input Voltage - V
15
20
Figure 6. 1.05-V Output Voltage vs Input Voltage
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C (unles otherwise noted)
100
900
IO = 1 A
VO = 3.3 V
850
fsw - Switching Frequency - kHz
90
Efficiency - %
80
VO = 2.5 V
VO = 1.8 V
70
60
50
VO = 5 V
800
VO = 3.3 V
VO = 2.5 V
750
700
650
VO = 1.05 V
VO = 1.2 V
600
VO = 1.5 V
550
VO = 1.8 V
500
450
400
40
0
1
2
3
IO - Output Current - A
4
0
5
Figure 7. Efficiency vs Output Current
5
10
VI - Input Voltage - V
15
20
Figure 8. Switching Frequency vs Input Voltage
900
fsw - Switching Frequency - kHz
850
VO = 3.3 V
800
VO = 1.8 V
VO = 1.05 V
750
700
650
600
550
500
450
400
0
1
2
3
IO - Output Current - A
4
5
Figure 9. Switching Frequency vs Output Current
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7 Detailed Description
7.1 Overview
The TPS54527 is a 5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
EN
EN
1
VIN
Logic
VIN
8
VREG5
Control Logic
Ref
+
SS
+ PWM
7
1 shot
VFB
SW
VO
6
-
2
VBST
XCON
ON
VREG5
VREG5
Ceramic
Capacitor
3
SGND
SS
SS
4
5
Softstart
GND
PGND
SGND
+
OCP
-
SW
PGND
VIN
UVLO
VREG5
UVLO
REF
TSD
Protection
Logic
Ref
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7.3 Feature Description
7.3.1 Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
6-µA.
C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
t SS (ms) =
=
ISS (μA)
6
(1)
8
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Feature Description (continued)
The TPS54527 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by 1 – D, where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the output voltage (VOUT) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
7.3.2 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current (IOUT). The TPS54527 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage returns to the regulated value. This
protection is non-latching.
7.3.3 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54527 is shut off. This protection is non-latching.
7.3.4 Thermal Shutdown
TPS54527 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
7.4 Device Functional Modes
7.4.1 PWM Operation
The main control loop of the TPS54527 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
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Device Functional Modes (continued)
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage (VIN) and the output voltage (VOUT) to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2 mode control.
7.4.2 PWM Frequency and Adaptive On-Time Control
TPS54527 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54527 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT / VIN, the frequency is constant.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54327 is designed to provide up to a 2-A output current from an input voltage source ranging from 4.5 V
to 18 V. The output voltage is configuarable from 0.7 V to 6 V.
8.2 Typical Application
U1
TPS54527
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Figure 10. Shows the schematic diagram for this design example.
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage
4.5 V to 18 V
Output voltage
1.05 V
Output current
5A
Output voltage ripple
20 mV
Input voltage ripple
100 mV
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using a 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance is more
susceptible to noise and voltage errors from the VFB input current is more noticeable.
æ
ö
R1÷
V
= 0.765 x çç1 +
÷
OUT
çè
R2 ÷ø
(2)
8.2.2.2 Output Filter Selection
The output filter used with the TPS54527 is an LC circuit. This LC filter has a double pole at:
F =
P
2p L
1
x COUT
OUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54527. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. TI recommends the values in Table 2 to
meet this requirement.
Table 2. Recommended Component Values
(1)
OUTPUT VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
C4 (pF) (1)
L1 (µH)
C8 + C9 (µF)
1
6.81
22.1
—
1 to 1.5
22 to 68
1.05
8.25
22.1
—
1 to 1.5
22 to 68
1.2
12.7
22.1
—
1 to 1.5
22 to 68
1.5
21.5
22.1
—
1.5
22 to 68
1.8
30.1
22.1
5 to 22
1.5
22 to 68
2.5
49.9
22.1
5 to 22
2.2
22 to 68
3.3
73.2
22.1
5 to 22
2.2
22 to 68
5
124
22.1
5 to 22
3.3
22 to 68
Optional
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 650 kHz for fSW. Chose an inductor that is rated for the peak current of Equation 5 and the RMS current of
Equation 6.
- VOUT
V
V
OUT x IN(max)
I
=
IPP
V
L x f
IN(max)
O
SW
I
=I +
Ipeak
O
=
I
Lo(RMS)
12
(4)
I
lpp
2
I
2
O
(5)
+
1
2
I
12 IPP
(6)
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For this design example, the calculated peak current is 5.51 A and the calculated RMS current is 5.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of
11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54527 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.29 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS54527 requires an input decoupling capacitor and a bulk capacitor is required depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from VIN to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating must to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST and SW pins for proper operation. TI
recommends using a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF. ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. TI
recommends using a ceramic capacitor.
8.2.3 Application Curves
EN (10 V/div)
Vout (50 mV/div)
VREG5 (5 V/div)
Iout (2 A/div)
Vout (0.5 V/div)
t - Time - 1 ms/div
t - Time - 100 ms/div
Figure 11. 1.05-V, 50-mA to 2-A Load Transient Response
Figure 12. Start-Up Wave Form
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Vo = 1.05 V
VIN (50 mV/div)
Vo (10 mV/div)
Vo = 1.05 V
SW (5 V/div)
SW (5 V/div)
t - Time - 400 ns/div
t - Time - 400 ns/div
IOUT = 2 A
IOUT = 2 A
Figure 13. Voltage Ripple at Output
Figure 14. Voltage Ripple at Input
9 Power Supply Recommendations
The input voltage range is from 4.5 V to 18 V. The input power supply and the input capacitors must be placed
as close to the device as possible to minimize the impedance of the power-supply line.
10 Layout
10.1 Layout Guidelines
1. The TPS54527 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top side
area adjacent to the TPS54527 must be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC must a dedicated ground area. It must be directly connected to
the thermal pad of the device using vias as shown. The ground area must be as large as practical. Additional
internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor must be placed near the device, and connected PGND.
11. Output capacitor must be connected to a broad pattern of the PGND.
12. Voltage feedback loop must be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
14. Providing sufficient via is required for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND must be as broad as possible.
16. VIN capacitor must be placed as near as possible to the device.
14
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10.2 Layout Example
VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
BIAS
CAP
EN
VIN
VFB
VBST
VREG5
SW
SS
GND
SLOW
START
CAP
Connection to
POWER GROUND
on internal or
bottom layer
ANALOG
GROUND
TRACE
BOOST
CAPACITOR
OUTPUT
INDUCTOR
EXPOSED
THERMAL PAD
AREA
VOUT
OUTPUT
FILTER
CAPACITOR
POWER GROUND
VIA to Ground Plane
Figure 15. PCB Layout
10.3 Thermal Consideration
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heat
sink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used
as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heat sink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD Thermally Enhanced Package and PowerPAD Made Easy.
The exposed thermal pad dimensions for this package are shown in Figure 16.
Figure 16. Thermal Pad Dimensions (Top View)
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package (SLMA002)
• PowerPAD Made Easy (SLMA004)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54527DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54527
TPS54527DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54527
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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