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TPS54528
SLVSAY4C – JULY 2011 – REVISED MARCH 2014
TPS54528 4.5-V To 18-V Input, 5-A Synchronous Step-Down Converter With Eco-Mode™
1 Features
3 Description
•
The TPS54528 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54528
enables system designers to complete the suite of
various end-equipment power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54528 uses the D-CAP2™ mode control that
provides a fast transient response with no external
compensation components. The adaptive on-time
control supports seamless transition between PWM
mode at higher load conditions and Eco-mode™
operation at light loads. Eco-mode™ allows the
TPS54528 to maintain high efficiency during lighter
load conditions. The TPS54528 also has a proprietary
circuit that enables the device to adopt to both low
equivalent series resistance (ESR) output capacitors,
such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors. The device operates from 4.5-V
to 18-V VIN input. The output voltage can be
programmed between 0.76 V and 6 V. The device
also features an adjustable soft start time. The
TPS54528 is available in the 8-terminal DDA
package, and designed to operate from –40°C to
85°C.
1
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 6 V
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 65 mΩ (High Side) and 36 mΩ (Low Side)
High Efficiency, less than 10 μA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
650-kHz Switching Frequency (fSW)
Cycle By Cycle Over Current Limit
Auto-Skip Eco-mode™ for High Efficiency at Light
Load
2 Applications
•
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
Device Information
ORDER NUMBER
TPS54528DDA
PACKAGE
HSOP (8)
BODY SIZE
4,89 mm × 3,9 mm
4 Simplified Schematic
1.05-V, Load Transient Response
TPS54528
Vout (50 mV/div)
Iout (2 A/div)
t - Time - 100 ms/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54528
SLVSAY4C – JULY 2011 – REVISED MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements - On-Time Timer Control........
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
11.3 Thermal Information .............................................. 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2012) to Revision C
Page
•
Formatted data sheet to meet new template requirements ................................................................................................... 1
•
Added Table of Contents, and moved Revision History to page 2. ...................................................................................... 3
•
Moved ABS Max, Handling Ratings, ROC, Thermal Info, and Electrical Characteristics tables to the new
"Specifications" section. ......................................................................................................................................................... 4
•
Added Maximum Power Dissipation graph............................................................................................................................. 8
•
Added "Power Supply Recommendations" section ............................................................................................................. 15
•
Added "Device and Documentation Support" section ......................................................................................................... 18
Changes from Revision A (January 2012) to Revision B
•
Page
Changed tOFF(MIN) From: 310 ns To: 330 ns............................................................................................................................ 6
Changes from Original (July 2011) to Revision A
Page
•
Added CONDITIONS statement at the Typical Characteristics section heading ................................................................... 6
•
Changed 2-µA to 6µA in Soft Start and Pre-Biased Soft Start subsection and denominator in equation 2....................... 9
2
Copyright © 2011–2014, Texas Instruments Incorporated
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6 Terminal Configuration and Functions
DDA-8 PACKAGE
(TOP VIEW)
1
EN
2
VFB
3
VREG5
4
SS
TPS54528
VIN
8
VBST
7
SW
6
GND
5
Exposed
Thermal Pad
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
EN
1
Enable input control. EN is active high and must be pulled up to enable the device.
VFB
2
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
when EN is low.
SS
4
Soft-start control. An external capacitor should be connected to GND.
GND
5
Ground terminal. Power ground return for switching circuit. Connect sensitive SS and VFB returns to
GND at a single point.
SW
6
Switch node connection between high-side NFET and low-side NFET.
VBST
7
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW
terminals. An internal diode is connected between VREG5 and VBST.
VIN
8
Input voltage supply terminal.
Exposed Thermal
Pad
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
3
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Input voltage range
MIN
MAX
VIN, EN
–0.3
20
VBST
–0.3
26
VBST (10 ns transient)
–0.3
28
VBST (vs SW)
–0.3
6.5
VFB, SS
–0.3
6.5
–2
20
SW
SW (10 ns transient)
UNIT
V
–3
22
VREG5
–0.3
6.5
GND
–0.3
0.3
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Output voltage range
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
Electrostatic discharge
MIN
MAX
–55
150
°C
2
kV
500
V
Human Body Model (HBM)
Charged Device Model (CDM)
UNIT
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VI
MIN
MAX
4.5
18
VBST
–0.1
24
VBST (10 ns transient)
–0.1
27
VBST(vs SW)
–0.1
5.7
SS
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
Supply input voltage
Input voltage
SW (10 ns transient)
–3
21
GND
–0.1
0.1
–0.1
5.7
UNIT
V
V
VO
Output voltage
VREG5
IO
Output Current
IVREG5
0
5
mA
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
4
V
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7.4 Thermal Information
TPS54528
THERMAL METRIC (1)
θJA
Junction-to-ambient thermal resistance
43.5
θJCtop
Junction-to-case (top) thermal resistance
49.4
θJB
Junction-to-board thermal resistance
25.6
ψJT
Junction-to-top characterization parameter
7.4
ψJB
Junction-to-board characterization parameter
25.5
θJCbot
Junction-to-case (bottom) thermal resistance
5.2
(1)
UNIT
DDA (8)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
900
1200
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3.6
10
μA
LOGIC THRESHOLD
VEN
EN high-level input voltage
EN
EN low-level input voltage
EN
1.6
V
0.6
V
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA, Ecomode™ operation
VFBTH
IVFB
VFB threshold voltage
VFB input current
771
mV
TA = 25°C, VO = 1.05 V, continuous mode
operation
757
765
773
mV
TA = -40 to 85°C, VO = 1.05 V, continuous
mode operation (1)
751
765
779
mV
0
±0.15
μA
5.5
5.7
V
25
mV
100
mV
VFB = 0.8 V, TA = 25°C
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VLN5
Line regulation
6 V < VIN < 18 V, IVREG5 = 5 mA
VLD5
Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
Output current
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
60
mA
High side switch resistance
25°C, VBST - SW = 5.5 V
65
mΩ
Low side switch resistance
25°C
36
mΩ
5.2
MOSFET
RDS(on)
CURRENT LIMIT
Iocl
Current limit
L out = 1.5 μH (1)
5.6
6.4
7.9
A
THERMAL SHUTDOWN
TSDN
(1)
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(1)
(1)
165
35
°C
Not production tested.
5
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.8
UNIT
SOFT START
ISS
SS charge current
VSS = 1 V
4.2
6
SS discharge current
VSS = 0.5 V
0.1
0.2
Wake up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.19
0.32
0.45
μA
mA
UVLO
UVLO
UVLO threshold
V
7.6 Timing Requirements - On-Time Timer Control
MIN
TYP
tON
On time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
260
MAX
UNIT
ns
330
ns
7.7 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted).
1200
7
6
Ivccsdn - Shutdown Current - mA
ICC - Supply Current - mA
1000
800
600
400
200
5
4
3
2
1
0
-50
0
50
100
TJ - Junction Temperature - °C
0
-50
150
0
VI = 12 V
50
100
TJ - Junction Temperature - °C
150
VI = 12 V
Figure 1. VIN Current vs Junction Temperature
Figure 2. VIN Shutdown Current vs
Junction Temperature
50
1.1
45
40
VO - Output Voltage - V
EN - Input Current - mA
1.075
35
30
25
20
15
VIN = 18 V
VIN = 12 V
1.05
VIN = 5 V
1.025
10
5
0
1
0
5
10
EN - Input Voltage - V
15
20
0
1
2
3
IO - Output Current - A
4
5
VI= 18 V
Figure 3. EN Current vs EN Voltage
Figure 4. 1.05-V Output Voltage vs Output Current
6
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted).
1.08
100
VO = 3.3 V
VO = 2.5 V
VO = 1.8 V
90
IO = 10 mA
80
Efficiency - %
VO - Output Voltage - V
1.07
1.06
IO = 1 A
70
60
1.05
50
1.04
40
0
5
10
VI - Input Voltage - V
15
20
0
1
Figure 5. 1.05-V Output Voltage vs Input Voltage
4
5
Figure 6. Efficiency vs Output Current
900
100
850
VO = 3.3 V
90
fsw - Switching Frequency - kHz
VO = 2.5 V
80
VO = 1.8 V
70
Efficiency - %
2
3
IO - Output Current - A
60
50
40
30
20
VO = 3.3 V
800
VO = 5 V
750
VO = 2.5 V
700
650
VO = 1.05 V
600
VO = 1.2 V
VO = 1.5 V
550
VO = 1.8 V
500
450
10
0
0.001
400
0.01
IO - Output Current - A
0
0.1
5
10
VI - Input Voltage - V
15
20
IO= 1 A
Figure 8. Switching Frequency vs Input Voltage
Figure 7. LIght Load Efficiency vs Output Current
800
0.78
700
0.775
600
VFBTH - Vfb Voltage - V
fsw - Switching Frequency - kHz
VO = 3.3 V
VO = 1.8 V
500
VO = 1.05 V
400
300
0.77
0.765
0.76
200
0.755
100
0
0.01
0.1
1
IO - Output Current - A
10
0.75
-50
VI= 12 V
Figure 9. Switching Frequency vs Output Current
0
50
100
TJ - Junction Temperature - °C
150
Figure 10. VFB Voltage vs Junction Temperature
7
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted).
Ambient Temperature
Figure 11. Maximum Power Dissipation
8
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8 Detailed Description
8.1 Overview
The TPS54528 is a 5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
8.2 Functional Block Diagram
EN
1
EN
VIN
Logic
VIN
8
VREG5
Control Logic
Ref
+
SS
+ PWM
7
1 shot
VFB
SW
VO
6
-
2
VBST
XCON
ON
VREG5
VREG5
Ceramic
Capacitor
3
SGND
SS
SS
4
5
Softstart
+
ZC
-
PGND
SGND
SW
GND
PGND
+
OCP
-
SW
PGND
VIN
UVLO
VREG5
UVLO
REF
TSD
Protection
Logic
Ref
8.3 Feature Description
8.3.1 Soft Start And Pre-Biased Soft Start
The soft start function is adjustable. When the EN terminal becomes high, 6μA current begins charging the
capacitor which is connected from the SS terminal to GND. Smooth control of the output voltage is maintained
during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS
terminal source current is 6μA.
C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
t SS (ms) =
=
ISS (μA)
6
(1)
9
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Feature Description (continued)
The TPS54528 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
8.3.2 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW terminal and GND.
This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54528 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent
threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage will return to the regulated value. This
protection is non-latching.
8.3.3 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 terminal. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS54528 is shut off. This protection is non-latching.
8.3.4 Thermal Shutdown
TPS54528 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
8.4 Device Functional Modes
8.4.1 PWM Operation
The main control loop of the TPS54528 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
10
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Device Functional Modes (continued)
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
8.4.2 PWM Frequency And Adaptive On-Time Control
TPS54528 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54528 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
8.4.3 Auto-Skip Eco-Mode™ Control
The TPS54528 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 2
(VIN - VOUT )×VOUT
1
×
I OUT ( LL ) =
2 × L × fsw
VIN
(2)
11
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9 Applications and Implementation
9.1 Application Information
The TPS54528 is designed to provide up to a 2-A output current from an input voltage source ranging from 4.5 V
to 18 V. The output voltage is configurable from 0.76 V to 6 V. A simplified design procedure for a 1.05-V output
is shown below .
9.2 Typical Application
U1
TPS54528DDA
Figure 12. 5-A Synchronous Step-Down (Buck) Converter
9.2.1 Design Requirements
Figure 12 shows the schematic of the design example.
To
•
•
•
•
•
begin the design process, the user must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB terminal. It is recommended to
use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ
ö
R1÷
V
= 0.765 x çç1 +
÷
OUT
çè
R2 ÷ø
(3)
12
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Typical Application (continued)
9.2.2.2 Output Filter Selection
The output filter used with the TPS54528 is an LC circuit. This LC filter has double pole at:
F =
P
2p L
1
x COUT
OUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54528. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.
Table 1. Recommended Component Values
C4 (pF) (1)
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
C8 + C9 (µF)
1
6.81
22.1
1.0 - 1.5
22 - 68
1.05
8.25
22.1
1.0 - 1.5
22 - 68
1.2
12.7
22.1
1.0 - 1.5
22 - 68
1.5
21.5
22.1
1.5
22 - 68
1.8
30.1
22.1
5 - 22
1.5
22 - 68
2.5
49.9
22.1
5 - 22
2.2
22 - 68
3.3
73.2
22.1
5 - 22
2.2
22 - 68
5
124
22.1
5 - 22
3.3
22 - 68
(1)
Optional
Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
- VOUT
V
V
OUT x IN(max)
I
=
IPP
V
L x f
IN(max)
O
SW
I
=I +
Ipeak
O
=
I
Lo(RMS)
(5)
I
lpp
2
I
2
O
(6)
+
1
2
I
12 IPP
(7)
For this design example, the calculated peak current is 5.51 A and the calculated RMS current is 5.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of
11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54528 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(8)
13
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For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.29 A and each output capacitor is rated for 4A.
9.2.2.3 Input Capacitor Selection
The TPS54528 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor (C3) from terminal 8 to ground is optional to provide additional high frequency filtering. The capacitor
voltage rating needs to be greater than the maximum input voltage.
9.2.2.4 Bootstrap Capacitor Selection
A 0.1 µF. ceramic capacitor must be connected between the VBST to SW terminal for proper operation. It is
recommended to use a ceramic capacitor.
9.2.2.5 Vreg5 Capacitor Selection
A 1-µF. ceramic capacitor must be connected between the VREG5 to GND terminal for proper operation. It is
recommended to use a ceramic capacitor.
9.2.3 Application Performance Curves
EN (10 V/div)
Vout (50 mV/div)
VREG5 (5 V/div)
Iout (2 A/div)
Vout (0.5 V/div)
t - Time - 1 ms/div
t - Time - 100 ms/div
VO = 1.05 V
IO = 5 A
Figure 14. Start-Up Wave Form
Figure 13. Load Transient Response
Vo (10 mV/div)
VO = 50 mV / div (-950 mV dc offset)
SW = 10 V / div
SW (5 V/div)
Time = 1 µsec / div
t - Time - 400 ns/div
VO = 1.05 V
IO = 2 A
IO = 30 mA
Figure 15. Voltage Ripple At Output
14
Figure 16. DCM Voltage Ripple At Output
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Product Folder Links: TPS54528
TPS54528
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SLVSAY4C – JULY 2011 – REVISED MARCH 2014
VIN (50 mV/div)
SW (5 V/div)
t - Time - 400 ns/div
VO = 1.05 V
IO = 2 A
Figure 17. Voltage Ripple At Input
10 Power Supply Recommendations
The input voltage range is from 4.5V to 18V. The input power supply and the input capacitors should be located
as close to the device as possible to minimize the impedance of the power-supply line.
11 Layout
11.1 Layout Guidelines
1. The TPS54528 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top side
area adjacent to the TPS54528 should be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad of the device using vias as shown. The ground area should be as large as practical.
Additional internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB terminal should be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
16. VIN Capacitor should be placed as near as possible to the device.
15
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Product Folder Links: TPS54528
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11.2 Layout Example
VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
BIAS
CAP
EN
VIN
VFB
VBST
VREG5
SW
SS
GND
SLOW
START
CAP
Connection to
POWER GROUND
on internal or
bottom layer
ANALOG
GROUND
TRACE
BOOST
CAPACITOR
EXPOSED
THERMAL PAD
AREA
OUTPUT
INDUCTOR
VOUT
OUTPUT
FILTER
CAPACITOR
POWER GROUND
VIA to Ground Plane
16
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Product Folder Links: TPS54528
TPS54528
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SLVSAY4C – JULY 2011 – REVISED MARCH 2014
11.3 Thermal Information
This 8-terminal DDA package incorporates an exposed thermal pad that is designed to be directly connected to
an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the
PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be
attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 18. Thermal Pad Dimensions
17
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Product Folder Links: TPS54528
TPS54528
SLVSAY4C – JULY 2011 – REVISED MARCH 2014
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
D-CAP2TM Frequency Response Model, SLVA546
TPS54528EVM-052, 5-A, SWIFT™ Regulator Evaluation Module, SLVU480
12.2 Trademarks
D-CAP2, Eco-mode are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: TPS54528
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS54528DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54528
Samples
TPS54528DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54528
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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