User's Guide
SLVU864 – June 2013
Evaluation Module for the TPS54540 Step-Down Converter
This user's guide contains information for the TPS54540EVM-558 evaluation module (PWR558) including
the performance specifications, schematic, and the bill of materials.
spacer so the title "List of Tables" will print on page with the list.
1
2
3
4
Contents
Introduction .................................................................................................................. 2
Test Setup and Results .................................................................................................... 5
Board Layout ............................................................................................................... 11
Bill of Materials ............................................................................................................. 14
1
TPS54540EVM-558 Board
List of Figures
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
................................................................................................
TPS54540EVM-558 Schematic ...........................................................................................
Efficiency Versus Load Current ...........................................................................................
Light-Load Efficiency .......................................................................................................
Regulation Versus Output Current ........................................................................................
Regulation Versus Input Voltage..........................................................................................
Load Transient Response .................................................................................................
Loop Response .............................................................................................................
Line Transient Response ..................................................................................................
Input Voltage Ripple CCM .................................................................................................
Input Voltage Ripple DCM .................................................................................................
Output Voltage Ripple CCM ..............................................................................................
Output Voltage Ripple DCM ..............................................................................................
Output Voltage Ripple Eco-mode .........................................................................................
Start Up Relative to VIN ....................................................................................................
Start Up Relative to EN ....................................................................................................
Prebias Start Up Relative to EN ..........................................................................................
Shutdown Relative to VIN .................................................................................................
Shutdown Relative to EN .................................................................................................
Low Dropout Operation ...................................................................................................
Low Dropout Start Up and Shutdown ...................................................................................
TPS54540EVM-558 Top Assembly and Silkscreen ..................................................................
TPS54540EVM-558 Top-Side Layout ..................................................................................
TPS54540EVM-558 Layer 2 Layout ....................................................................................
TPS54540EVM-558 Layer 3 Layout ....................................................................................
TPS54540EVM-558 Bottom-Side Layout ..............................................................................
2
3
5
5
6
6
6
6
7
7
7
8
8
8
9
9
9
10
10
10
10
11
12
12
13
13
List of Tables
1
Input Voltage and Output Current Summary ............................................................................ 2
2
TPS54540EVM-558 Performance Specification Summary ............................................................ 3
Eco-mode is a trademark of Texas Instruments.
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Introduction
1
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3
R5 Values for Common Output Voltages ................................................................................ 4
4
EVM Connectors and Test points ......................................................................................... 5
5
TPS54540EVM-558 Bill of Materials .................................................................................... 14
Introduction
This user's guide contains background information for the TPS54540 as well as support documentation for
the TPS54540EVM-558 evaluation module (PWR558). Also included are the performance specifications,
the schematic, and the bill of materials for the TPS54540EVM-558.
Figure 1. TPS54540EVM-558 Board
1.1
Background
The TPS54540 DC-DC converter is designed to provide up to a 5-A output from an input voltage source of
4.5 V to 42 V. Rated input voltage and output current range for the evaluation module are given in
Table 1. This evaluation module is designed to demonstrate the small, printed-circuit-board (PCB) areas
that may be achieved when designing with the TPS54540 regulator. The switching frequency is externally
set at a nominal 400 kHz. The high-side MOSFET is incorporated inside the TPS54540 package along
with the gate-drive circuitry. The compensation components are external to the integrated circuit (IC), and
an external resistor divider allows for an adjustable output voltage. Additionally, the TPS54540 provides an
adjustable undervoltage lockout with hysteresis through an external resistor divider. The absolute
maximum input voltage is 42 V for the TPS54540EVM-558.
Table 1. Input Voltage and Output Current Summary
2
EVM
Input Voltage Range
Output Current Range
TPS54540EVM-558
VIN = 6 V to 42 V
IOUT = 0 A to 5 A
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1.2
Performance Specification Summary
A summary of the TPS54540EVM-558 (EVM) performance specifications is provided in Table 2.
Specifications are given for an input voltage of VIN = 12 V and an output voltage of 3.3 V, unless otherwise
specified. This EVM is designed and tested for VIN = 6 V to 42 V. The ambient temperature is 25°C for all
measurements, unless otherwise noted.
Table 2. TPS54540EVM-558 Performance Specification Summary
Specification
Test Conditions
MIN
TYP
MAX
6
12
42
VIN voltage range
Output voltage set point
Unit
V
3.3
Output current range
VIN = 6 V to 42 V
Line regulation
IOUT = 5 A, VIN = 6 V to 42 V
Load regulation
VIN = 12 V, IOUT = 0.001 A to 5 A
V
0
IOUT = 1.25 A to 3.75 A
Load transient response
IOUT = 3.75 A to 1.25 A
5
A
±0.2%
±0.3%
Voltage change
–120
Recovery time
250
mV
µs
Voltage change
120
mV
Recovery time
250
µs
Loop bandwidth
VIN = 12 V, IOUT = 5 A
31
kHz
Phase margin
VIN = 12 V, IOUT = 5 A
59
°
Input voltage ripple
IOUT = 5 A
200
mVpp
Output voltage ripple
IOUT = 5 A
10
mVpp
2.6
ms
400
kHz
Output rise time
Operating frequency
Maximum efficiency
TPS54540EVM-558, VIN = 12 V, IOUT = 1.5 A
87.5%
DCM threshold
VIN = 12 V
560
mA
Pulse skipping threshold
VIN = 12 V
18
mA
No load input current
VIN = 12 V
241
µA
UVLO start threshold
5.75
V
UVLO stop threshold
4.5
V
1.3
Schematic
Figure 2 is the schematic for the EVM.
C4
0.1µF
+
DNP
J2
3
C10
4.7µF
C3
4.7µF
C1
4.7µF
C2
4.7µF
R1
365k
4
EN
COMP
RT/CLK
FB
1
7
D1
PDS760-13
6
5
FB
TP6
1
744325550
5.5µH
C6
100µF
C7 DNPC9
100µF
1
VOUT
TP3
2
+
C12
DNP
R7
49.9
TP4
GND
J1
1
GND
TP7
9
2
1
C11
GND
TP5
2
1
TP1
1
GND
VIN
3.3V @ 5A
8
3
2
2
L1
SW
1
VIN
BOOT
PWRPD
1
2
U1
6V to 42V
TPS54540DDA
TP2
GND
2
1
GND
GND
2
1
EN
GND
R2
88.7k
R5
31.6k
GND
R4
16.9k
R3
243k
C5
4700pF
J3
FB
C8
47pF
R6
10.2k
J4
TP8
GND
GND
GND
1
Not Populated
Figure 2. TPS54540EVM-558 Schematic
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Introduction
1.4
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Modifications
These evaluation modules are designed to provide access to the features of the TPS54540. Some
modifications can be made to this module. Component selection for modifications can be done with the aid
of WEBENCH or the excel spreadsheet (SLVC452) located on the product page.
1.4.1
Output Voltage Set Point
To change the output voltage of the EVM, the value of resistor R5 (RHS) should be changed while keeping
R6 (RLS) fixed. The output voltage can be adjusted to a minimum of the 0.8 V internal reference. The value
of R5 for a specific output voltage can be calculated using Equation 1:
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(1)
Table 3 lists the R5 values for some common output voltages assuming R6 = 10.2 kΩ. Note VIN must be in
a range to keep the on time greater than the minimum on-time. The values given in Table 3 are standard
1% values, not the exact value calculated using Equation 1.
Table 3. R5 Values for Common Output Voltages
Output Voltage (V)
R5 Value (kΩ)
1.8
12.7
2.5
21.5
3.3
31.6
5.0
53.6
Be aware, changing the output voltage can affect the loop response. It may be necessary to modify the
compensation components. Please see the TPS54540 data sheet (SLVSBX7) for details.
1.4.2
Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R1 (RUVLO1) and R2 (RUVLO2). The EVM
is set for a start voltage of 5.75 V and stop voltage of 4.5 V, using R1 = 365 kΩ and R2 = 88.7 kΩ. Use
Equation 2 and Equation 3 to calculate the required resistor values for R3 and R4, respectively, for
different start and stop voltages. The typical values of the constants in the two equations are as follows:
IHYS = 3.4 µA, VENA = 1.2 V, and I1 = 1.2 µA.
- VSTOP
V
RUVLO1 = START
IHYS
(2)
RUVLO2 =
4
VENA
VSTART - VENA
+ I1
RUVLO1
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2
Test Setup and Results
This section describes how to properly connect, set up, and use the EVM. The section also includes test
results typical for the EVM covering efficiency, output voltage regulation, load transients, loop response,
output ripple, input ripple, start up, and shutdown.
2.1
I/O Connections
This EVM includes I/O connectors and test points as shown in Table 4. A power supply capable of
supplying at least 5 A must be connected to J2 through a pair of 20-AWG wires. The load must be
connected to J1 through a pair of 20-AWG wires. The maximum load-current capability must be 5 A. Wire
lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the
VIN input voltages with TP2 providing a convenient ground reference. TP3 is used to monitor the output
voltage with TP4 as the ground reference.
Table 4. EVM Connectors and Test points
Reference Designator
2.2
Function
J1
VOUT, 3.3 V at 5-A maximum
J2
VIN (see Table 1 for VIN range)
J3
EN jumper. Connect EN to ground to disable, open to enable.
J4
GND jumper for additional ground connections
TP1
VIN test point at VIN connector
TP2
GND test point at VIN
TP3
Output voltage test point at VOUT connector
TP4
GND test point at VOUT connector
TP5
SW test point
TP6
VOUT test point used for loop response measurements
TP7
Test point between voltage divider network and output. Used for loop response measurements.
TP8
GND test point
Efficiency
The efficiency of this EVM peaks at a load current of about 1.5 A with VIN = 12 V, and then decreases as
the load current increases towards full load. Figure 3 shows the efficiency for the EVM. Figure 4 shows
the light-load efficiency for the EVM using a semi-log scale. Measurements are taken at an ambient
temperature of 25°C. The efficiency may be lower at higher ambient temperatures due to temperature
variation in the drain-to-source resistance of the internal MOSFET.
100
100
95
90
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
65
VOUT = 3.3 V, fsw = 400 kHz
60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Load Current (A)
Figure 3. Efficiency Versus Load Current
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50
40
30
VIN
V
IN ==66VV
V
VIN
12VV
IN ==12
V
VIN
24VV
IN ==24
V
VIN
36VV
IN ==36
70
60
VIN
V
IN ==66VV
V
VIN
12VV
IN ==12
V
VIN
24VV
IN ==24
V
VIN
36VV
IN ==36
20
10
5
VOUT = 3.3 V, fsw = 400 kHz
0
0.001
0.01
0.1
Load Current (A)
C050
1
C051
Figure 4. Light-Load Efficiency
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Output Voltage Regulation
0.5
0.20
0.4
0.15
Output Voltage Normalized (%)
Output Voltage Normalized (%)
The load regulation for the EVM is shown in Figure 5. The line regulation for the EVM is shown in
Figure 6. Measurements are given for an ambient temperature of 25°C.
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
VIN = 12 V, VOUT = 3.3 V, fsw = 400 kHz
-0.4
0.10
0.05
0.00
±0.05
±0.10
±0.15
±0.20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Output Current (A)
0
5
5
10
15
20
25
30
35
40
Input Voltage (V)
C054
Figure 5. Regulation Versus Output Current
2.4
VIN = 12 V, IOUT = 5 A, fsw = 400 kHz
45
C055
Figure 6. Regulation Versus Input Voltage
Load Transients and Loop Response
The EVM response to load transients is shown in Figure 7. The current step is from 25% to 75% of the
maximum rated load at 12-V input. The current step slew rate is 100 mA/µs. Total peak-to-peak voltage
variation is as shown, including ripple and noise on the output.
100 MV/div
60
180
50
150
40
120
30
90
20
60
10
30
0
0
±10
±30
±20
±60
±30
VOUT –3.3V offset
Phase (£)
IOUT
Gain (dB)
1 A/div
The EVM loop-response characteristics are shown in Figure 8. Gain and phase plots are shown for VIN
voltage of 12 V. Load current for the measurement is 5 A.
±90
±40
±50
VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A
Gain
±120
Phase
±150
±60
±180
10
100
1k
10k
100k
Frequency (Hz)
1M
C053
Time = 100 µs/div
Figure 7. Load Transient Response
6
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Figure 8. Loop Response
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2.5
Line Transients
VIN
10 mV/div
10 V/div
The EVM response to line transients is shown in Figure 9. The input voltage step is from 8.0 V to 40 V.
Total peak-to-peak voltage variation is as shown, including ripple and noise on the output.
VOUT ±3.3V offset
Time = 4 ms/div
Figure 9. Line Transient Response
2.6
Input Voltage Ripple
The EVM CCM input voltage ripple is shown in Figure 10. The output current is the rated full load of 5 A
and VIN = 12 V. The voltage ripple is measured directly across the input capacitors.
The DCM input voltage ripple is shown in Figure 11. The output current is 0.1 A and VIN = 12 V.
SW
500 mA/div
1 A/div
10 V/div
10 V/div
SW
10 mV/div
200 mV/div
IL
IL
VIN ± AC Coupled
IOUT = 100 mA
VIN ± AC Coupled
Time = 4 Ps/div
Time = 4 Ps/div
Figure 10. Input Voltage Ripple CCM
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Figure 11. Input Voltage Ripple DCM
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Output Voltage Ripple
The EVM CCM output voltage ripple is shown in Figure 12. The output current is the rated full load of 5 A
and VIN = 12 V. The voltage ripple is measured directly across the output capacitors.
The DCM output voltage ripple is shown in Figure 13. The output current is 0.1 A and VIN = 12 V.
The Pulse Skip Eco-mode™ output voltage ripple is shown in Figure 14. There is no external load on the
output and VIN = 12 V.
10 V/div
SW
500 mA/div
IL
10 mV/div
IL
10 mV/div
1 A/div
10 V/div
SW
VOUT ± AC Coupled
VOUT ± AC Coupled
IOUT = 100 mA
Time = 4 Ps/div
Time = 4 Ps/div
10 V/div
IL
10 mV/div
SW
200 mA/div
Figure 12. Output Voltage Ripple CCM
Figure 13. Output Voltage Ripple DCM
VOUT ± AC Coupled
No Load
Time = 1 ms/div
Figure 14. Output Voltage Ripple Eco-mode
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2.8
Start Up
The start up waveforms are shown in Figure 15, Figure 16, and Figure 17. The input voltage for these
plots is 12 V with a 5-A resistive load. In Figure 15 the top trace shows VIN, the middle trace shows EN,
and the bottom trace shows VOUT. The input voltage is initially applied, and when the input reaches the
undervoltage lockout threshold, the start up sequence begins and the output ramps up toward the set
value of 3.3 V.
In Figure 16 the input voltage is initially applied with EN held low. When EN is released, the start up
sequence begins and the output ramps up toward the set value of 3.3 V.
In Figure 17 the input voltage is initially applied with EN held low. An external voltage of 1.8 V is supplied
to VOUT. When EN is released, the start up sequence begins and the internal reference ramps up from 0 V
with the internal soft-start. When the internal reference reaches the FB voltage the output begins ramping
toward the set value of 3.3 V.
5 V/div
VIN
VOUT
2 V/div
EN
EN
2 V/div
2 V/div
2 V/div
5 V/div
VIN
VOUT
Time = 2 ms/div
Time = 20 ms/div
5 V/div
Figure 15. Start Up Relative to VIN
Figure 16. Start Up Relative to EN
VIN
1 V/div
1 V/div
EN
VOUT DC
Time = 20 ms/div
Figure 17. Prebias Start Up Relative to EN
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Shutdown
The shutdown waveforms are shown in Figure 18 and Figure 19. The input voltage for these plots is 12 V
with a 5-A resistive load. The top trace shows VIN, the middle trace shows EN, and the bottom trace shows
VOUT. In Figure 18 the input voltage is removed, and when the input falls below the undervoltage lockout
threshold, the TPS54540 shuts down and the output falls to ground.
In Figure 19, the input voltage is held at 12 V, and EN is shorted to ground. When EN is grounded, the
TPS54540 is disabled, and the output voltage discharges to ground.
VIN
5 V/div
5 V/div
VIN
EN
1 V/div
1 V/div
EN
2 V/div
VOUT DC
2 V/div
VOUT DC
Time = 20 ms/div
time = 50 µs/div
Figure 18. Shutdown Relative to VIN
Figure 19. Shutdown Relative to EN
2.10 Low Dropout Operation
For improved low dropout operation, the TPS54540 includes a small integrated low-side MOSFET to pull
SW to GND when the BOOT to SW voltage drops below 2.1 V. This recharges the BOOT capacitor for
driving the high-side MOSFET. Figure 20 shows the steady state operation and Figure 21 shows the start
up and shutdown in a low dropout condition. Both measurements are taken with a 5-V output.
C1: SW
20 mV/div
2 V/div
200 mA/div
2 V/div
IOUT = 1 A
EN Floating
C4
C4: IL
VIN
C3
VOUT
C3: VOUT ac coupled
VIN = 5.5 V
VOUT = 5 V
No Load
EN Floating
Time = 20 ms/div
Figure 20. Low Dropout Operation
10
Time = 40 ms/div
Figure 21. Low Dropout Start Up and Shutdown
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3
Board Layout
This section provides a description of the EVM, board layout, and layer illustrations.
3.1
Layout
The board layout for the EVM is shown in Figure 22 through Figure 26. The top-side layer of the EVM is
laid out in a manner typical of a user application. The top and bottom layers are 2-oz copper.
The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are connections
for the remaining pins of the TPS54540 and a large area filled with ground. The bottom layer contains
ground and a signal route for the bootstrap capacitor. The top and bottom and internal ground traces are
connected with multiple vias placed around the board including six vias directly under the TPS54540
device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitors (C1-C3, C10), bootstrap capacitor (C4), and frequency set resistor (R3)
are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components
are also kept close to the IC. The voltage divider network ties to the output voltage at the point of
regulation, the copper VOUT trace past the output connector (J1). For the TPS54540, an additional input
bulk capacitor may be required (C11), depending on the EVM connection to the input supply.
Figure 22. TPS54540EVM-558 Top Assembly and Silkscreen
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Figure 23. TPS54540EVM-558 Top-Side Layout
Figure 24. TPS54540EVM-558 Layer 2 Layout
12
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Figure 25. TPS54540EVM-558 Layer 3 Layout
Figure 26. TPS54540EVM-558 Bottom-Side Layout
3.2
Estimated Circuit Area
The estimated printed-circuit-board area for the components used in this design is 1.025 in2 (661 mm2).
This area does not include test points or connectors. This design uses 0603 components for easy
modifications. The area can be reduced by using smaller-sized components.
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Bill of Materials
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Bill of Materials
Table 5 presents the bill of materials for the EVM.
Table 5. TPS54540EVM-558 Bill of Materials
Count
RefDes
Value
Description
Size
Part Number
MFR
2
C1-3, C10
4.7 µF
CAP, CERM, 4.7uF, 50V, +/-10%, X7R,
1210
1210
STD
STD
1
C4
0.1 µF
CAP, CERM, 0.1uF, 10V, +/-10%, X7R,
0603
0603
STD
STD
1
C5
4700 pF
CAP, CERM, 4700pF, 50V, +/-5%, X7R,
0603
0603
STD
STD
2
C6
100 µF
CAP, CERM, 100uF, 6.3V, +/-20%, X5R,
1210
1210
STD
STD
1
C8
47 pF
CAP, CERM, 47pF, 50V, +/-5%, C0G/NP0,
0603
0603
STD
STD
0
C9, C11-12
open
CAP
Multi sizes
Engineering Only
STD
1
D1
PDS760-13
Diode, Schottky, 60V, 7A, PowerDI5
PowerDI5
PDS760-13
Diodes Inc
1
J3-4
PEC02SAAN
Header, TH, 100mil, 2x1, Gold plated, 230
mil above insulator
TSW-102-07-G-S
TSW-102-07-G-S
Samtec,
Inc.
2
J1-2
ED120/2DS
Terminal Block, 2-pin, 15-A, 5.1mm
0.40 x 0.35 inch
ED120/2DS
OST
1
L1
5.6 µH
Inductor, Shielded Drum Core, Superflux,
5.5uH, 10A, 0.0112 ohm, SMD
WE-HC6
744325550
WE
1
R1
365 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R2
88.7 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R3
243 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R4
16.9 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R5
31.6 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R6
10.2 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
R7
49.9 Ω
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
SH1
Shunt, 100mil, Gold plated, Black
Shunt
SNT-100-BK-G
Samtec,
Inc.
1
TP6
5013
Test point, orange, thru hole
0.125 × 0.125 in
5013
Keystone
1
TP7
5014
Test point, yellow, thru hole
0.125 × 0.125 in
5014
Keystone
3
TP1 TP3
TP5
5010
Test point, red, thru hole
0.125 × 0.125 in
5010
Keystone
3
TP2 TP4
TP8
5011
Test point, black, thru hole
0.125 × 0.125 in
5011
Keystone
1
U1
TPS54540DDA
IC, 42V, 5A, Low Iq, Current Mode, NonSynchronous Monolithic Buck
HSOIC
TPS54540DDA
TI
1
–
PWR558
Any
PCB, 3 in × 3 in × 0.062 in
Notes: 1. These assemblies are ESD sensitive, observe ESD precautions.
2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
14
Evaluation Module for the TPS54540 Step-Down Converter
Copyright © 2013, Texas Instruments Incorporated
SLVU864 – June 2013
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This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
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• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
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Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
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Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
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Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
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Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
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【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
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respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
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なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
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西新宿三井ビル
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EVALUATION BOARD/KIT/MODULE (EVM)
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Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
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4.
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