TPS54540QDDARQ1

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 TPS54540-Q1 4.5-V to 42-V Input, 5-A, Step-Down DC-DC Converter With Eco-mode™ 1 Features 3 Description • • The TPS54540-Q1 device is a 42-V, 5-A, step-down regulator with an integrated high-side MOSFET. The device survives load-dump pulses up to 65 V per ISO 7637. Current mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the no load supply current to 146 μA. Shutdown supply current is reduced to 2 μA when the enable pin is pulled low. 1 • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H1C – Device CDM ESD Classification Level C3B High-Efficiency at Light Loads With PulseSkipping Eco-mode™ 92-mΩ High-Side MOSFET 146-μA Operating Quiescent Current and 2-µA Shutdown Current 100-kHz to 2.5-MHz Adjustable Switching Frequency Synchronizes to External Clock Low Dropout at Light Loads With Integrated BOOT Recharge FET Adjustable UVLO Voltage and Hysteresis 0.8-V 1% Internal Voltage Reference 8-Pin HSOP PowerPAD™ Package –40°C to 150°C TJ Operating Range Supported by WEBENCH® Software Tool • • • VIN A wide adjustable frequency range allows either efficiency or external component size to be optimized. Output current is limited cycle-by-cycle. Frequency foldback and thermal shutdown protect internal and external components during an overload condition. The TPS54540-Q1 is available in an 8-pin thermallyenhanced HSOP PowerPAD package. Device Information(1) PART NUMBER Vehicle Accessories: GPS (See SLVA412), Entertainment, ADAS, eCall USB-Dedicated Charging Ports and Battery Chargers (See SLVA464) Industrial Automation and Motor Control 12-V, 24-V, and 48-V Industrial, Automotive, and Communications Power Systems SPACE Simplified Schematic VIN PACKAGE TPS54540-Q1 BODY SIZE (NOM) HSOP (8) 4.89 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • Undervoltage lockout is internally set at 4.3 V but can be increased using an external resistor divider at the enable pin. The output voltage start-up ramp is internally controlled to provide a controlled start-up and eliminate overshoot. Efficiency vs Load Current BOOT 100 90 TPS54540-Q1 SW COMP 70 Efficiency (%) EN 80 VOUT 60 50 40 30 RT/CLK FB 20 VSeries1 IN = 12 V VSeries2 IN = 36 V VSeries4 IN = 60 V 10 GND 0 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current (A) 4 4.5 5 5.5 C024 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 22 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 8.2 Typical Applications ................................................ 23 9 Power Supply Recommendations...................... 36 10 Layout................................................................... 37 10.1 Layout Guidelines ................................................. 37 10.2 Layout Example .................................................... 37 10.3 Estimated Circuit Area .......................................... 37 11 Device and Documentation Support ................. 38 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 38 38 38 38 38 38 12 Mechanical, Packaging, and Orderable Information ........................................................... 39 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2013) to Revision B Page • ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Changed Thermal Information table values............................................................................................................................ 4 Changes from Original (September 2013) to Revision A Page • Changed the Electrostatic Discharge (CDM) Max value From: 500 V To: 750 V .................................................................. 4 • Changed the ELECTRICAL CHARACTERISTICS condition statement From: TJ = –40°C to 150°C, VIN = 4.5 to 60 V To: TJ = –40°C to 150°C, VIN = 4.5 to 42 V........................................................................................................................... 5 • Changed Figure 4 X-axis From: max = 60V To: max = 45V .................................................................................................. 7 • Changed Figure 16 X-axis From: max = 60V To: max = 45V ................................................................................................ 8 • Changed Figure 18 X-axis From: max = 60V To: max = 45V ................................................................................................ 8 • Changed the FBD, removed the Logic block and Shutdown signal from the OV comparator ............................................. 12 • Changed the APPLICATION INFORMATION section.......................................................................................................... 23 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions DDA Package 8-Pin HSOP With PowerPAD Top View BOOT 1 VIN 2 8 SW 7 GND PowerPAD 9 EN 3 6 COMP RT/CLK 4 5 FB Pin Functions PIN I/O DESCRIPTION NAME NO. BOOT 1 I A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high side MOSFET, the MOSFET stops switching until the capacitor is refreshed. COMP 6 I Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this pin. EN 3 I Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section. FB 5 I Inverting input of the transconductance (gm) error amplifier. GND 7 — Ground RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is reenabled and the operating mode returns to resistor frequency programming. SW 8 O The source of the internal high-side power MOSFET and switching node of the converter. VIN 2 I Input supply voltage is connected to this pin with a 4.5-V to 42-V operating range. PowerPAD 9 — GND pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 3 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage MIN MAX VIN –0.3 65 EN –0.3 8.4 FB –0.3 3 COMP –0.3 3 RT/CLK –0.3 3.6 BOOT-SW –0.3 8 SW –0.6 65 SW, 10-ns Transient UNIT V –2 65 Operating junction temperature –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage 4.5 60 V VO Output voltage 0.8 58.8 V IO Output current 0 5 A TJ Junction Temperature –40 150 °C 6.4 Thermal Information TPS54540-Q1 THERMAL METRIC (1) DDA (HSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 41.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.7 °C/W RθJB Junction-to-board thermal resistance 22.6 °C/W ψJT Junction-to-top characterization parameter 7.9 °C/W ψJB Junction-to-board characterization parameter 22.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 6.5 Electrical Characteristics TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4.3 4.48 UNIT SUPPLY VOLTAGE (VIN PIN) Operating input voltage Internal undervoltage lockout threshold 4.5 Rising 4.1 Internal undervoltage lockout threshold hysteresis 42 V V 325 mV Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V 2.25 4.5 Operating: nonswitching supply current FB = 0.9 V, TA = 25°C 146 175 1.2 1.3 μA ENABLE AND UVLO (EN PIN) Enable threshold voltage Input current No voltage hysteresis, rising and falling 1.1 Enable threshold 50 mV V –4.6 Enable threshold –50 mV Hysteresis current –0.58 –1.2 –1.8 –2.2 –3.4 –4.5 μA μA INTERNAL SOFT-START TIME Soft-start time fSW = 500 kHz, 10% to 90% 2.1 ms Soft-start time fSW = 2.5 MHz, 10% to 90% 0.42 ms VOLTAGE REFERENCE Voltage reference 0.792 0.8 0.808 92 190 V HIGH-SIDE MOSFET On-resistance VIN = 12 V, BOOT-SW = 6 V mΩ ERROR AMPLIFIER Input current Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V Error amplifier transconductance (gM) during soft-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V Error amplifier DC gain VFB = 0.8 V Minimum unity gain bandwidth Error amplifier source and sink V(COMP) = 1 V, 100-mV overdrive COMP to SW current transconductance 50 nA 350 μS 77 μS 10000 V/V 2500 kHz ±30 μA 17 A/V CURRENT LIMIT Current limit threshold All VIN and temperatures, Open Loop (1) 6.3 7.5 8.8 All temperatures, VIN = 12 V, Open Loop (1) 6.3 7.5 8.3 VIN = 12 V, TA = 25°C, Open Loop (1) 7.1 7.5 7.9 A THERMAL SHUTDOWN Thermal shutdown Thermal shutdown hysteresis 176 °C 12 °C 540 µs ERROR AMPLIFIER Enable to COMP active (1) VIN = 12 V, TA = 25°C Open-loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation. 6.6 Timing Requirements TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted) MIN NOM MAX UNIT RT/CLK Minimum CLK input pulse width 15 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 ns 5 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 6.7 Switching Characteristics TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT Current limit threshold delay 60 ns RT/CLK Switching frequency range using RT mode fSW Switching frequency 100 RT = 200 kΩ Switching frequency range using CLK mode 450 160 RT/CLK high threshold 1.55 RT/CLK low threshold 6 500 0.5 2500 kHz 550 kHz 2300 kHz 2 V 1.2 V RT/CLK falling edge to SW rising edge delay Measured at 500 kHz with RT resistor in series 55 ns PLL lock in time Measured at 500 kHz 78 μs Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 6.8 Typical Characteristics 0.814 VFB - Voltage Referance ( V) RDSON - On-State Resistance ( ) 0.25 0.2 0.15 0.1 0.05 BOOT-SW = 3 V 0.809 0.804 0.799 0.794 0.789 BOOT-SW = 6 V 0 0.784 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) ±50 150 8.5 8.5 High Side Switch Current (A) High Side Switch Current (A) 9 7.5 7 6.5 25 50 75 100 125 150 C026 Figure 2. Voltage Reference vs Junction Temperature 9 8 0 TJ - Junction Temperature (ƒC) Figure 1. ON-Resistance vs Junction Temperature 6 ±40ƒC Series1 25ƒC Series2 150ƒC Series4 8 7.5 7 6.5 6 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) 0 150 5 10 540 450 FSW - Switching Frequency (kHz) 500 520 510 500 490 480 470 460 450 20 25 30 35 40 45 C028 Figure 4. Switch Current Limit vs Input Voltage 550 530 15 VI - Input Voltage (V) C027 Figure 3. Switch Current Limit vs Junction Temperature FS - Switching Frequency (kHz) ±25 C025 400 350 300 250 200 150 100 50 0 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 200 Figure 5. Switching Frequency vs Junction Temperature 300 400 500 600 700 800 900 RT/CLK - Resistance (k ) C029 1000 C030 Figure 6. Switching Frequency vs RT/CLK Resistance LowFrequency Range Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 7 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) 500 2300 450 2100 1900 400 gm (µA/V) FSW - Switching Frequency (kHz) 2500 1700 1500 1300 300 1100 900 250 700 500 200 0 50 100 150 ±50 200 RT/CLK - Resistance (k ) EN - Threshold (V) 100 gm (µA/V) 80 70 60 50 40 30 20 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) ±50 100 125 150 C032 0 25 50 75 100 125 150 C034 Figure 10. EN Pin Voltage vs Junction Temperature ±0.5 ±3.7 ±0.7 ±3.9 ±0.9 ±4.1 ±1.1 ±4.3 ±1.3 IEN (µA) ±3.5 ±1.5 ±1.7 ±4.9 ±1.9 ±5.1 ±2.1 ±5.3 ±2.3 ±5.5 75 TJ - Junction Temperature (ƒC) Figure 9. EA Transconductance During Soft-Start vs Junction Temperature IEN (uA) ±25 C033 ±4.7 50 1.3 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.2 1.19 1.18 1.17 1.16 1.15 150 ±4.5 25 Figure 8. EA Transconductance vs Junction Temperature 110 90 0 TJ - Junction Temperature (ƒC) 120 ±50 ±25 C031 Figure 7. Switching Frequency vs RT/CLK Resistance High-Frequency Range ±2.5 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) C035 Figure 11. EN Pin Current vs Junction Temperature 8 350 125 150 C036 Figure 12. EN Pin Current vs Junction Temperature Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Typical Characteristics (continued) 100 % of Nominal Switching Frequency ±2.5 ±2.7 IEN - Hysteresis (µA) ±2.9 ±3.1 ±3.3 ±3.5 ±3.7 ±3.9 ±4.1 ±4.3 Series2 VSENSE Falling VSENSE Rising Series4 75 50 25 0 ±4.5 ±50 ±25 0 25 50 75 100 125 0.0 150 TJ - Junction Temperature (ƒC) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VSENSE (V) C037 Figure 13. EN Pin Current Hysteresis vs Junction Temperature 0.8 C038 Figure 14. Switching Frequency vs VSENSE 3 3 2.5 2.5 2 2 IVIN (µA) IVIN (µA) TJSeries2 = 25ƒC 1.5 1.5 1 1 0.5 0.5 0 0 ±50 ±25 0 25 50 75 100 125 0 150 TJ - Junction Temperature (ƒC) 5 10 Figure 15. Shutdown Supply Current vs Junction Temperature 15 20 25 30 35 40 VIN - Input Voltage (V) C039 45 C040 Figure 16. Shutdown Supply Current vs Input Voltage (VIN) 210 210 190 190 170 170 IVIN (µA) IVIN (µA) TJSeries2 = 25ƒC 150 130 150 130 110 110 90 90 70 70 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 0 Figure 17. VIN Supply Current vs Junction Temperature 5 10 15 20 25 30 35 40 VIN - Input Voltage (V) C041 45 C042 Figure 18. VIN Supply Current vs Input Voltage Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 9 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) 2.6 2.5 2.4 4.3 2.3 4.2 2.2 4.0 2.0 3.9 1.9 3.8 3.7 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) ±50 150 0 5.5 8 5.4 7 5.3 6 5.2 VIN (V) 5.6 75 100 125 150 C044 Start Stop 5.1 4 5 3 4.9 2 4.8 1 4.7 0 4.6 Dropout Voltage Dropout Voltage 2500 2300 2100 1900 1700 1500 1300 1100 900 700 500 300 100 0 0.05 0.1 0.15 0.2 0.25 0.3 Output Current (A) C045 Figure 21. Soft-Start Time vs Switching Frequency 50 Figure 20. Input Voltage UVLO vs Junction Temperature 9 5 25 TJ - Junction Temperature (ƒC) 10 Switching Frequency (kHz) ±25 C043 Figure 19. BOOT-SW UVLO vs Junction Temperature Soft-Start Time (ms) 4.1 2.1 1.8 10 UVLO Start Switching UVLO Stop Switching 4.4 VIN (V) VI - BOOT-PH (V) 4.5 BOOT-PH UVLO Falling BOOT-PH UVLO Rising 0.35 0.4 0.45 0.5 C046 Figure 22. 5-V Start and Stop Voltage (See Low Dropout Operation and Bootstrap Voltage (BOOT)) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 7 Detailed Description 7.1 Overview The TPS54540-Q1 device is a 42-V, 5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. The device implements constant frequency, current mode control that reduces output capacitance and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows either efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop (PLL) connected to the RT/CLK pin that will synchronize the power switch turnon to a falling edge of an external clock signal. The TPS54540-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current source enables operation when the EN pin is floating. The operating current is 146 μA under no load condition (not switching). When the device is disabled, the supply current is 2 μA. The integrated 92-mΩ high-side MOSFET supports high-efficiency power supply designs capable of delivering 5 A of continuous current to a load. The gate drive bias voltage for the integrated high-side MOSFET is supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54540-Q1 device reduces the external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54540-Q1 device to operate at high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the application. The minimum output voltage is the internal 0.8-V feedback reference. Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than 106% of the desired output voltage. The TPS54540-Q1 device includes an internal soft-start circuit that slows the output rise time during start-up to reduce in-rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help maintain control of the inductor current. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 11 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 7.2 Functional Block Diagram EN VIN Thermal Shutdown UVLO Enable Comparator OV Shutdown Shutdown Logic Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum Clamp Pulse Skip Error Amplifier PWM Comparator FB Current Sense BOOT Logic Shutdown 6 Slope Compensation SW COMP Frequency Foldback Reference DAC for Soft- Start Maximum Clamp Oscillator with PLL 8/8/ 2012 A 0192789 GND POWERPAD RT/ CLK 7.3 Feature Description 7.3.1 Fixed Frequency PWM Control The TPS54540-Q1 device uses fixed frequency, peak current mode control with adjustable switching frequency. The output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output at the COMP pin controls the high-side power switch current. When the high-side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements current limiting by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a minimum voltage clamp on the COMP pin. 7.3.2 Slope Compensation Output Current The TPS54540-Q1 device adds a compensating ramp to the MOSFET switch current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range. 12 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Feature Description (continued) 7.3.3 Pulse-Skip Eco-mode The TPS54540-Q1 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV. When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited. Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal. During Eco-mode operation, the TPS54540-Q1 device senses and controls peak switch current, not the average load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor value. As the load current approaches zero, the device enters a pulse-skip mode during which it draws only 152 µA of input quiescent current. The circuit in Figure 34 enters Eco-mode at about 18-mA output current, and with no external load has an average input current of 240 µA. 7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS54540-Q1 device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT capacitor is 0.1 μF. For stable performance over temperature and voltage, TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher. When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54540-Q1 device will operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the voltage from BOOT to SW drops to less than 2.1 V, the high-side MOSFET is turned off and an integrated lowside MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high-output voltages, it is disabled at 24-V output and reenabled when the output reaches 21.5 V. Because the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus, the effective duty cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the lowside diode voltage and the printed-circuit-board resistance. The start and stop voltage for a typical 5-V output application is shown in Figure 22 where the VIN voltage is plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where switching stops. During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle PWM control. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 13 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) At heavy loads, the minimum input voltage must be increased to insure a monotonic start-up. Equation 1 can be used to calculate the minimum input voltage for this condition. VOmax = Dmax × (VVINmin – IOmax × RDS(on) + Vd) – Vd – IOmax × Rdc where • • • • • • Dmax ≥ 0.9 Vd = Forward Drop of the Catch Diode RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246) VB2SW = VBOOT + Vd VBOOT = (1.41 × VVIN – 0.554 – Vd × ƒSW – 1.847 × 103 × IB2SW) / (1.41 + ƒSW) IB2SW = 100 × 10–6A (1) 7.3.5 Error Amplifier The TPS54540-Q1 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal softstart voltage. The frequency compensation components (capacitor, series resistor and capacitor) are connected between the error amplifier output COMP pin and GND pin. 7.3.6 Adjusting the Output Voltage The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor divider from the output node to the FB pin. TI recommends using 1% tolerance or better divider resistors. Select the low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable. æ Vout - 0.8V ö RHS = RLS ´ ç ÷ 0.8 V è ø (2) 7.3.7 Enable and Adjusting Undervoltage Lockout The TPS54540-Q1 device is enabled when the VIN pin voltage is greater than 4.3 V and the EN pin voltage exceeds the enable threshold of 1.2 V. The TPS54540-Q1 device is disabled when the VIN pin voltage falls less than 4 V or when the EN pin voltage is less than 1.2 V. The EN pin has an internal pullup current source, I1, of 1.2 μA that enables operation of the TPS54540-Q1 device when the EN pin floats. If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 23 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled to less than 1.2 V, the 3.4-μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for the desired VIN start voltage. In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high input voltages (for example, 40 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN resistors, the EN pin is clamped internally with a 5.8 V Zener diode that will sink up to 150 μA. 14 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Feature Description (continued) VIN TPS54540-Q1 i1 VIN ihys RUVLO1 RUVLO1 EN EN 10 kW Node VEN RUVLO2 RUVLO2 Figure 23. Adjustable Undervoltage Lockout (UVLO) 5.8 V Figure 24. Internal EN Clamp - VSTOP V RUVLO1 = START IHYS (3) VENA RUVLO2 = VSTART - VENA + I1 RUVLO1 (4) 7.3.8 Internal Soft Start The TPS54540-Q1 device has an internal digital soft start that ramps the reference voltage from zero volts to its final value in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 5. 1024 tSS (ms) = fSW (kHz) (5) If the EN pin is pulled below the stop threshold of 1.2 V, switching stops and the internal soft start resets. The soft start also resets in thermal shutdown. 7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin) The switching frequency of the TPS54540-Q1 device is adjustable over a wide range from 100 kHz to 2500 kHz by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V, and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 6 or Equation 7 or the curves in Figure 5 and Figure 6. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time is typically 135 ns, which limits the maximum operating frequency in applications with high input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. See Accurate Current Limit for a more detailed discussion of the maximum switching frequency. 92417 RT (kW) = f sw (kHz)0.991 (6) f sw (kHz) = 101756 RT (kW)1.008 (7) 7.3.10 Synchronization to RT/CLK Pin The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in Figure 25. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and have a pulse-width greater than 15 ns. The synchronization frequency range is from 160 kHz to 2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 15 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) circuit should be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 25. The two resistors in series provide the default frequency setting resistance when the signal source is turned off. The sum of the resistance should set the switching frequency close to the external CLK frequency. TI recommends ac-coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin. The first time the RT/CLK is pulled above the PLL threshold, the TPS54540-Q1 device switches from the RT resistor free-running frequency mode to the PLL synchronized mode. The internal 0.5-V voltage source is removed, and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor mode to the PLL mode, and locks onto the external clock frequency within 78 µs. During the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz and then increase or decrease to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the RT/CLK resistor. The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 V to 0.8 V. The device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and fault conditions. Figure 26, Figure 27, and Figure 28 show the device synchronized to an external system clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-mode). SPACER TPS54540-Q1 TPS54540-Q1 RT/CLK RT/CLK PLL PLL RT Hi-Z Clock Source Clock Source RT Figure 25. Synchronizing to a System Clock SW SW EXT EXT IL IL Figure 26. Plot of Synchronizing in CCM 16 Figure 27. Plot of Synchronizing in DCM Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Feature Description (continued) SW EXT IL Figure 28. Plot of Synchronizing in Eco-mode™ 7.3.11 Maximum Switching Frequency To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54540-Q1 device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54540-Q1 device uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short circuit events, the inductor current can exceed the peak current limit because of the high input voltage and the minimum controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down. With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. Equation 9 calculates the maximum switching frequency at which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency should not exceed the calculated value. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 17 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) Equation 8 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage. æ I ´R + V dc OUT + Vd ´ç O ç VIN - IO ´ RDS(on ) + Vd è ö ÷ ÷ ø fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd ´ tON ç VIN - ICL ´ RDS(on ) + Vd è ö ÷ ÷ ø fSW (max skip ) = fSW(shift) = 1 tON (8) where • • • • • • • • • • IO = Output current ICL = Current limit Rdc = inductor resistance VIN = maximum input voltage VOUT = output voltage VOUTSC = output voltage during short Vd = diode voltage drop RDS(on) = switch on resistance tON = controllable on time ƒDIV = frequency divide equals (1, 2, 4, or 8) (9) 7.3.12 Accurate Current Limit The TPS54540-Q1 device implements peak current mode control in which the COMP pin voltage controls the peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the highside switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the peak switch current limit. The TPS54540-Q1 device provides an accurate current limit threshold with a typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The relationship between the inductor value and the peak inductor current is shown in Figure 29. Inductor Current (A) Peak Inductor Current ΔCLPeak Open Loop Current Limit ΔCLPeak = VIN/L x tCLdelay tCLdelay tON Figure 29. Current Limit Delay 18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Feature Description (continued) 7.3.13 Overvoltage Protection The TPS54540-Q1 device incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low-output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. In some applications, the power supply output voltage can increase faster than the response of the error amplifier output resulting in an output overshoot. The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB pin voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal voltage reference, the high-side MOSFET resumes normal operation. 7.3.14 Thermal Shutdown The TPS54540-Q1 device provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature falls to less than 164°C, the device reinitiates the power-up sequence controlled by the internal soft-start circuitry. 7.3.15 Small Signal Model for Loop Response Figure 30 shows an equivalent model for the TPS54540-Q1 device control loop, which can be simulated to check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation. SW VO Power Stage gmps 17 A/V a b RESR R1 RL COMP c 0.8 V R3 CO C2 RO FB COUT gmea 350 mA/V R2 C1 Figure 30. Small Signal Model for Loop Response Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 19 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) 7.3.16 Simple Small Signal Model for Peak Current Mode Control Figure 31 describes a simple small signal model that can be used to design the frequency compensation. The TPS54540-Q1 power stage can be approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 10 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage transconductance, gmPS. The gmPS for the TPS54540-Q1 device is 17 A/V. The low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in Equation 11. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of Figure 31. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 13). VO Adc VC RESR fp RL gmps COUT fz Figure 31. Simple Small Signal Model and Frequency Response for Peak Current Mode Control æ s ö ç1 + ÷ 2 p ´ fZ ø VOUT = Adc ´ è VC æ s ö ç1 + ÷ 2p ´ fP ø è Adc = gmps ´ RL (10) (11) 1 fP = COUT ´ RL ´ 2p fZ = 20 (12) 1 COUT ´ RESR ´ 2p (13) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Feature Description (continued) 7.3.17 Small Signal Model for Frequency Compensation The TPS54540-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 32. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 14 and Equation 15 relate the frequency response of the amplifier to the small signal model in Figure 32. The open-loop gain and bandwidth are modeled using the RO and CO shown in Figure 32. See the Typical Applications section for a design example using a Type 2A network with a low ESR output capacitor. Equation 14 through Equation 23 are provided as a reference. An alternative is to use WEBENCH software tools to create a design based on the power supply requirements. VO R1 FB gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 32. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 33. Frequency Response of the Type 2A and Type 2B Frequency Compensation Aol(V/V) gmea gmea = 2p ´ BW (Hz) Ro = CO (14) (15) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 21 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) æ ö s ç1 + ÷ 2p ´ fZ1 ø è EA = A0 ´ æ ö æ ö s s ç1 + ÷ ´ ç1 + ÷ 2 2 p ´ p ´ f f P1 ø è P2 ø è R2 R1 + R2 R2 ´ Ro| | R3 ´ R1 + R2 A0 = gmea ´ Ro ´ A1 = gmea P1 = Z1 = P2 = (17) (18) 1 2p ´ Ro ´ C1 (19) 1 2p ´ R3 ´ C1 (20) 1 2p ´ R3 | | RO ´ (C2 + CO ) type 2a (21) 1 P2 = type 2b 2p ´ R3 | | RO ´ CO P2 = 2p ´ R O (16) 1 type 1 ´ (C2 + C O ) (22) (23) 7.4 Device Functional Modes The TPS54540-Q1 device is designed to operate with input voltages greater than 4.5 V. When the VIN voltage is greater than the 4.3 V typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the device is active. If the VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the EN voltage falls below the 1.2-V threshold the device stops switching and enters a shutdown mode with low supply current of 2 μA typical. The TPS54540-Q1 device operates in CCM when the output current is enough to keep the inductor current greater than 0 A at the end of each switching period. As a nonsynchronous converter, it will enter DCM at lowoutput currents when the inductor current falls to 0 A before the end of a switching period. At very low-output current the COMP voltage will drop to the pulse-skipping threshold and the device operates in a pulse-skipping Eco-mode. In this mode, the high-side MOSFET does not switch every switching period. This operating mode reduces power loss while keeping the output voltage regulated. For more information on Eco-mode, see the Pulse-Skip Eco-mode section. 22 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS54540-Q1 device is a 42-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 5 A. Example applications are: 12-V and 24-V industrial, automotive, and communications power systems. Use the following design procedure to select component values for the TPS54540-Q1 device. This procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. 8.2 Typical Applications 8.2.1 Buck Converter With 6-V to 42-V Input and 3.3-V at 5-A Output L1 5.5uH 3.3V, 5A VOUT C4 0.1uF U1 TPS54540-Q1DDA 6V to 42V 2 3 C10 C3 C1 4.7uF 4.7uF 4.7uF C2 4.7uF R1 365k 4 SW BOOT VIN GND EN COMP RT/CLK PWRPD 1 VIN 9 R2 88.7k R3 243k FB C6 D1 8 100uF B560C C7 100uF R5 31.6k 7 6 5 FB FB R4 16.9k C8 R6 10.2k 47pF C5 4700pF Figure 34. 3.3-V Output TPS54540 Design Example 8.2.1.1 Design Requirements This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. A few parameters must be known to start the design process. These requirements are typically determined at the system level. This example in Figure 34 is designed with the known parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUE Output Voltage 3.3 V Transient Response 1.25-A to 3.75-A load step ΔVOUT = 4 % Maximum Output Current 5A Input Voltage 12 V nom. 6 V to 42 V Output Voltage Ripple 0.5% of VOUT Start Input Voltage (rising VIN) 5.75 V Stop Input Voltage (falling VIN) 4.5 V Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 23 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Selecting the Switching Frequency The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest switching frequency possible because this produces the smallest solution size. High switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency foldback protection. Equation 8 and Equation 9 should be used to calculate the upper limit of the switching frequency for the regulator (see Equation 24 and Equation 25). Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit. The typical minimum on time, tonmin, is 135 ns for the TPS54540-Q1 device. Equation 8 and Equation 9 should be used to calculate the upper limit of the switching for the regulator (see Equation 24 and Equation 25). For this example, the output voltage is 3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of 10.3 mΩ, typical switch resistance of 92-mΩ and 5-A load, from Equation 8 the maximum switch frequency to avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits use Equation 9 to determine the maximum switching frequency for frequency foldback protection. With a current limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz. For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 6 or the curve in Equation 6. The switching frequency is set by resistor R3 shown in Figure 34. For 400-kHz operation, the closest standard value resistor is 243 kΩ (see Equation 26). 1 æ 5 A x 10.3 mW + 3.3 V + 0.52 V ö fSW(max skip) = ´ ç ÷ = 680 kHz 135ns è 42 V - 5 A x 92 mW + 0.52 V ø (24) 8 æ 6.3 A x 10.3 mW + 0.1 V + 0.52 V ö ´ ç ÷ = 960 kHz 135 ns è 42 V - 6.3 A x 92 mW + 0.52 V ø 92417 RT (kW) = = 244 kW 400 (kHz)0.991 fSW(shift) = (25) (26) 8.2.1.2.2 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 27. KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable. When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple current. This provides sufficient ripple current with the input voltage at the minimum. For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 29 and Equation 30 (using Equation 28). For this design, the RMS inductor current is 5 A and the peak inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A and an RMS current rating of 10 A. This conductor also has a typical inductance of 5.5 µH at no load and 4.8 µH at a 5-A load. Lastly, the chosen conductor has a DCR of 10.3 mΩ. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. 24 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54540 device, which is nominally 7.5 A. VIN(max ) - VOUT VOUT 42 V - 3.3 V 3.3 V ´ = ´ = 5.1 mH LO(min ) = IOUT ´ KIND VIN(max ) ´ fSW 5 A x 0.3 42 V ´ 400 kHz (27) spacer IRIPPLE = VOUT ´ (VIN(max ) - VOUT ) VIN(max ) ´ LO ´ fSW = 3.3 V x (42 V - 3.3 V) = 1.58 A 42 V x 4.8 mH x 400 kHz (28) spacer ( æ 1 ç VOUT ´ VIN(max ) - VOUT 2 IL(rms ) = (IOUT ) + ´ 12 çç VIN(max ) ´ LO ´ fSW è )÷ö 2 ÷ = ÷ ø 2 (5 A ) 2 æ 3.3 V ´ (42 V - 3.3 V ) ö 1 + ´ ç ÷ =5A ç ÷ 12 è 42 V ´ 4.8 mH ´ 400 kHz ø (29) spacer IL(peak ) = IOUT + IRIPPLE 1.58 A = 5A + = 5.79 A 2 2 (30) 8.2.1.2.3 Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the increased load current until the regulator responds to the load step. A regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. Equation 31 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore, ΔIOUT is 3.75 A – 1.25 A = 2.5 A and ΔVOUT = 0.04 × 3.3 V = 0.13 V. Using these numbers gives a minimum capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is shown in Figure 39. The excess energy absorbed in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 32 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 V = 3.43 V. Vi is the initial capacitor voltage that is the nominal output voltage of 3.3 V. Using these numbers in Equation 32 yields a minimum capacitance of 68 μF. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 25 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Equation 33 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. Equation 33 yields 30 μF. Equation 34 calculates the maximum ESR an output capacitor must meet the output voltage ripple specification. Equation 34 indicates the equivalent ESR should be less than 10 mΩ. The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within regulation tolerance during a load transient. Capacitance deratings for aging, temperature and Eco-mode bias increases this minimum value. For this example, 2 × 100-μF, 6.3-V type X5R ceramic capacitors with 2 mΩ of ESR will be used. The derated capacitance is 130 µF, well above the minimum required capacitance of 95 µF. Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability, especially non ceramic capacitors. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 35 can be used to calculate the RMS ripple current that the output capacitor must support. For this example, Equation 35 yields 460 mA. 2 ´ DIOUT 2 ´ 2.5 A COUT > = = 95 mF fSW ´ DVOUT 400 kHz x 0.13 V (31) ((I ) - (I ) ) = 4.8 mH x (3.75 A - 1.25 A ) = 68 mF x (3.43 V - 3.3 V ) ((V ) - (V ) ) 2 OH COUT > LO 2 2 2 2 2 OL 2 f 2 I (32) 1 1 1 1 x ´ = = 30 mF 8 ´ fSW æ VORIPPLE ö 8 x 400 kHz æ 16 mV ö ç 1.58 A ÷ ç ÷ è ø è IRIPPLE ø V 16 mV RESR < ORIPPLE = = 10 mW IRIPPLE 1.58 A COUT > ICOUT(rms) = ( VOUT ´ VIN(max ) - VOUT )= 12 ´ VIN(max ) ´ LO ´ fSW 3.3 V ´ (42 V - 3.3 V ) 12 ´ 42 V ´ 4.8 mH ´ 400 kHz (33) (34) = 460 mA (35) 8.2.1.2.4 Catch Diode The TPS54540 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator. Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54540-Q1 device. For the example design, the PDS760-13 Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760-13 is 0.52 V at 5 A and 25°C. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 36 is used to calculate the total power dissipation, including conduction losses and AC losses of the diode. The PDS760-13 diode has a junction capacitance of 300 pF. Using Equation 36, the total loss in the diode at the nominal input voltage is 1.9 W. 26 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode, which has a low leakage current and slightly higher forward voltage drop. PD = (V IN(max ) - VOUT )´ I OUT + VIN (12 V 2 ´ Vf d - 3.3 V ) ´ 5 A x 0.52 V 12 V C j ´ fSW ´ (VIN + Vf d) = 2 + 300 pF x 400 kHz x (12 V + 0.52 V)2 = 1.9 W 2 (36) 8.2.1.2.5 Input Capacitor The TPS54540-Q1 device requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance due to DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54540-Q1 device. The input ripple current can be calculated using Equation 37. The value of a ceramic capacitor varies significantly with temperature and the Eco-mode bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V. For this example, four 4.7-μF, 50-V capacitors in parallel are used. Table 2 lists several choices of high voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage ripple occurs at 50% duty cycle and can be calculated using Equation 38. Using the design example values, IOUT = 5 A, CIN = 18.8 μF, ƒsw = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of 2.5 A. ICI(rms ) = IOUT x VOUT x VIN(min ) (V IN(min ) - VOUT VIN(min ) ) = 5A 3.3 V ´ 6V (6 V - 3.3 V ) 6V = 2.5 A (37) I ´ 0.25 5 A ´ 0.25 DVIN = OUT = = 170 mV CIN ´ fSW 18.8 mF ´ 400 kHz (38) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 27 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Table 2. Capacitor Types VENDOR VALUE (μF) 1 to 2.2 Murata 1 to 4.7 1 1 to 2.2 1 to 1.8 Vishay 1 to 1.2 1 to 3.9 1 to 1.8 1 to 2.2 TDK 1.5 to 6.8 1 to 2.2 1 to 3.3 1 to 4.7 AVX 1 1 to 4.7 1 to 2.2 EIA SIZE 1210 1206 2220 2225 1812 1210 1210 1812 VOLTAGE DIALECTRIC 100 V COMMENTS GRM32 series 50 V 100 V GRM31 series 50 V 50 V 100 V VJ X7R series 50 V 100 V X7R 100 V C series C4532 50 V 100 V C series C3225 50 V 50 V 100 V X7R dielectric series 50 V 100 V 8.2.1.2.6 Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10-V or higher voltage rating. 8.2.1.2.7 Undervoltage Lockout Set Point The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54540-Q1device. The UVLO has two thresholds, one for power-up when the input voltage is rising and one for power-down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage is greater than 5.75 V (UVLO start). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.5 V (UVLO stop). Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the example application, a 365 kΩ between VIN and EN (RUVLO1) and a 88.7 kΩ between EN and ground (RUVLO2) are required to produce the 5.75-V and 4.5-V start and stop voltages. V - VSTOP 5.75 V - 4.5 V RUVLO1 = START = = 368 kW IHYS 3.4 mA (39) RUVLO2 = VENA 1.2 V = = 88.7 kW VSTART - VENA 5.75 V - 1.2 V + m 1.2 A + I1 365 kW RUVLO1 (40) 8.2.1.2.8 Output Voltage and Feedback Resistors Selection The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6. Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher resistor values decreases quiescent current and improves efficiency at low-output currents but may also introduce noise immunity problems. For more details about adjusting the output voltage, see Equation 41. V - 0.8 V æ 3.3 V - 0.8 V ö RHS = RLS x OUT = 10.2 kW x ç ÷ = 31.9 kW 0.8 V 0.8 V è ø (41) 28 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 8.2.1.2.9 Compensation There are several methods to design compensation for DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 42 and Equation 43. For COUT, use a derated value of 130 μF. Use equations Equation 44 and Equation 45 to estimate a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1850 Hz and ƒz(mod) is 610 kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of modulator pole and half of the switching frequency. Equation 44 yields 34 kHz and Equation 45 gives 19 kHz. Use the geometric mean value of Equation 44 and Equation 45 for an initial crossover frequency. For this example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved transient response. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. IOUT(max ) 5A fP(mod) = = = 1850 Hz 2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 130 mF (42) f Z(mod) = 1 1 = = 610 kHz 2 ´ p ´ RESR ´ COUT 2 ´ p ´ 1 mW ´ 130 mF fco1 = fp(mod) x f z(mod) = fco2 = fp(mod) x fSW 2 = 1850 Hz x 610 kHz = 34 kHz 400 kHz 2 = 19 kHz 1850 Hz x (43) (44) (45) To determine the compensation resistor, R4, use Equation 46. The typical power stage transconductance, gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 5100 pF for compensating capacitor C5. 4700 pF is used for this design. ö VOUT æ 2 ´ p ´ fco ´ COUT ö æ ö 3.3V æ 2 ´ p ´ 30 kHz ´ 130 mF ö æ R4 = ç ÷ = ç ÷ x ç ÷ x ç 0.8 V x 350 mA / V ÷ = 17 kW gmps V x gmea 17 A / V è ø è ø è ø è REF ø (46) 1 1 C5 = = = 5100 pF 2 ´ p ´ R4 x fp(mod) 2 ´ p ´ 16.9 kW x 1850 Hz (47) A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 48 and Equation 49 for C8 to set the compensation pole. The selected value of C8 is 47 pF for this design example. C x RESR 130 mF x 1 mW = = 15 pF C8 = OUT R4 16.9 kW (48) 1 1 C8 = = = 47 pF R4 x f sw x p 16.9 kW x 400 kHz x p (49) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 29 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 8.2.1.2.10 Power Dissipation Estimate The formulas in Equation 50 and Equation 56 show how to estimate the TPS54540-Q1 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example. æV ö 5V 2 PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 5 A 2 ´ 92 mW ´ = 0.958 W V 12 V è IN ø (50) spacer PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W (51) spacer PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 400 kHz = 0.014 W (52) spacer PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W where • • • • • • • • IOUT is the output current (A) RDS(on) is the on-resistance of the high-side MOSFET (Ω) VOUT is the output voltage (V) VIN is the input voltage (V) fsw is the switching frequency (Hz) trise is the SW pin voltage rise time and can be estimated by trise = VIN × 0.16 ns/V + 3 ns QG is the total gate charge of the internal MOSFET IQ is the operating nonswitching supply current (53) Therefore, PTOT = PCOND + PSW + PGD + PQ = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W (54) For given TA, TJ = TA + RTH ´ PTOT (55) For given TJMAX = 150°C TA (max ) = TJ(max ) - RTH ´ PTOT where • • • • • • Ptot is the total device power dissipation (W) TA is the ambient temperature (°C) TJ is the junction temperature (°C) RTH is the thermal resistance of the package (°C/W) TJMAX is maximum junction temperature (°C) TAMAX is maximum ambient temperature (°C) (56) There will be additional power losses in the regulator circuit due to the inductor AC and Eco-mode losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator. 30 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 8.2.1.2.11 Safe Operating Area 90 90 80 80 70 70 60 60 TA (ƒC) TA (ƒC) The safe operating area (SOA) of the device is shown in Figure 35, through Figure 38 for 3.3-V, 5-V, and 12-V outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at which the TPS54540-Q1 device is at or below the maximum operating temperature. The device is soldered directly to the EVM, which is a 4-layer double-sided PCB with 2-oz. copper. Careful attention must be paid to the other components chosen for the design, especially the catch diode. 50 40 40 6V 12 V 24 V 36 V 30 20 0.0 0.5 50 8V 12 V 24 V 36 V 30 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IOUT (Amps) 5.0 0.0 0.5 1.0 2.0 2.5 3.0 3.5 4.0 4.5 IOUT (Amps) Figure 35. 3.3-V Outputs 5.0 C048 Figure 36. 5-V Outputs 90 90 80 80 70 70 60 60 TA (ƒC) TA (ƒC) 1.5 C047 50 50 400 LFM 40 40 18 V 24 V 30 36 V 20 0.0 0.5 1.0 200 LFM 100 LFM 30 Nat Conv 20 1.5 2.0 2.5 3.0 3.5 IOUT (Amps) 4.0 4.5 5.0 0.0 0.5 C048 Figure 37. 12-V Outputs 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IOUT (Amps) 5.0 C048 Figure 38. Air Flow Conditions VIN = 36 V, VO = 12 V 8.2.1.2.12 Discontinuous Conduction Mode and Eco-mode Boundary With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input current draw is 240 μA with no load. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 31 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 8.2.1.3 Application Curves 10 V/div 1 A/div Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted. IOUT VIN 100 mV/div 10 mV/div VOUT ±3.3V offset VOUT ±3.3V offset Time = 4 ms/div Time = 100 Ps/div Figure 40. Line Transient (8 V to 40 V) Figure 39. Load Transient 5 V/div VIN VOUT 2 V/div EN EN 2 V/div 2 V/div 2 V/div 5 V/div VIN VOUT Time = 2 ms/div Time = 20 ms/div Figure 42. Start-Up With EN Figure 41. Start-Up With VIN 10 V/div SW 500 mA/div IL 10 mV/div IL 10 mV/div 1 A/div 10 V/div SW VOUT ± AC Coupled VOUT ± AC Coupled IOUT = 100 mA Time = 4 Ps/div Time = 4 Ps/div Figure 43. Output Ripple CCM 32 Submit Documentation Feedback Figure 44. Output Ripple DCM Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted. 10 V/div 1 A/div 10 V/div IL IL 200 mV/div 10 mV/div 200 mA/div SW SW VOUT ± AC Coupled No Load VIN ± AC Coupled Time = 1 ms/div Time = 4 Ps/div Figure 45. Output Ripple PSM Figure 46. Input Ripple CCM 10 V/div 2 V/div SW SW VIN ± AC Coupled IL VOUT = 5 V 20 mV/div 10 mV/div 200 mA/div 500 mA/div IL IOUT = 100 mA No Load EN Floating VIN = 5.5 V Time = 4 Ps/div Time = 40 Ps/div Figure 47. Input Ripple DCM Figure 48. Low Dropout Operation IOUT = 1 A EN Floating 2 V/div 2 V/div IOUT = 100 mA EN Floating VIN VIN VOUT VOUT Time = 40 ms/div Time = 40 ms/div Figure 49. Low Dropout Operation Figure 50. Low Dropout Operation Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 33 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted. 100 100 90 95 80 70 Efficiency (%) 85 80 75 60 50 VOUT = 5 V, fsw = 400 kHz 70 65 60 0 0.5 1 1.5 Series4 VIN = 7 V 12V VIN = 12 V VIN = 24 V 24V VIN = 36 V 36V 2 2.5 3 3.5 4 4.5 IO - Output Current (A) VIN=6V V IN = 7 V 40 30 V VIN=12V IN = 12 V 20 VIN=24V V IN = 24 V 10 0 0.001 5 1 C024 Figure 52. Light Load Efficiency 100 100 95 90 80 70 Efficiency (%) Efficiency (%) 0.1 IO - Output Current (A) 90 85 80 75 65 VOUT = 3.3 V, fsw = 400 kHz 60 0 0.5 1 1.5 2 2.5 60 50 40 30 VIN V IN ==66VV V VIN 12VV IN ==12 V VIN 24VV IN ==24 V VIN 36VV IN ==36 70 3 3.5 4 4.5 Load Current (A) VIN V IN ==66VV V VIN 12VV IN ==12 V VIN 24VV IN ==24 V VIN 36VV IN ==36 20 10 VOUT = 3.3 V, fsw = 400 kHz 0 0.001 5 0.01 0.1 1 Load Current (A) C050 Figure 53. Efficiency vs Load Current C051 Figure 54. Light Load Efficiency 100 60 180 50 150 95 40 120 90 30 90 20 60 85 Gain (dB) Efficiency (%) 0.01 C024 Figure 51. Efficiency vs Load Current 80 75 V 18in IN = 18 V 70 10 30 0 0 ±10 ±30 ±20 ±60 ±30 ±90 ±40 Series1 V IN = 24 V 65 ±50 VOUT = 12 V, fsw = 800 kHz Series3 V IN = 36 V VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A 0.5 1 1.5 2 2.5 3 3.5 4 4.5 IO - Output Current (A) ±120 Phase ±150 ±180 10 0 Gain ±60 60 100 5 1k 10k 100k 1M Frequency (Hz) C053 C024 Figure 55. Efficiency vs Output Current 34 VIN=24V V IN = 36 V VOUT = 5 V, fsw = 400 kHz Phase (£) Efficiency (%) 90 Figure 56. Overall Loop Frequency Response Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 0.5 0.20 0.4 0.15 Output Voltage Normalized (%) Output Voltage Normalized (%) Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted. 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 VIN = 12 V, VOUT = 3.3 V, fsw = 400 kHz -0.4 VIN = 12 V, IOUT = 5 A, fsw = 400 kHz 0.10 0.05 0.00 ±0.05 ±0.10 ±0.15 ±0.20 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Current (A) 4.5 5 0 5 Figure 57. Regulation vs Load Current 10 15 20 25 30 35 40 Input Voltage (V) C054 45 C055 Figure 58. Regulation vs Input Voltage Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 35 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output The TPS54540-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and negative voltage power supply. For a more detailed example, see SLVA317. VIN + Cin Cboot Lo BOOT VIN Cd GND SW R1 + GND TPS54540-Q1 Co R2 FB VOUT EN COMP Rcomp RT/CLK Czero RT Cpole Figure 59. TPS54540-Q1 Inverting Power Supply from SLVA317 Application Note 8.2.3 Split-Rail Power Supply The TPS54540-Q1 device can be used to convert a positive input voltage to a split-rail positive and negative output voltage by using a coupled inductor. Example applications are amplifiers requiring a split-rail positive and negative voltage power supply. For a more detailed example, see SLVA369. VOPOS + VIN Copos + Cin Cboot BOOT VIN GND SW Lo Cd R1 GND + Coneg R2 TPS54540-Q1 VONEG FB EN COMP Rcomp RT/CLK RT Czero Cpole Figure 60. TPS54540-Q1 Split Rail Power Supply Based on the SLVA369 Application Note 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range from 4.5 V to 42 V. This input supply must remain within this range. If the input supply is located more than a few inches from the TPS54540-Q1 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice. 36 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 61 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad. The power pad must be connected to internal PCB ground planes using multiple vias directly under the IC. The SW pin should be routed to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching node, the catch diode and output inductor must be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout has been shown to produce good results and is meant as a guideline. 10.2 Layout Example Vout Output Capacitor Topside Ground Area Output Inductor Route Boot Capacitor Trace on another layer to provide wide path for topside ground Input Bypass Capacitor BOOT Vin UVLO Adjust Resistors Catch Diode SW VIN GND EN COMP RT/CLK FB Frequency Set Resistor Compensation Network Resistor Divider Thermal VIA Signal VIA Figure 61. PCB Layout Example 10.3 Estimated Circuit Area Boxing in the components in the design of Figure 34 the estimated printed-circuit-board area is 1.025 in2 (661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can be done by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 37 TPS54540-Q1 SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support For the TPS54360 and TPS54361 Family Design Excel Tool, see the following: • Design Calculator zip file (SLVC452) For more information about generating a complete design, see the following: • WEBENCH Design Center 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Creating GSM Power Supply from TPS54260 (SLVA412) • Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511 (SLVA464) • Create an Inverting Power Supply from a Step-Down Regulator (SLVA317) • Create a Split-Rail Power Supply with a Wide Input Voltage Buck Regulator (SLVA369) 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 38 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 TPS54540-Q1 www.ti.com SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS54540-Q1 39 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54540QDDAQ1 NRND SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54540Q TPS54540QDDARQ1 NRND SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54540Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of